Power stage of switching converter and voltage regulation module

Abstract

The power stage of the switching converter includes a high-side switch and a low-side switch that are operated by respective drive signals, respectively. The current sensing block generates a sensing current signal that undergoes blanking processing for a first time duration at the beginning of a longer phase of the high-side phase and the low-side phase. The sense current signal is de-blanked at the end of the first duration. The current sensing block generates a first pulse synchronized with the starting point of the longer phase, and the pulse width of the first pulse is equal to the first duration. The gate driver receives the first pulse and generates a delay pulse synchronized with the start point of the longer phase, the pulse width of the delay pulse being equal to the sum of the first duration and the second duration, the gate driver generating a drive signal (for the switch driven in the longer phase), the drive signal has a first logic level for a duration of at least a pulse width of the delayed pulse.

Description

Priority Claim

[0001] This application relates to and claims priority to a co-pending Indian provisional patent application entitled “Current Sensing Blanking in Feedback (T-BLANK)”, serial number: 202341080928, filed on November 29, 2023, attorney file number: AURA-352-INPR, the entire contents of which are incorporated herein to the extent consistent with the description herein. Background Art Technical Field

[0002] Embodiments of the present invention generally relate to switching converters, and more particularly, to a power stage and a voltage regulation module of a switching converter. Related technologies

[0003] As is well known in the related art, a switching converter refers to a component that generates a regulated DC (direct current) voltage from an input power supply by using one or more switches. Typically, a switching converter converts the voltage of an input power supply (input power supply voltage) into a pulse voltage by operating a switch, and then uses capacitors, inductors, and other components to smooth the pulse voltage to generate a regulated DC voltage. By turning on and off switches (e.g., metal oxide semiconductor field effect transistors, MOSFETs), power is provided from the input to the output to generate and regulate the required voltage. Switching converters are used in components such as regulated power supplies, which in turn are used in devices such as computers and mobile phones, which is also well known in the related art.

[0004] A switching converter typically includes a pair of switches that drive an inductor. Each switch is typically implemented as a transistor (e.g., a MOSFET), and the switches are connected in series between an input supply voltage and a reference terminal (e.g., ground). The switch that is coupled closer to the input voltage (the input power source to the converter) is called a high-side switch, while the other is called a low-side switch. The switches are operated by a control circuit that turns on the transistors for consecutive non-overlapping durations so that the currently turned-on switch drives the inductor for the corresponding duration.

[0005] The multiphase switching converter includes a plurality of such switch pairs, and associated circuits for each pair. As is well known in the relevant art, each pair of switches is typically operated in a corresponding phase of the phase sequence, and these switch pairs operate together to produce the desired regulated voltage, and can support higher load currents with higher efficiency and provide other advantages. Each pair of switches in these switch pairs together with the associated circuits is referred to as a power stage of the multiphase switching converter. The phase controller is used to control the specific time at which each power stage produces the required output voltage.

[0006] The phase controller typically needs to communicate the amount of current provided to the output by each power stage via the corresponding inductor, referred to as inductor current information. Therefore, each power stage obtains (senses) the current through the inductor corresponding to the power stage and provides the inductor current information to the phase controller.

[0007] Several aspects of the present invention relate to the measurement of inductor current in a power stage of a switching converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Example embodiments of the present invention will be described with reference to the accompanying drawings which are briefly described below.

[0009] Figure 1 is a block diagram of an example system in which aspects of the invention may be implemented.

[0010] Figure 2 is a block diagram showing details of a voltage regulator module (VRM) in an embodiment of the present invention.

[0011] Figure 3 A block diagram depicting the implementation of blanking duration and minimum off-time in an existing power stage.

[0012] Figure 4 is a diagram showing an implementation of a smart power stage (SPS) in an embodiment of the present invention.

[0013] Figure 5 is a timing diagram (not drawn to scale) illustrating the manner in which T-min-long is timed relative to T-blank in an embodiment of the present invention.

[0014] Figure 6 FIG. 4 is a diagram showing relevant implementation details of a current sensing block and a gate driver in an embodiment of the present invention.

[0015] Figure 7 is a diagram showing implementation details of a delay block in an embodiment of the present invention.

[0016] Fig. 8A FIG. 4 is a timing diagram (not drawn to scale) showing exemplary waveforms generated at various nodes of an SPS in an embodiment of the present invention.

[0017] Figure 8B is a timing diagram (not to scale) illustrating the manner in which the low-side switch remains on during the minimum off-time in an embodiment of the present invention.

[0018] In the drawings, like reference numbers generally indicate identical, functionally similar, and / or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number. DETAILED DESCRIPTION 1. Overview

[0019] Aspects of the present invention relate to a power stage of a switching converter. The power stage includes a high-side switch and a low-side switch operated by a first drive signal and a second drive signal, respectively, the first drive signal and the second drive signal being turned on to drive respective currents through an inductor in a high-side stage and a low-side stage, respectively. A gate driver generates the first drive signal and the second drive signal based on a control signal received from a phase controller, wherein the control signal is received at a first logic level in a first interval and a second logic level in a second interval.

[0020] The current sensing block generates a sense current signal representing an instantaneous magnitude of an inductor current flowing through the inductor, wherein the sense current signal is blanked for a first duration at the beginning of a longer phase of a high-side phase and a low-side phase, the other of which is a shorter phase. The sense current signal is de-blanked at the end of the first duration.

[0021] According to one aspect, the current sensing block generates a first pulse synchronized with the starting point of the longer phase, and the pulse width of the first pulse is equal to the first duration, wherein the gate driver receives the first pulse and generates a delayed pulse synchronized with the starting point of the longer phase, and the pulse width of the delayed pulse is equal to the sum of the first duration and the second duration. In addition, the gate driver generates a drive signal for a switch driven with the longer phase, and the drive signal has a first logic level during a duration of at least the pulse width of the delayed pulse.

[0022] In one embodiment, the low-side phase is the longer phase and the sum represents the minimum desired duration that the low-side switch is in the on state during the low-side phase.

[0023] Several aspects of the present invention are described below with reference to examples for illustration. However, those skilled in the relevant art will recognize that the present invention can be implemented without one or more specific details or using other methods, components, materials, etc. In other cases, well-known structures, materials or operations are not shown in detail to avoid obscuring the features of the present invention. In addition, although only some of these combinations are described herein for the sake of simplicity, the described features / aspects can be implemented in various combinations.

[0024] 2. Example system

[0025] Figure 1 is a block diagram of an example system in which several aspects of the present invention may be implemented. Figure 1As shown, system 100 includes power supply 110, central processing unit (CPU) 120, memory 130, network interface 140, and peripheral device 150. In one embodiment, system 100 corresponds to a computer (desktop computer, laptop computer, etc.), although system 100 may represent other types of systems in other embodiments. It should be understood that system 100 may include more than Figure 1 More or fewer blocks as shown.

[0026] CPU 120 generally represents a processor or system on a chip (SoC), and is shown as receiving a pair of supply voltages (Va and Vb) on respective paths 112A and 112B from power supply 110. As an example, Va may be a smaller voltage than Vb, and may be used to power the core portion of the CPU, which may include an arithmetic logic unit (ALU), a microprogram sequencer, registers, etc. Vb may be used to power the remainder of CPU 120, such as input / output (I / O) units, I / O buffers, on-chip peripherals, etc. CPU 120 provides various signals (all considered to be included in path 121) to power supply 110 that specify, among other things, its power requirements. Examples of such signals may be signals that specify a particular operating mode (in terms of power consumption) such as PS1, PS2, PS3, etc., which refer to "power saving states for improved efficiency."

[0027] Memory 130 represents a memory that may include volatile and non-volatile memory. For example, in a personal computer, the memory may include magnetic memory (hard disk) as well as solid-state memory (RAM, flash memory, etc.). Memory 130 is shown receiving a power supply voltage on path 113 for powering various circuits and blocks therein.

[0028] The network interface 140 is used to provide two-way communication between the system 100 and a computer network (or typically the Internet). The network interface 140 implements a network interface such as Ethernet or Wi-Fi. TM The network interface 140 may also include a network protocol stack to allow communication with other computers on the same local area network (LAN), as well as large-scale network communication through routable protocols such as the Internet Protocol (IP). The network interface 140 receives power on path 114 for powering internal circuits and blocks. The network interface 140 receives / sends from / to external systems and CPU 120 on paths 141 and 124, respectively.

[0029] Peripheral device 150 represents one or more peripheral circuits, such as a speaker, a microphone, a user interface device, etc. Peripheral device 150 receives power on path 115 and communicates with external devices on path 151 .

[0030] The power supply 110 receives power from one or more sources (e.g., a battery) on path 101 and is used to provide a desired power supply voltage on paths 112A, 112B, 113, 114, and 115. In one embodiment, the power supply 110 is designed to include one or more multi-phase DC-DC converters to generate the power supply voltage. The power supply 110 responds to a signal received from the CPU 120 on path 121 to control the multi-phase converter to reduce / increase the current output based on a specific signal (e.g., PS1, PS2, and PS3).

[0031] In this embodiment, the power supply 110 is a voltage regulation module (VRM), sometimes also referred to as a processor power module (PPM), and includes one or more step-down switching (buck) converters to generate several smaller voltages from a higher voltage power supply. However, in other embodiments, other types of DC-DC converters such as boost, buck-boost, hysteretic converters, etc. may be implemented in place of the buck converter. Using the VRM, multiple devices / ICs requiring different power supply voltages can be installed on the same platform, such as a computer motherboard of a personal computer (PC). Therefore, continuing to describe as Figure 2 VRM shown.

[0032] 3. Voltage Regulator Module (VRM)

[0033] Figure 2 1 is a block diagram showing the details of the VRM in an embodiment of the present invention. Figure 1 ) is implemented as a voltage regulation module implemented in the form of a multi-phase switching converter that generates two regulated voltages Va (240) and Vb (250).

[0034] The VRM 110 is shown as including a phase controller 210, smart power stages (SPS) SPSA-1 (220-1) to SPSA-6 (220-6), SPSB-1 ​​(230-1) to SPSB-3 (230-3), inductors 225A-1 to 225A-6 and 227B-1 to 227B-3, and capacitors 226A-1 to 226A-6 and 228B-1 to 228B-3. The power supply Va (240) (power rail-A) is generated by a 6-phase buck converter (there are six SPS: 220-1 to 220-6), while the power supply Vb (250) (power rail-B) is generated by a 3-phase buck converter (there are three SPS: 230-1 to 230-3). The nodes / paths 240 and 250 may correspond to Figure 1Paths 112A and 112B. Figure 2 Also shown are the switch nodes 221-1 to 221-6 of the corresponding power stages. For simplicity, Figure 2 Other power circuits that generate power on paths 113, 114, and 115 are not shown. As is clear from the context, the smart power stages are individually or collectively referred to by reference numerals 220 / 230. Similarly, as is clear from the context, inductors 225A-1 to 225A-3 and 227B-1 to 227B-4 can be collectively or individually represented by corresponding numerals 225 and 227. In the present invention, similar conventions are followed for other blocks / components / signals.

[0035] In an embodiment of the present invention, each power stage and phase controller is implemented as a separate integrated circuit (IC). However, in other embodiments, the implementation of the power stage and phase controller may be different.

[0036] Phase controller 210 works with one or more power stages of the power rail to produce a regulated voltage as an output. Figure 2 In the example shown, the phase controller 210 and one or more power stages of the power rail-A, namely SPSA-1 to SPSA-6, are used to generate a regulated voltage Va (240). Similarly, the phase controller 210 and one or more power stages of the power rail-B, namely SPSB-1 ​​to SPSB-3, are used to generate a regulated voltage Vb (250). Therefore, as shown, Va (240) and Vb (250) are provided as inputs to the phase controller 210 to enable operation of one or more feedback loops within the phase controller 210 to regulate the voltages Va and Vb. The phase controller 210 also receives inductor current information (regarding the current IL, 290 flowing through each inductor 225) from each SPS to implement various operations such as current mode control of voltage regulation, current limiting, short circuit protection, and balancing the current generated by each SPS of the same converter (or "power rail") so that the current from each SPS of the converter is substantially equal in magnitude. Other signals flowing between the phase controller 210 and the SPS are described below.

[0037] The combination of phase controller 210 (corresponding circuitry therein), SPS, and corresponding inductors and capacitors form one "phase" of the power rail. Thus, for example, SPSA-1, inductor 225A-1, capacitor 226A-1, and corresponding portions within phase controller 210 form a single buck converter and one phase of a 6-phase buck converter. It is noted that while each phase is shown as having its own individual capacitor (e.g., 226A-1), in another embodiment, only a single larger capacitor (larger capacitance) may be employed at node 240 (and 250). In other embodiments, multiple capacitors are placed close to the load powered by the corresponding supply voltage.

[0038] The phase controller 210 may be designed to implement automatic phase management (APM). Thus, the specific number of power stages (or phases) operated by the phase controller 210 may vary depending, for example, on the magnitude of the load current drawn from the power rail (e.g., Va 240). Typically, the smaller the load current, the smaller the number of power stages used / operated, and vice versa.

[0039] Each SPS (or "power stage" in general) can be implemented to include a high-side switch, a low-side switch, gate drive circuits for both switches, a temperature monitoring circuit, and an inductor current sensing circuit / block to provide information indicative of the magnitude of the inductor current 290 to the phase controller 210. Although the high-side switch and the low-side switch of the SPS can be viewed as "driving" the inductor, the current provided by the SPS and the corresponding inductor current generally depends on the load current drawn from the supply voltage. Each SPS receives a power supply (which can all be the same power supply) as an input that is connected to the high-side switch (shown in detail in the following section). In Figure 2 In FIG. 1 , the power supply is referenced as 201 and has a voltage Vin. An example value of Vin in an embodiment of VRM 110 is approximately 21 volts (V).

[0040] Each SPS communicates with the phase controller 210 via respective signals PWM, SYNC, CS and TEMP. Thus, SPSA-1 is shown connected to the phase controller 210 via signals / paths PWMA-1 (211), SYNC-A (212), CSA-1 (213) and TEMPA (214). Although Figure 2 214, SPSA-6 communicates with the phase controller 210 via signals PWMA-6, SYNC-A, CSA-6, and TEMP (214). Similarly, SPSB-1 ​​is shown connected to the phase controller 210 via signals / paths PWMB-1 (216), SYNC-B (217), CSB-1 (218), and TEMPB (219). Although the Figure 2 The corresponding connections of signals PWMB-3, SYNC-A and CSB-3 to phase controller 210 are not shown, but SPSB-3 communicates with phase controller 210 through signals PWMB-3, SYNC-A, CSB-3 and TEMPB (219). Other SPSs have similar connections to phase controller 210.

[0041] Signal PWM is an input from the phase controller 210 to the SPS and can be considered as a "phase control signal" that controls the operation (on and off states) of the power switches in the SPS of the corresponding phase. In an embodiment of the present invention, signal PWM is a pulse width modulated (PWM) signal. Therefore, in such an embodiment, signal PWM is a signal with a fixed frequency and a variable duty cycle. The duty cycle of the PWM signal is set by the phase controller 210 and is designed to produce the desired power supply voltage and / or control / change the current provided by that phase. For example, PWMA-1 (211) has a magnitude such as Va240 and a duty cycle required for the current provided by SPSA-1 (220-1). However, in general, depending on the specific implementation details of the power supply 110, signal PWM can have other characteristics.

[0042] For example, in another embodiment, the phase controller 210 may employ a constant on-time control technique to generate Va. Thus, in such an embodiment, the signal PWM is a signal having a variable frequency and a fixed pulse width (constant on-time) (i.e., a pulse frequency modulated signal, although for ease of reference, the abbreviation PWM is still used herein to refer to such a signal). The frequency of the signal is generally proportional to the desired regulated voltage (Va) and the load current. In yet another embodiment, as will be appreciated by those skilled in the relevant art, the signal PWM may vary between a constant on-time variable frequency signal and a fixed frequency pulse width modulated signal based on load current requirements, the desired efficiency of the power supply 110, and other considerations.

[0043] A PWM signal may be generated with a logic high state, a logic low state, or a high impedance (Hi-Z) state. Typically, as is well known in the relevant art, the logic high state and logic low state of the PWM signal correspond to the voltages of the positive and negative rails, respectively, of the power supply of the circuit generating the PWM signal (within error / noise margins), while the high impedance state corresponds to the mid-rail voltage of the power supply (or a voltage window around the mid-rail voltage). However, it will be apparent to those skilled in the relevant art that other conventions may be employed for the three states of the PWM signal. Typically, the PWM signal needs to remain within the above-mentioned voltage window for a predetermined minimum duration of the power stage to correctly identify the high impedance state.

[0044] The signal PWM controls the turning off and on of the high-side switch and the low-side switch of the phase / power stage through a logic high state and a logic low state. In one embodiment, the logic high level of PWMA-1 turns on and off the high-side switch and the low-side switch in SPSA-1, respectively. The logic low level of PWMA-1 turns off and on the high-side switch and the low-side switch in SPSA-1, respectively. The interval in which the high-side switch is turned on can be regarded as the "first stage" (or "high-side stage"), and the interval in which the low-side switch is turned on can be regarded as the "second stage" (or "low-side stage"). The first stage and the second stage are repeated, so they are periodic. The high-side switch and the low-side switch can be regarded as periodically "driving" the inductor in each of the first stage and the second stage, respectively. Note that the terms "first stage" and "second stage" are not to be confused with the phases of the multi-phase converter (as described above).

[0045] The high impedance state of the PWM signal indicates to the power stage that the power stage will not operate in generating an output voltage, i.e., is "inactive". Therefore, when the PWM is in a high impedance state, both the high-side switch and the low-side switch of the power stage are turned off, and the power stage can enter a low power / power-off mode. Typically, the phase controller 210 is designed to generate the PWM signal in a manner that can indicate three states, one of which indicates that the corresponding power stage will be in an inactive state. It will be apparent to those skilled in the relevant art that this three-state capability can be implemented in alternative manners. As an example, the phase controller 210 can be implemented to generate a PWM as a conventional binary signal, wherein if the PWM signal is turned off (i.e., not generated at all), the power stage is implemented to recognize a high impedance state.

[0046] As is well known in the art, the PWM signals to each SPS of the same converter may be staggered, i.e., delayed in phase with respect to each other, so that the two high-side switches of a common track (i.e., in each SPS) are not turned on at the same time. The reason for adopting this technique is, for example, to ensure that the peak instantaneous current drawn from Vin is always relatively low.

[0047] The signal TEMP is an output (e.g., a voltage) from the SPS to the phase controller 210 and provides information about the temperature in the SPS. The phase controller 210 can process the TEMP signal (or the information included therein) to regulate the current provided by that phase, or to shut down the VRM in the event of a fault. The TEMP output lines for each phase of the converter are connected together, and a single input (e.g., TEMPA 214) is connected to the phase controller 210. The maximum value of the TEMP output of the driving phase is on the wired connection.

[0048] The SYNC signal is an input to the SPS and can be used by the phase controller 210 to wake up the SPS when the power supply 110 is powered on, and is also used to indicate the power mode (e.g., PS2, PS3) of the multi-phase converter, i.e., the output current requirement. Typically, all SPSs of the same converter share a single SYNC signal (e.g., SYNC-A 212).

[0049] The CS (current sense) signal is an input from the SPS / phase to the phase controller 210 and includes information about the instantaneous magnitude of the inductor current for that phase. This information can be in the form of current, voltage, digital value, etc., depending on the specific implementation of the power stage and the phase controller 210. The CS block in the SPS implements the current sensing operation and sends the CS signal to the phase controller 210.

[0050] In an embodiment of the present invention, the current sensing block of the power stage sends the sensed inductor current information to the phase controller 210 in the form of a current, which may have the same magnitude as the inductor current or (more typically) a scaled-down version (in terms of magnitude) of the inductor current. Accordingly, in this embodiment, the phase controller 210 is designed to receive information in the form of a current, and when a scaled version is used, the scaling factor is known to the phase controller 210 and the (corresponding) power stage.

[0051] As described above, each SPS provides its CS signal 213 to the phase controller 210 to enable the phase controller 210 to perform various operations, such as current mode control for voltage regulation, current limiting, short circuit protection, responding to overcurrent conditions, and balancing the current generated by each SPS of the buck converter so that the current magnitudes from each SPS of the converter are substantially equal.

[0052] One problem with measuring (or sensing) the inductor current occurs when the (high-side or low-side) switch is turned on for only a very short duration. Typically, the duration that the high-side switch and the low-side switch are turned on in each phase (the first phase and the second phase described above) depends on the difference between Vin and Va (or the regulated output voltage in general). If Vin is much greater than Va (for example, Vin equals 21V and Va is 1V), the first phase (also called the charging phase) has a very short duration, while the second phase (also called the discharging phase) has a relatively long duration.

[0053] Typically, it may be difficult to measure the inductor current with reasonable accuracy during a very short phase (hereinafter referred to as the "shorter phase", such as the first phase described above). On the other hand, it may be easier to measure the inductor current fairly accurately during a long phase (hereinafter referred to as the "longer phase", such as the second phase described above). An example of such a very short duration is when the duty cycle of the PWM signal is approximately 5% and the period of the PWM signal is 1.6 microseconds (μs). The duration of the longer phase is greater than or equal to the duration of the shorter phase. When the durations of the longer phase and the shorter phase are equal, the inductor current can be measured in either phase.

[0054] Typically, a blanking duration is introduced between the end point of the shorter phase and the longer phase that follows it to allow transients in the CS block to stabilize. During the blanking duration, the output of the CS block is blanked, i.e., the output of the CS block is disconnected from the CS pin 213. The magnitude of the current sensed during the blanking duration (CS signal) can be maintained at the last measured magnitude of the inductor current before the blanking duration begins (scaled or otherwise). At the end of the blanking duration until the end of the longer phase, the output of the CS block is not blanked, i.e., the output of the CS block is connected to the CS pin 213. The magnitude of the sensed current (CS signal) during the non-blanking duration is the magnitude of the inductor current (or a scaled-down version thereof).

[0055] In order to measure the inductor current in the longer phase reasonably reliably, the "minimum duration that the switch driven in the longer phase needs to be turned on" (hereinafter referred to as "T-min-long duration") should be greater than the blanking duration by "some time interval" (hereinafter referred to as "minimum post-blanking duration"). As an example, if the blanking duration is 120 nanoseconds (ns) and the minimum post-blanking duration is 30ns, then T-min-long can be at least 150ns.

[0056] If the above conditions are not met, the inductor current cannot be reliably measured, and thus operations that rely on inductor current measurement (such as current limiting, overcurrent protection, etc. described above) may fail, leading to undesirable results that are unacceptable in at least some environments.

[0057] As follows about Figure 3 An example existing power stage is briefly described, and the above conditions may not be met in existing implementations of the power stage.

[0058] 4. Existing power levels

[0059] Figure 3 1 is a diagram depicting relevant implementation details of an existing power stage and problems associated with the implementation. Figure 3As shown, the prior art power stage 320 includes a gate driver 310 and a current sensing block 340. The gate driver 310 is shown to include a delay block-1B 305 and a drive (DRV) circuit 315. The current sensing block 340 is shown to include a delay block-1A 325 and a measurement circuit 335. Figure 3 Also shown in FIG. 3 is a current sensing pin 313 and a switch node 329. Figure 3 Other components within the conventional power stage 320, such as a high-side switch, a low-side switch, etc., are not shown.

[0060] The gate driver 310 receives the signal PWM 311 and responds to the logic level of PWM 311 to generate a gate driver 310 in a corresponding path ( Figure 3 The DRV circuit 315 generates a suitable voltage (drive signal) on the DRV circuit 315 (not shown) to turn on or off the high-side switch and the low-side switch (included in the power stage 320) in the corresponding intervals indicated by the PWM 311. Assuming that the second phase is a longer phase, the delay block-1B 305 generates a pulse T-min-OFF (307) with a pulse width corresponding to the above-mentioned duration T-min-long. The DRV circuit 315 uses the pulse 307 in combination with the PWM signal 311 to generate a drive signal to turn on / off the high-side switch and the low-side switch.

[0061] The current sensing block 340 measures / senses the inductor current and provides current sensing information to the phase controller on path 313. The delay block-1A 325 generates a pulse T-blank (327) internal to the current sensing block 335, which has a pulse width corresponding to the blanking duration described above. The measurement circuit 335 uses pulse 327 to disconnect the output of the block 335 from the CS pin 313 for the blanking duration.

[0062] The magnitude of the desired delay produced by the delay block-1A 325 and the delay block-1B 305 may be fixed, having a predetermined value configured in the existing power stage 320, with the magnitude of the desired delay of the delay block-1B 305 being greater than the magnitude of the desired delay of the delay block-1A (325). The delay blocks 305 and 325 may be implemented using a resistor capacitor (RC) delay circuit, a delay line, or the like.

[0063] The delays generated by the delay blocks 305 and 325 may vary due to reasons such as process, voltage and temperature (PVT) variations, aging, device mismatch, etc. Since the delays generated by the delay blocks 305 and 325 are independent of each other (i.e., in the time domain, the delay generated by one delay block does not depend on or correlate with the delay generated by the other delay block), such variations in the delays generated by one or both of the delay blocks 305 and 325 may result in (T-min-OFF duration minus T-blank duration) being insufficient to reliably measure the inductor current. In addition, any offset in the start times of T-min-OFF and T-blank may also cause the above-mentioned problems.

[0064] In order to minimize the above changes, existing solutions can be adopted, such as increasing the size of the device, adding additional voltage and / or current sources, or using redundant and fault-tolerant circuits. However, such existing solutions may lead to increased area, power and complexity of IC design.

[0065] As described below, embodiments of the present invention overcome the above-mentioned problems.

[0066] 5. Smart Power Stage (SPS)

[0067] Figure 4 FIG. 4 is a diagram showing the implementation of SPS in an embodiment of the present invention. Figure 4 The SPSA-1 (220-1) is shown in detail. Other SPSs may also be implemented similar to the SPSA-1. The SPSA-1 shown includes a gate driver 410, a high-side (HS) switch 420, a low-side (LS) switch 430, a current sensing block 450, and an overcurrent detector 460. Figure 4 Also shown are inductor 225A-1 and capacitor 226A-1. Node 240 provides a supply voltage Vout. Current "IL" represents the inductor current through inductor 225A-1, and current "Ics" 459 represents the sense current provided as an output on CS pin 213.

[0068] It should be noted here that Figure 4 Only components relevant to understanding the present invention are depicted. It should be understood that SPS220-1 may include Figure 4 More or fewer blocks (modules) may be shown. For example, although for simplicity Figure 4 Not shown, but the power stage 220 - 1 may include various other blocks (modules) / circuits, such as temperature sensors, level converters, etc.

[0069] In the exemplary embodiment, it is assumed that the first phase (when the HS switch 420 is turned on and the LS switch 430 is turned off) is the "shorter" phase, and the second phase (when the HS switch 420 is turned off and the LS switch 430 is turned on) is the above-mentioned "longer phase". When the first / HS phase is the longer phase and the second / LS phase is the shorter phase, and the circuits within the power stage 220-1 have corresponding changes, various aspects of the present invention are also applicable, which will be apparent to those skilled in the art by reading the disclosure herein.

[0070] Gate driver 410 generates drive signals en-HS 412 and en-LS 413 based on signal PWMA-1 (211) received from phase controller 210. Gate driver 410 is also shown receiving signal 497 (OC) and T-blank (453), which will be described in detail below.

[0071] HS switch 420 and LS switch 430 are each shown as an N-channel MOSFET (metal oxide semiconductor field effect transistor), where gate driver 410 drives the gate terminal of the MOSFET. Alternative embodiments may implement the switches in different ways. Figure 4 In the example shown, when PWM 211 is a logic high level, gate driver 410 generates corresponding appropriate voltages on paths 412 (en-HS) and 413 (en-LS) to turn on MOSFET 420 and turn off MOSFET 430. Therefore, signals en-HS (412) and en-LS (413) can be considered as 'drive signals' that drive the respective transistors. When PWM 211 is a logic low level, gate driver 410 generates corresponding appropriate voltages on paths 412 and 413 to turn off MOSFET 420 and turn on MOSFET 430. When PWM 211 is a high impedance state, gate driver 410 generates corresponding appropriate voltages on paths 412 and 413 to turn off both MOSFETs 420 and 430.

[0072] The gate driver 410 generates en-LS (413) which is opposite to en-HS (412), but has "guard" intervals on either side of en-HS (412) to ensure that the HS switch and the LS switch are not on at the same time in any interval, thereby preventing a short circuit (breakdown condition) from Vin to ground. The gate driver 410 receives a logic signal (497) indicating an overcurrent condition. If an overcurrent condition exists (logic signal 497 is logic high), the gate driver 410 generates corresponding appropriate voltages on paths 412 and 413 to turn off both MOSFET 420 and MOSFET 430. In addition, the gate driver 410 can communicate with the phase controller 210 regarding the overcurrent condition on the appropriate pin / path.

[0073] The current sensing block 450 is used to determine the magnitude (eg, instantaneous magnitude) of the inductor current (IL290, through the inductor 225A-1), with or without scaling, and provides information indicative of the magnitude of the inductor current as an output on the node 213. Figure 6 In the described embodiment, the current sensing block 450 employs sensing of the voltage drop across the LS switch 430 for directly obtaining the magnitude of the inductor current (or a scaled-down version thereof) when the LS switch is on, and "constructing" (or emulating) the magnitude of the inductor current when the HS switch 420 is on. The current sensing block 450 generates a pulse T-blank on path 453 having a pulse width equal to the blanking duration described above.

[0074] The overcurrent detector 460 is used to determine whether the inductor current exceeds the maximum allowed or expected value. The overcurrent detector 460 compares the received inductor current (Ics) information 213 (of the low-side stage) and the current I-lim 492 (or information / voltage indicating the current) representing the maximum allowed / expected inductor current. I-lim 492 can be received from the phase controller 210, or can be configured in a known manner within the SPSA-1 (220-1) at design time. Based on Ics 213 and I-lim492, the overcurrent detector 460 generates a logic signal 497 indicating whether an overcurrent condition exists. If an overcurrent condition exists, the overcurrent detector 460 asserts the logic signal 497 as a logic high (HIGH). Otherwise, the overcurrent detector 460 maintains the signal (497) in a de-asserted (logic low (LOW)) state. The overcurrent detector 460 can be implemented in a known manner.

[0075] It should be noted here that overcurrent detection (and protection) can be performed in both the shorter phases and the longer phases described above. For example, if the first phase (HS switch 420 is turned on) is a shorter phase, overcurrent detection can be performed in these phases to address fault / error conditions (such as when PWMA-1, 211 continues to be in a logic high state from the beginning of the first phase, causing the inductor current to increase to an unacceptably high level).

[0076] As mentioned above, T-min-long should be greater than the blanking duration, and the minimum post-blanking duration. According to one aspect of the present invention, the above condition is ensured by generating T-min-long relative to T-blank. Specifically, as will be referred to below Figure 5 As described, the delay corresponding to the minimum post-blanking duration begins after the end of the blanking duration.

[0077] 6. Generation of T-min-long relative to T-blank

[0078] Figure 5 To illustrate T-min-long (411, Figure 4 4. A timing diagram (not shown) showing the relative timing of T-blank (453) and T-blank (454). Figure 5 The waveforms of PWMA-1 (211), T-blank (453), T-min-long (411), en-LS (413), IL (290) and Ics (459) are described.

[0079] When PWMA-1 is logic high (time interval t502-t507), HS switch 420 is turned on (LS switch 430 is turned off), and current flows from Vin to the load (connected to the Va node, but not shown) via HS MOSFET 420 and inductor 225A-1 with a rising slope. When PWMA-1 is logic low (time interval t507-t519), LS switch 430 is turned on (HS switch 420 is turned off), and the inductor current flows in the loop formed by LS switch 430, inductor 225A-1 and the load with a falling slope. One cycle of the PWMA-1 signal may generally be referred to as a "cycle" of the operation of the SPS or switching converter.

[0080] The starting edge (here, the rising edge) of pulse T-blank (453) (at t507) is shown to be generated synchronously with the falling edge of PWMA-1 (211), which corresponds to the start of the second phase in the illustrative embodiment. Note that the term "synchronous" used to refer to the timing relationship of one or more signals means that ideally, one or more signals (e.g., here, the falling edge of signal PWM-1 (211) and the starting edge of pulse T-blank, 453) occur at the same time. In practice, there may be some delay between the occurrence of one or more signals (intentional, such as a guard interval, etc., or otherwise, such as a propagation delay, etc.).

[0081] Typically, the starting edge of pulse T-blank (453) is generated synchronously with the start of the longer phase. Therefore, when the first phase is the longer phase, the starting edge (211) of pulse T-blank is generated synchronously with the rising edge of PWMA-1.

[0082] The pulse width (t507-t511) of T-blank (453) corresponds to the blanking duration described above. The end of the T-blank duration (at time t511) triggers the start of the minimum post-blanking duration (t511-t513). Thus, T-min-long (411) is shown to have a pulse width (t507-t513) equal to the T-blank duration plus the minimum post-blanking duration, thereby preventing the duration of T-min-long from being less than or equal to the duration of T-blank. The minimum post-blanking duration indicates that T-min-long (411) should ideally exceed the duration of T-blank (453) duration in order to be able to reliably measure the inductor current over a longer period.

[0083] Signal en-LS (413) is generated as logic low in the first phase (time interval t502-t507). Signal en-LS transitions to logic high in synchronization with the falling edge of signal PWMA-1 (211) and remains at logic high until the end of the T-min-long duration or the end of the duration that PWMA-1 (211) is logic low, whichever is longer. Figure 5 , it is shown that en-LS (413) switches to logic low at time t519 (ie, the duration of PWMA-1, 211 being logic low ends).

[0084] Point 531 on waveform Ics (459) at time t507 represents the (simulated) magnitude of the inductor current at the end of the first phase and the beginning of the second phase. Waveform Ics (459) maintains / holds the previously measured value (531) until the end of the blanking duration (at time t511), as shown by point 532. At the end of the blanking duration, at time t511, waveform Ics (459) represents the magnitude of the actual inductor current (or a scaled version thereof).

[0085] Since T-min-long is generated in a serial manner relative to T-blank (i.e., the end of the T-blank duration triggers the start of the above-mentioned minimum post-blanking duration), it can be ensured that the duration of T-min-long is greater than the duration of T-blank. This overcomes the problem of Figure 3 At least one or more disadvantages of the prior art power stages are noted (eg, as described above). Thus, the SPS 220 - 1 can reliably measure the inductor current over a longer period.

[0086] Next, implementation details of the gate driver 410 and the current sensing block 450 in an embodiment of the present invention are provided.

[0087] 7. Current sensing block and gate driver

[0088] Figure 6 Schematic diagram showing implementation details of the gate driver and current sensing block in an embodiment of the present invention. The current sensing block 450 shown includes circuits 610 and 630. The gate driver 410 shown includes a delay block B (605-B), an inverter 680 and an OR gate 675. It should be noted here that details of the circuits 610, 630 and the gate driver 410 related to the present invention have been provided and described. However, it should be understood that alternative embodiments of the gate driver 410 and the current sensing block 450 may use more or fewer components and circuits. Reference numeral 299 represents grounding.

[0089] Circuit 610 generates pulse T-blank 453 from signal PWMA-1 received on path 211, beginning synchronously with the start of the longer phase (the second phase in the illustrative embodiment).

[0090] Circuit 630 measures (or senses) the second phase (i.e., when LS switch 430 ( Figure 4 ) is turned on and drives the inductor front current, the HS switch 420 is turned off in the second phase) and the inductor current IL (for clarity, the Figure 2 The circuit 630 regenerates the inductor current (i.e., generates a copy of the inductor current) in the second phase. Figure 5 It can be seen that the inductor current in the second phase has a decreasing trend (negative slope). The current sensing block 450 provides a replica of the inductor current in the second phase at / on the node / path CSA- 1 ( 213 ), as described below.

[0091] The series connection of transistors 660 and 670 across power supply node 202 (Vcc) and ground 299 is referred to herein as an "output block." Transistor 660 is shown as a P-channel metal oxide semiconductor field effect transistor (PMOS), and transistor 670 is shown as an N-channel metal oxide semiconductor field effect transistor (NMOS). Power supply Vcc may be provided to SPSA-1 (and other SPSs) by phase controller 210, or generated in VRM 110 in a known manner.

[0092] The circuit 610 shown includes a delay block-A 605-A and an XOR gate 615. The delay block-A 605-A generates a delayed PWM signal 607 from the input signal PWMA-1 received on the path 211. In the illustrative embodiment, the delay block-A 605-A is used to delay only the falling edge of PWMA-1 211 by the amount of the above-mentioned blanking duration. Therefore, the rising edges of PWMA-1 211 and the delayed PWM signal 607 are synchronized with each other, while the falling edge of the delayed PWM signal 607 is delayed by the blanking duration relative to the corresponding falling edge of PWMA-1 211.

[0093] In one embodiment, the following reference is used Figure 7 The RC delay circuit described implements the delay block-A 605-A. The magnitude of the duration of T-blank (453) may be fixed and may be configured at design time in the power supply 110, or as an input from an external device (not shown) or as a user input (received through corresponding means not shown). In the illustrative embodiment, the magnitude of the duration of T-blank (453) is equal to 120ns.

[0094] The delayed PWM signal 607 and PWMA-1211 are provided as inputs to an XOR gate 615 to generate pulse T-blank453.

[0095] Although the illustrative embodiment describes a specific logic operation (XOR) using delayed PWM signal 607 and PWMA-1211 to generate T-blank453, various aspects of the present invention are equally applicable when alternative logic operations (with corresponding signals) are used to generate T-blank (453), which will be apparent to those skilled in the art from reading the disclosure herein.

[0096] Circuit 630 of current sense block 450 is shown including amplifier 650, transistors 660 and 670, capacitors 658 and 659, switches 635, 636, 653 and 654, inverter 631 and AND gate 633. LS switch 430 is also shown for clarity, although it is not typically part of circuit 630.

[0097] Amplifier 650 receives the voltage across LS switch 430 in the second stage and provides an amplified output voltage as an output. The amplifier 650 shown is a fully differential amplifier, by way of example only. Other amplifier types and topologies may also be used alternatively. In one embodiment, amplifier 650 is a fully differential amplifier with a gain determined by a feedback network (not shown, but using, for example, two pairs of resistors known in the art) that will be used to operate amplifier 650 in a closed-loop mode. In this embodiment, the fully differential amplifier receives the voltage across LS switch 430, which is connected across the negative (-) input terminal connected to path 435 and the positive (+) input terminal connected to ground 299. The fully differential amplifier 650 provides the corresponding amplified difference as an output voltage across terminals 651 (+) and 652 (-).

[0098] Switches 635 and 636 are controlled by control signals en-LS-b (413') and en-LS (413), respectively. Control signal en-LS-b 413' is the logical inverse of control signal en-LS (413). When LS switch 430 is off and HS switch 420 is on, switch 635 is on. When LS switch is on, switch 635 is off. On the other hand, when LS switch is on, switch 636 is on, and when LS switch is off, switch 636 is off.

[0099] The control signal non-blanking output 634 causes each of the switches 653 and 654 to turn on at the end of the blanking duration and turn off at the end of the corresponding second phase, and the switch is turned on for the duration from the end of the blanking phase to the end of the corresponding second phase ( Fig. 8A The device remains turned on during the time interval T-LS-2).

[0100] Despite Figure 6 4, but a comparator (not shown) within the overcurrent detector 460 may also use the control signal non-blanking output 634 to only blank the output 634 during the duration from the end of the blanking duration to the end of the corresponding second phase ( Fig. 8A Overcurrent detection is enabled during the time interval T-LS-2).

[0101] LS switch 430 is switched on by signal 'en-LS' ( Figure 4413) is turned on (and therefore conducting). Therefore, by measuring / obtaining the voltage across the LS switch 430 in the second phase, the circuit 630 senses the current (IL) through the inductor 225A-1. For example, if the LS switch has a 2.5 milliohm resistance Ron and provides an inductor current of 40A, the voltage across the LS switch 430 will be 100 millivolts (mV). Detecting the voltage across the LS switch 430 is a non-destructive method of detecting current. However, other techniques for obtaining a measurement of the magnitude of the inductor current in the second phase may also be used, which will be apparent to those skilled in the art after reading this disclosure.

[0102] Delay block-B 605-B (of gate driver 410) generates a pulse T-min-long on path 411 from an input pulse T-blank received on path 453, the pulse width of T-min-long being equal to the sum of the duration of T-blank 453 and the above-mentioned minimum post-blanking duration. In other words, the end of the T-blank duration triggers the start of the minimum post-blanking duration, so that the duration of T-min-long exceeds the duration of T-blank by the minimum post-blanking duration.

[0103] In the illustrated embodiment, the delay block-B 605-B is used to delay the ending edge of the pulse T-blank 453 only by the amount of the above-mentioned minimum sample. Therefore, the starting edges (e.g., rising edges) of the pulses T-blank 453 and T-min-long 411 are synchronized with each other, while the ending edge (e.g., falling edge) of T-min-long 411 is delayed by the minimum post-blanking duration relative to the corresponding ending edge of T-blank 453.

[0104] In one embodiment, the following reference is used Figure 7 The RC delay circuit described is used to implement the delay block-B 605-B. Considering the process corner, the operating voltage and the ambient temperature, the magnitude of the minimum post-blanking duration can be determined based on the simulation results at the time of design, and the magnitude of the minimum post-blanking duration can be configured in the power stage 220, or the magnitude of the minimum post-blanking duration is received as an input from an external device (not shown) or as a user input (via a corresponding device not shown). In the illustrative embodiment, the magnitude of the minimum post-blanking duration is equal to 30ns. Therefore, the duration of the pulse T-min-long is equal to 120ns plus 30ns, that is, 150ns.

[0105] Signals T-min-long 411 and PWM-b 211 ′ (representing the logical inverse of PWMA- 1 , 211 ) are provided as inputs to an OR gate 675 to generate signal en-LS 413 .

[0106] Although the illustrative embodiment depicts the circuit for generating pulse T-blank 453 as being internal to the current sensing block 450 and the circuit for generating pulse T-min-long 411 as being internal to the gate driver 410, in alternative embodiments, the logic blocks / circuits for generating one or both of pulses T-blank 453 and T-min-long 411 may be implemented external to the current sensing block 450 and / or the gate driver 410, as would be apparent to a person skilled in the art from reading the disclosure herein.

[0107] Now combine the reference Figure 6 and Fig. 8A The combined operation of the circuits 610 and 630 and the gate driver 410 in the first and second phases is described.

[0108] 8. Example Operation of SPS

[0109] Fig. 8A FIG. 4 is a timing diagram (not drawn to scale) showing exemplary waveforms generated at various nodes of SPS 220 in an embodiment of the present invention. Fig. 8A Example waveforms of PWMA-1 (211), delayed PWM signal (607), T-blank (453), T-min-long (411), PWM-b (211'), and en-LS (413) are shown. (A) Phase I:

[0110] In operation, LS switch 430 is switched on at the beginning of the first phase (eg, Fig. 8A LS switch 430 is turned off by drive signal en-LS 413 at the beginning of the next second phase (e.g., Fig. 8A When LS switch 430 is off, switch 635 is on (and switch 636 is off), and thus the inputs of amplifier 650 are shorted to each other and to ground 299. Alternatively, the inputs of amplifier 650 may all be connected to the same reference potential. Therefore, the voltage at the SW node is not sampled in the first phase. Switches 653 and 654 are off during the first phase. Simulation circuit ( Figure 6 ) estimates the inductor current in the first phase without sensing or measuring the inductor current in the first phase and provides a simulated current on path CS213. (B) Phase II:

[0111] LS switch 430 starts at the beginning of the second phase (eg, Fig. 8AAt the beginning of the second phase and throughout the duration, when the LS switch 430 is turned on ( Fig. 8A During the time interval t803-t815 in the blanking duration), switch 635 is turned off and switch 636 is turned on. Thus, at the beginning of the second phase, the voltage across LS switch 430 is provided to amplifier 650. However, the output on CSA-1 is disabled for the duration of T-blank 453 to prevent pending / transient outputs from being provided on CSA-1. Switches 653 and 654 are turned on at the end of the blanking duration and are turned on for the duration from the end of the blanking duration to the end of the corresponding second phase ( Fig. 8A The device remains turned on during the time interval T-LS-2).

[0112] As described above, the blanking duration is the interval during which the amplifier 650 is turned on (starting from the beginning of T-blank) but its output has not yet stabilized and does not correctly reflect the input. This is because the bandwidth (BW) of the differential amplifier 650 is limited. Therefore, it may take some time for the amplifier 650 to reach steady-state operation and correctly produce an output from turning on (e.g., at the beginning of T-LS). The blanking duration can be set by the designer / user based on the BW of the differential amplifier 650.

[0113] In the second phase, voltages 651 and 652 cause transistors 660 and 670 to source and sink respective currents based on the particular magnitudes of voltages 651 and 652, the input voltages of the amplifier. Thus, the output block effectively acts as a voltage-to-current converter. Thus, a difference current (represented by Ics) between the current sourced by transistor 660 and the current sunk by transistor 670 is provided on path 213 (CSA-1). The differential current is a replica (which may be scaled or actual) of the inductor current in the second phase (or more specifically, for the portion corresponding to the end of the blanking interval to the end of the second phase).

[0114] Additionally, capacitors 658 and 659 will charge / discharge based on the voltages on paths 651 and 652, respectively, and at the end of the second phase (e.g., Fig. 8A At time t815 in the second phase) the inductor 213 and the inductor 214 will each have a voltage across them that represents (or corresponds to) the differential current on path 213 at the end of the second phase. In other words, capacitors 658 and 659 are able to store (or hold) 'information' (in these two voltages) representing the inductor current at the end of the second phase (e.g., time t815). This "valley hold" capability of circuit 630 is desirable because, immediately following the first phase, the simulation circuit ( Figure 6Such initial conditions are not shown in Figure 4. For example, the simulation circuit of the current sensing block 450 is used to create a replica of the inductor current in the first phase without sensing or measuring the inductor current in the first phase. The simulation circuit can be implemented, for example, as described in US Publication No.: US20240030811A1.

[0115] In the second phase, the gate driver 410 delays the falling edge of the corresponding pulse T-blank (453) by the minimum post-blanking duration ( Fig. 8A The gate driver 410 generates a pulse T-min-long (411) at the beginning of the second phase ( Fig. 8A At t803 and t817 in the figure, the drive signal en-LS (413) generates a logic high and is kept in the state of T-min-long (411) or the state of PWMA-1 (211) being a logic low ( Fig. 8A The en-LS(413) is maintained at logic high for t803-t815 in the above table, whichever is longer. Fig. 8A , en-LS (413) is shown to be at logic high during duration t803-t815 because PWMA-1 (211) is at logic low for a duration longer than T-min-long (411).

[0116] Even if the signal PWMA-1 (211) changes to logic high before the duration T-min-long (411) ends, the gate driver 410 still keeps en-LS (413) at logic high for at least the duration T-min-long (411). Figure 8B shown.

[0117] Figure 8B A timing diagram (not drawn to scale) is shown showing how the low-side switch remains on during the minimum off time in an embodiment of the present invention. Time intervals t821-t823 and t828-t834 represent the first phase, and time intervals t823-t828 and t834-t838 represent the second phase.

[0118] In the second phase t823-t828, the time interval t823-t826 is the blanking duration, and t823-t830 is the minimum time (T-mmin-long, 411) that the LS switch should be turned on.

[0119] However, at time t828, PWMA-1 (211) is shown to transition to logic high before the end of duration T-min-long (411). Through the operation of OR gate 675 within gate driver 410, en-LS (413) remains at logic high until the end of duration T-min-long (411), i.e., until time t830.

[0120] Next, implementation details of delay blocks 605 -A and 605 -B in an embodiment of the present invention are provided.

[0121] 9. Delay Block

[0122] Figure 7 FIG. 6 is a diagram showing implementation details of the delay block 605 in an embodiment of the present invention. In one embodiment, the delay block 605 corresponds to Figure 6 Both delay blocks 605-A and 605-B are shown. The delay block 605 shown includes an asymmetric inverter (including transistors 710, 720, resistor 750 and capacitor 760) and a symmetric inverter (including transistors 730 and 740). Signal Signal-in (701) represents an input signal whose falling edge is only delayed by delay block 605 to generate signal signal-out (779). Therefore, when delay block 605 is implemented as delay block 605-A, signal signal-in (701) corresponds to signal PWMA-1 (211), while signal signal-out (779) corresponds to delayed PWM signal 607.

[0123] The RC time constant of the RC circuit formed by resistor R750 and capacitor 760 determines the slope of the rising edge of the signal input at node 759. The switching voltage of the symmetrical inverter is fixed and can be designed to be midway between Vcc (202) and ground 299. Therefore, the RC circuit produces an exponential ramp, while the threshold comparison of the comparator defines the decision threshold and generates an output edge (of signal output 759) when the threshold is crossed.

[0124] The values ​​of R 750 and C 760 are selected so that the delay blocks 605 provide the desired delay. Thus, in the illustrative embodiment, the R and C values ​​of delay block A (605-A) are designed to provide a delay of 120 ns (the duration of T-blank, 453), while the R and C values ​​of delay block B (605-B) are designed to provide a delay of 30 ns (the minimum post-blanking duration described above).

[0125] Although the illustrative embodiments depict RC delay circuits to achieve the desired delay, aspects of the present invention are equally applicable when alternative delay generating circuits / components (e.g., counters, delay lines, timers, etc.) are employed, as will be apparent to those skilled in the art from a reading of the disclosure herein.

[0126] One benefit of this solution is that since the minimum post-blanking duration starts after the blanking duration ends, T-min-long being less than or equal to the blanking duration can be prevented even taking into account any variation in the delays produced by blocks 605-A and 605-B. According to aspects of the present invention, there is no longer a constraint that the two delays must start at the same time. Therefore, compared to the prior art described above, this solution further reduces the likelihood of not meeting the condition.

[0127] In this way, aspects of the present invention enable measurement of inductor current in a power stage of a switching converter.

[0128] 10. Conclusion

[0129] References in this specification to "one embodiment," "an embodiment," or similar language mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases "in one embodiment," "in an embodiment," and similar language in this specification may, but do not necessarily, all refer to the same embodiment.

[0130] Although in Figure 1 , Figure 2 , Figure 4 , Figure 6 and Figure 7 In the illustrations of , although terminals / nodes are shown as having direct connections to various other terminals (i.e., "connected to"), it should be understood that additional components (as appropriate to the particular circumstances) may also be present in the path, so the connections may be viewed as "electrically coupled" to the same connection terminals.

[0131] It should be understood that the specific types of transistors described above (e.g., NMOS, PMOS, etc.) are provided for illustration only. However, alternative embodiments using different configurations and transistors will be apparent to those skilled in the relevant art by reading the disclosure provided herein. For example, an NMOS transistor may be replaced with a PMOS (P-type MOS) transistor, while also swapping the connections to the power and ground terminals.

[0132] Therefore, in this application, the power and ground terminals are referred to as constant reference potentials, the source (emitter) and drain (collector) terminals of the transistor (although providing a current path when turned on and an open path when turned off) are referred to as current terminals, and the gate (base) terminal is referred to as the control terminal.

[0133] Although various embodiments of the present invention have been described above, it should be understood that these embodiments are only examples and do not impose any limitations on the present invention. Therefore, the breadth and scope of the present invention should not be limited only by the embodiments described above, but should only be defined according to the following claims and their equivalents.

Claims

1. A power stage of a switching converter, comprising: a high-side switch and a low-side switch respectively operated by a first drive signal and a second drive signal, the first drive signal and the second drive signal being turned on to drive respective currents through the inductors in the high-side stage and the low-side stage, respectively; a gate driver for generating the first drive signal and the second drive signal based on a control signal received from a phase controller, wherein the control signal is received at a first logic level in a first interval and a second logic level in a second interval; and a current sensing block for generating a sensed current signal; wherein the sensed current signal represents an instantaneous magnitude of an inductor current flowing through the inductor; the sensed current signal is blanked for a first duration at the beginning of the longer of the high-side phase and the low-side phase, the other of the high-side phase and the low-side phase being a shorter phase, and the sensed current signal is de-blanked at the end of the first duration; the duration of the longer phase is greater than or equal to the duration of the shorter phase; wherein the current sensing block generates a first pulse synchronized with the starting point of the longer phase, and a pulse width of the first pulse is equal to the first duration, wherein the gate driver receives the first pulse and generates a delayed pulse synchronized with the starting point of the longer phase, and the pulse width of the delayed pulse is equal to the sum of the first duration and the second duration, The gate driver generates a drive signal for a switch driven with the longer phase, the drive signal having the first logic level during a duration of at least the pulse width of the delayed pulse.

2. The power stage according to claim 1, wherein: The low side phase is the longer phase; Therein, the sum represents the minimum desired duration that the low-side switch is turned on in the low-side phase.

3. The power stage of claim 1, wherein: The current sensing block includes: a first delay block for receiving the control signal and generating a delayed control signal by delaying a high-to-low transition of the control signal by the first duration; an XOR gate, configured to receive the control signal and the delayed control signal, and generate the first pulse; and A current measurement block is used to measure the instantaneous magnitude of an inductor current flowing through the inductor in the low-side phase and to simulate the inductor current in the high-side phase.

4. The power stage according to claim 3, wherein: The gate driver comprises: a second delay block for receiving the first pulse and delaying an end edge of the first pulse by the second duration to generate an end edge of the delayed pulse; and An OR gate is used to receive the delayed pulse and the complement of the control signal and generate the driving signal for the low-side switch.

5. The power stage of claim 3, wherein: The current sensing block includes: an amplifier for amplifying a voltage across the switch driven during the longer phase and providing an amplified voltage between the terminal pair; a first capacitor and a second capacitor; a first switch coupled to a first terminal of the terminal pair and operable to conduct for a duration corresponding to an interval from an end of a blanking period of the low-side phase to an end of the low-side phase to charge the first capacitor; a second switch coupled to a second terminal of the terminal pair and operable to also conduct for a duration corresponding to an interval from an end of the blanking period of the low-side phase to an end of the low-side phase to charge the second capacitor; a first inverter, configured to receive the first pulse and generate a first inversion signal; and An AND gate, configured to receive a second gate drive signal and the first inversion signal, and generate a non-blanking output signal; The non-blanking output signal is operable to control the on and off of the first switch and the second switch, so that the sensing signal is blanked during the first duration and is de-blanked at the end of the first duration.

6. The power stage according to claim 5, wherein: The current sensing block includes: a first transistor and a second transistor coupled in series between a first constant reference potential and a second constant reference potential, wherein the sensed current signal is provided at a current sense output terminal located at a connection of the first transistor and the second transistor, wherein a first current terminal of the first transistor is coupled to the first constant reference potential, a second current terminal of the first transistor is coupled to the current sensing output terminal, and a control terminal of the first transistor is coupled to a corresponding terminal of the first switch, wherein a first current terminal of the second transistor is coupled to the second constant reference potential, a second current terminal of the second transistor is coupled to the current sensing output terminal, and a control terminal of the second transistor is coupled to a corresponding terminal of the second switch, wherein the first capacitor is coupled between the first constant reference potential and the control terminal of the first transistor, and The second capacitor is coupled between the second constant reference potential and the control terminal of the second transistor.

7. The power stage according to claim 6, wherein: Each of the first delay block and the second delay block is operable to receive a corresponding input signal and generate a corresponding delayed signal, the delay block comprising: an asymmetric inverter comprising a third transistor, a fourth transistor, a first resistor, and a third capacitor; and a symmetrical inverter comprising a fifth transistor and a sixth transistor, wherein the fifth transistor and the sixth transistor are coupled in series between the first constant reference potential and the second constant reference potential, and the delayed signal is provided at an output of a delay block located at a connection of the fifth transistor and the sixth transistor; wherein a first current terminal of the third transistor is coupled to the first constant reference potential, and a control terminal of the third transistor is coupled to the input signal of the delay block; wherein a first current terminal of the fourth transistor is coupled to the second constant reference potential, and a control terminal of the fourth transistor is coupled to the input signal of the delay block; wherein the first resistor is coupled between the second current terminal of the third transistor and the second current terminal of the fourth transistor; wherein the third capacitor is coupled between the first current terminal of the fourth transistor and a connection point between the resistor and the second current terminal of the fourth transistor; Wherein, control terminals of the fifth transistor and the sixth transistor are coupled to the connection point of the resistor and the second current terminal of the fourth transistor.

8. A voltage regulation module VRM, comprising: a phase controller for generating a regulated supply voltage at a first supply node based on an input voltage received at the input node; as well as Smart Power Stage SPS, including: a high-side switch and a low-side switch respectively operated by a first drive signal and a second drive signal, the first drive signal and the second drive signal being turned on to drive respective currents through the inductors in the high-side stage and the low-side stage, respectively; a gate driver for generating the first drive signal and the second drive signal based on a control signal received from the phase controller, wherein the control signal is received at a first logic level in a first interval and a second logic level in a second interval; and a current sensing block for generating a sensed current signal; wherein the sensed current signal represents an instantaneous magnitude of an inductor current flowing through the inductor; the sensed current signal is blanked for a first duration at the beginning of the longer of the high-side phase and the low-side phase, the other of the high-side phase and the low-side phase being a shorter phase, and the sensed current signal is de-blanked at the end of the first duration; the duration of the longer phase is greater than or equal to the duration of the shorter phase, wherein the current sensing block generates a first pulse synchronized with the starting point of the longer phase, and a pulse width of the first pulse is equal to the first duration, wherein the gate driver receives the first pulse and generates a delayed pulse synchronized with the starting point of the longer phase, and a pulse width of the delayed pulse is equal to the sum of the first duration and the second duration, wherein the gate driver generates a drive signal for a switch driven with the longer phase, and the drive signal has the first logic level during a duration of at least the pulse width of the delayed pulse.

9. The VRM of claim 8, wherein: The low side phase is the longer phase; Therein, the sum represents the minimum desired duration that the low-side switch is turned on in the low-side phase.

10. The VRM of claim 8, wherein: The current sensing block includes: a first delay block for receiving the control signal and generating a delayed control signal by delaying a high-to-low transition of the control signal by the first duration; an XOR gate, configured to receive the control signal and the delayed control signal, and generate the first pulse; and A current measurement block is used to measure the instantaneous magnitude of an inductor current flowing through the inductor in the low-side phase and to simulate the inductor current in the high-side phase.

11. The VRM of claim 10, wherein: The gate driver comprises: a second delay block for receiving the first pulse and delaying an end edge of the first pulse by the second duration to generate an end edge of the delayed pulse; and An OR gate is used to receive the delayed pulse and the complement of the control signal and generate the driving signal for the low-side switch.

12. The VRM of claim 10, wherein: The current sensing block includes: an amplifier for amplifying a voltage across the switch driven during the longer phase and providing the amplified voltage across a pair of terminals; a first capacitor and a second capacitor; a first switch coupled to a first terminal of the terminal pair and operable to conduct for a duration corresponding to an interval from an end of a blanking period of the low-side phase to an end of the low-side phase to charge the first capacitor; a second switch coupled to a second terminal of the terminal pair and operable to also conduct for a duration corresponding to an interval from an end of the blanking period of the low-side phase to an end of the low-side phase to charge the second capacitor; a first inverter, configured to receive the first pulse and generate a first inversion signal; and An AND gate, configured to receive a second gate drive signal and the first inversion signal, and generate a non-blanking output signal; The non-blanking output signal is operable to control the on and off of the first switch and the second switch, so that the sensing signal is blanked during the first duration and is de-blanked at the end of the first duration.

13. The VRM of claim 12, wherein: The current sensing block includes: a first transistor and a second transistor coupled in series between a first constant reference potential and a second constant reference potential, wherein the sensed current signal is provided at a current sense output terminal located at a connection of the first transistor and the second transistor, wherein a first current terminal of the first transistor is coupled to the first constant reference potential, a second current terminal of the first transistor is coupled to the current sensing output terminal, and a control terminal of the first transistor is coupled to a corresponding terminal of the first switch, wherein a first current terminal of the second transistor is coupled to the second constant reference potential, a second current terminal of the second transistor is coupled to the current sensing output terminal, and a control terminal of the second transistor is coupled to a corresponding terminal of the second switch, wherein the first capacitor is coupled between the first constant reference potential and the control terminal of the first transistor, and The second capacitor is coupled between the second constant reference potential and the control terminal of the second transistor.

14. The VRM of claim 13, wherein: Each of the first delay block and the second delay block is operable to receive a corresponding input signal and generate a corresponding delayed signal, the delay block comprising: an asymmetric inverter comprising a third transistor, a fourth transistor, a first resistor, and a third capacitor; and a symmetrical inverter comprising a fifth transistor and a sixth transistor, wherein the fifth transistor and the sixth transistor are coupled in series between the first constant reference potential and the second constant reference potential, and the delayed signal is provided at an output of a delay block located at a connection of the fifth transistor and the sixth transistor; wherein a first current terminal of the third transistor is coupled to the first constant reference potential, and a control terminal of the third transistor is coupled to the input signal of the delay block, wherein a first current terminal of the fourth transistor is coupled to the second constant reference potential, and a control terminal of the fourth transistor is coupled to the input signal of the delay block, wherein the first resistor is coupled between the second current terminal of the third transistor and the second current terminal of the fourth transistor, wherein the third capacitor is coupled between the first current terminal of the fourth transistor and a connection point between the resistor and the second current terminal of the fourth transistor, Wherein, control terminals of the fifth transistor and the sixth transistor are coupled to the connection point of the resistor and the second current terminal of the fourth transistor.

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