A wide range capacitance test system for flying probe testing

Abstract

The present invention relates to a wide-range capacitance test system for flying probe testing, and belongs to the field of ultra-large-scale integrated circuits and semiconductor manufacturing. The system includes a switching module, a self-test channel, a test channel, a signal processing circuit and an AD acquisition circuit, which can accurately measure a wide range of capacitance values, and solve the problems of insufficient range, digitization, accuracy and anti-interference ability in the prior art. The switching module realizes efficient switching between self-test and test, and the self-test channel ensures the accuracy and stability of the system. A digital control system and a signal processing circuit are used to improve the test accuracy and stability, and the signal source frequency is dynamically adjusted to avoid noise interference. The method of averaging multiple samples further improves the test accuracy. The present invention has broad application prospects in the field of semiconductor manufacturing, can reduce test and production costs, and improve production efficiency.

Description

Technical Field

[0001] The invention belongs to the technical field of ultra-large-scale integrated circuits and semiconductor manufacturing, and in particular relates to a wide-range capacitance test system for flying probe testing. Background Art

[0002] In the flying probe test of semiconductor wafer devices and integrated circuit boards, the measurement of capacitance value is a key step in specific analysis. In traditional technology, the measurement of capacitance relies on a measurement system classified by test frequency band. Each measuring instrument is only applicable to a specific frequency band, resulting in a limited test range and a low degree of digital control. Enterprises and research institutions are usually equipped with instruments for commonly used frequency bands, which makes it difficult to meet the testing needs of a wide range of capacitance values.

[0003] Under current technology, the measurement of wide-range capacitance is susceptible to noise interference, which affects the accuracy and speed of the test. Although the existing technology ensures the test speed by quickly charging and discharging high-precision capacitors and establishing the capacitance transfer conservation law with the capacitor to be tested, and uses the charge conservation relationship to convert it into the voltage value of the detection capacitor terminal for subsequent signal processing, this method is costly to implement and difficult to popularize. At the same time, the existing wide-range capacitance test system lacks flexibility and cannot adjust the signal source frequency according to the test environment, thereby effectively avoiding noise interference, which in turn increases the test and production costs. Summary of the invention

[0004] The purpose of the present invention is to provide a wide-range capacitance test system for flying probe testing, which can measure capacitance values ​​with a wide range and high precision, and at the same time has a system self-check function and can dynamically adjust the signal source frequency according to the test environment to avoid noise interference.

[0005] The present invention achieves the above-mentioned purpose through the following technical solutions:

[0006] The present invention proposes a wide-range capacitance test system for flying probe testing, the system comprising:

[0007] A switching module, used for switching to a self-test channel or a test channel according to a test signal;

[0008] A self-test channel, comprising a self-test capacitor, the self-test channel being used to charge and discharge the self-test capacitor in response to the switching module, and outputting a response signal from the self-test capacitor for system self-test;

[0009] A test channel, used to apply the test signal to the capacitor to be tested through physical contact, charge and discharge the capacitor to be tested, and output a response signal from the capacitor to be tested;

[0010] The signal processing circuit is connected to the output end of the self-test channel and the test channel, and is used to receive the response signal of the self-test capacitor or the capacitor to be tested, and output the signal after amplifying, rectifying, integrating, zeroing and amplifying the response signal;

[0011] The AD acquisition circuit is connected to the output end of the signal processing circuit, and is used to receive the output signal and perform data analysis to determine the self-test capacitance value or the capacitance value to be measured.

[0012] Further, the switching module includes a DDS signal source and an analog switch;

[0013] The DDS signal source is used to output the test signal Vin with adjustable frequency over a wide range;

[0014] The analog switch is used to receive a test signal Vin output by a DDS signal source, and switch the output to the self-test channel input terminal V2 or the test channel input terminal V1 according to the test signal.

[0015] Furthermore, the self-test channel includes a 4-channel analog switch U7, and self-test capacitors C11, C12, C13 and C14 respectively connected to the 4-channel analog switch U7, and switching switches corresponding to the self-test capacitors, and an output terminal V3 of the self-test channel.

[0016] Furthermore, the signal processing circuit includes:

[0017] A multi-stage amplifier circuit, having a gear selection function, is used to amplify the received response signal Vin and output the amplified signal;

[0018] A rectifier-integrator circuit is connected to the output end of the multi-stage amplifier circuit, and is used to perform rectification and integration processing on the amplified signal and output a DC signal;

[0019] The zero adjustment amplifier circuit is connected to the output end of the rectifier integration circuit, and is used for performing zero adjustment and amplification processing on the DC signal and outputting the adjusted signal.

[0020] Furthermore, the multi-stage amplifier circuit includes a charge amplifier circuit and a gain amplifier circuit, the charge amplifier circuit includes gear capacitors C15, C16, C17, C18, C19 and switches corresponding to the gear capacitors, and includes a charge amplifier circuit input terminal V4 and an output terminal V4out; the charge amplifier circuit includes:

[0021] The output terminal V4 is connected to the negative input terminal of the operational amplifier U11, the first terminal of the resistor R13, the first terminal of the capacitor C19, and any input terminal of the 4-channel analog switch U8, the positive input terminal of the operational amplifier U11 is grounded, the first terminal of the resistor R13 is connected to the first terminal of the resistor R14, the output terminal of the operational amplifier U11 is connected to the second terminal of the resistor R14, any output terminal of the 4-channel analog switch U8, and the output terminal V4out of the charge amplifier circuit;

[0022] The gain amplifier circuit comprises:

[0023] The output terminal V4out of the charge amplifier circuit is connected to the first end of the resistor R15, the second end of the resistor R15 is connected to the negative input terminal of the operational amplifier U12A, the first end of the resistor R8 and the first end of the resistor R11, and the positive input terminal of the operational amplifier U12A is grounded; the second end of the resistor R8 is connected to the first end of the switch SW12 through the resistor R9, the second end of the resistor R11 is connected to the first end of the switch SW13 through the resistor R12, and the output terminal of the operational amplifier U12A, the second end of SW12 and the second end of SW13 are connected to the gain gear output terminal V5.

[0024] Furthermore, the zero adjustment amplifier circuit includes:

[0025] The output terminal V7 of the rectifier integrator circuit is connected to the first end of the resistor R22 and the negative input terminal of the operational amplifier U14D, the positive input terminal of the operational amplifier U14D is connected to the first end of the resistor R23, and the second end of the resistor R23 is connected to the digital potentiometer U15; the second end of the resistor R22 and the output terminal of the operational amplifier U14D are connected to the output terminal Vout of the zero adjustment amplifier circuit.

[0026] Furthermore, the test channel includes an excitation pin and a receiving pin, the excitation pin is used to input the test signal into the capacitor to be tested through physical contact, and the receiving pin is used to receive the response signal generated by the capacitor to be tested through physical contact and transmit it to the signal processing circuit and the AD acquisition circuit.

[0027] Furthermore, the system also includes a digital control system, wherein:

[0028] The digital control system is connected to the DDS signal source signal and is used to adjust the test signal of the DDS signal source with a wide frequency range;

[0029] The digital control system is connected to the signal processing circuit signal and is used to control the signal processing circuit to perform signal processing;

[0030] The digital control system is connected to the AD acquisition circuit signal, and is used to receive the output signal of the AD acquisition circuit and perform data analysis to obtain the self-test capacitance value and the capacitance value to be measured.

[0031] Furthermore, the wide-range capacitance test system includes a first processing unit, which is used to receive the self-test capacitance value and compare it with a preset standard value to determine whether the test system is working normally and whether the accuracy is up to standard.

[0032] Furthermore, the wide-range capacitance test system also includes a second processing unit, which is used to record the capacitance value to be measured when the test channel is tested multiple times, and take the average value as the test output.

[0033] Furthermore, the digital control system communicates with a host computer to upload data analysis results to the host computer for display or storage.

[0034] The beneficial effects of the present invention are:

[0035] The present invention can accurately measure a wide range of capacitance values, and solves the problems of insufficient capacitance measurement range, insufficient digitization, unchanged user interaction, insufficient precision and anti-interference ability in the prior art. By switching the self-check channel and the test channel, efficient switching of system self-check and capacitance test to be tested is achieved. At the same time, the accuracy and stability of the test are improved by using a digital control system and a signal processing circuit. The system also has the function of dynamically adjusting the frequency of the signal source, effectively avoiding noise interference, and reducing the test and production costs. In addition, the method of averaging multiple samples further improves the test accuracy, so that the system has a wide range of application prospects in the field of ultra-large-scale integrated circuits and semiconductor manufacturing. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 A system block diagram of a wide range capacitance test system for flying probe testing provided in an embodiment of the present application;

[0037] Figure 2 A schematic diagram of a switching module circuit in a wide-range capacitance test system for flying probe testing provided in an embodiment of the present application;

[0038] Figure 3 A schematic diagram of a self-test channel circuit in a wide-range capacitance test system for flying probe testing provided in an embodiment of the present application;

[0039] Figure 4 A schematic diagram of a multi-stage amplification circuit in a wide-range capacitance test system for flying probe testing provided in an embodiment of the present application;

[0040] Figure 5 A schematic diagram of a rectifier integration circuit and a zero adjustment amplifier circuit in a wide range capacitance test system for flying probe testing provided in an embodiment of the present application;

[0041] Figure 6 A schematic diagram of a flow chart of a wide range capacitance test system for flying probe testing provided in an embodiment of the present application;

[0042] Figure 7 Another flow chart of a wide-range capacitance testing system for flying probe testing provided in an embodiment of the present application. DETAILED DESCRIPTION

[0043] The present application is further described in detail below in conjunction with the accompanying drawings. It is necessary to point out here that the following specific implementation methods are only used to further illustrate the present application and cannot be understood as limiting the scope of protection of the present application. Technical personnel in this field can make some non-essential improvements and adjustments to the present application based on the above application content.

[0044] Example 1

[0045] against Figure 2 , Figure 3 and Figure 4 Description:

[0046] Vin: signal source input;

[0047] V1: Normal test input, given to the excitation pin Probe1 through relays U4 and U5;

[0048] V2: self-test input;

[0049] V3: self-test capacitor output;

[0050] V4: accepts probe probe2 input and self-test capacitor V3 output;

[0051] V4out: the output of the gear capacitor, which is proportional to the previous test capacitor and the gear capacitor;

[0052] V5: Gain gear output, you can select the appropriate multiple relationship through two switches to control the output amplitude;

[0053] V6: input of V5;

[0054] V6out: half-wave rectifier output, that is , The function is to downsample the voltage value after passing through the multi-stage amplification circuit for subsequent rectification and integration processing;

[0055] V7: Output of the integration circuit, that is ;

[0056] Vout: is the output of V7 after following, and finally given to ADC for collection;

[0057] Probe1, Probe2: respectively, the excitation pin and the receiving pin, used to insert into both ends of the capacitor to be tested;

[0058] SW1: controls the switching of V1 and V2;

[0059] SW2, 3: relay switch, control probe1, probe2 input and output;

[0060] SW4,5,6,7: Self-test capacitor switching for self-test;

[0061] SW8,9,10,11: gear capacitor switching;

[0062] SW12,13: Gain multiple switching;

[0063] C11,12,13,14: self-test capacitors;

[0064] C15, 16, 17, 18, 19: gear capacitors, used for the self-test capacitor and the capacitor to be tested, and output signals;

[0065] R8,9,11,12,15: gain resistors;

[0066] R13,14: op amp return resistor;

[0067] R16,19,20, D3,5: resistors and diodes that form a half-wave rectifier circuit;

[0068] R21, R22, R23: current limiting resistors;

[0069] R17, C20: reflux resistor and integration capacitor that constitute the integration circuit respectively;

[0070] U6: Analog switch, used for self-test mode and normal test mode selection;

[0071] U4, 5: digital relay, control the sending and receiving of the pin;

[0072] U7: 4-channel analog switch, controls the switching of self-test capacitors;

[0073] U8A, B, C, D: Four-channel analog switch, controlling the switching of gear capacitors;

[0074] U11, U12A, U14A, U14C, U14D: operational amplifier;

[0075] U15: digital potentiometer, used for channel zero adjustment;

[0076] EUT: Capacitor under test.

[0077] Combination Figure 1 , Figure 6 and Figure 7This embodiment proposes a wide-range capacitance test system for flying probe test, the system includes a switching module 1, a self-test channel 2, a test channel 3, a signal processing circuit 4 and an A / D acquisition circuit 5.

[0078] The switching module 1 is used to switch to the self-test channel 2 or the test channel 3 according to the test signal. The switching module 1 includes a DDS signal source 11 and an analog switch 12; the DDS signal source 11 is used to output a test signal with a wide range and adjustable frequency; the analog switch 12 is used to receive the test signal output by the DDS signal source 11, and switch the output to the self-test channel 2 (V2) or the test channel 3 (V1) according to the test signal.

[0079] In this embodiment, combined with Figure 2 , the DDS signal source 11 generates the signal required for the test, which is distributed through the analog switch 12. Signal distribution to test channel 3: The analog switch 12 outputs the signal generated by the DDS signal source 11 to the self-test channel 2 (V2 input in the figure) and the normal test channel (V1 input in the figure).

[0080] The self-test channel 2 includes a self-test capacitor, which is used to respond to the switching module 1 to charge and discharge the self-test capacitor, and output a response signal from the self-test capacitor for system self-test; the test channel 3 is used to apply a test signal to the capacitor to be tested through physical contact, charge and discharge the capacitor to be tested, and output a response signal from the capacitor to be tested.

[0081] It can be understood that the switching module in this embodiment can flexibly select the test path to ensure that the system can switch accurately and efficiently when performing self-test or actual test.

[0082] The signal processing circuit 4 is connected to the output ends of the self-test channel 2 and the test channel 3, and is used to receive the response signal of the self-test capacitor or the capacitor to be tested, and output the signal after amplifying, rectifying, integrating, zeroing and amplifying the response signal;

[0083] Optionally, the signal processing circuit 4 includes: a multi-stage amplifier circuit with a gear selection function, which is used to amplify the received response signal Vin and output the amplified signal; a rectifier integration circuit connected to the output end of the multi-stage amplifier circuit, which is used to rectify and integrate the amplified signal and output a DC signal; a zero adjustment amplifier circuit connected to the output end of the rectifier integration circuit, which is used to zero-adjust the DC signal and output the adjusted signal. The AD acquisition circuit 5 is connected to the output end of the signal processing circuit 4, and is used to receive the output signal and perform data analysis to determine the self-test capacitance value or the capacitance value to be measured.

[0084] More specifically, combined Figure 4The multi-stage amplifier circuit includes a charge amplifier circuit and a gain amplifier circuit. The charge amplifier circuit includes gear capacitors C15, C16, C17, C18, C19 and switching switches corresponding to the gear capacitors, and includes a charge amplifier circuit input terminal V4 and an output terminal V4out; the charge amplifier circuit includes: the output terminal V4 is connected to the negative input terminal of the operational amplifier U11, the first end of the resistor R13, the first end of the capacitor C19, and any input terminal of the 4-channel analog switch U8, the positive input terminal of the operational amplifier U11 is grounded, the first end of the resistor R13 is connected to the first end of the resistor R14, the output terminal of the operational amplifier U11 is connected to the second end of the resistor R14, the 4-channel analog switch Any output end of U8, and the output end V4out of the charge amplifier circuit; the gain amplifier circuit includes: the output end V4out of the charge amplifier circuit is connected to the first end of the resistor R15, the second end of the resistor R15 is connected to the negative input end of the operational amplifier U12A, the first end of the resistor R8 and the first end of the resistor R11, and the positive input end of the operational amplifier U12A is grounded; the second end of the resistor R8 is connected to the first end of the switch SW12 through the resistor R9, the second end of the resistor R11 is connected to the first end of the switch SW13 through the resistor R12, and the output end of the operational amplifier U12A, the second end of SW12, and the second end of SW13 are connected to the gain gear output end V5.

[0085] More specifically, combined Figure 5 The zero adjustment amplifier circuit includes: the output terminal V7 of the rectifier integration circuit is connected to the first end of the resistor R22 and the negative input terminal of the operational amplifier U14D, the positive input terminal of the operational amplifier U14D is connected to the first end of the resistor R23, and the second end of the resistor R23 is connected to the digital potentiometer U15; the second end of the resistor R22 and the output end of the operational amplifier U14D are connected to the output terminal Vout of the zero adjustment amplifier circuit.

[0086] Combination Figure 3 Further preferably, the self-test channel includes a 4-channel analog switch U7, and self-test capacitors C11, C12, C13 and C14 respectively connected to the 4-channel analog switch U7, and switching switches corresponding to the self-test capacitors, and an output end V3 of the self-test channel.

[0087] Further preferably, the test channel 3 includes an excitation pin and a receiving pin, the excitation pin is used to input the test signal into the capacitor to be tested through physical contact, and the receiving pin is used to receive the response signal generated by the capacitor to be tested through physical contact and transmit it to the signal processing circuit and the AD acquisition circuit.

[0088] In this embodiment, the workflow of self-check channel 2 is as follows:

[0089] In the self-test mode, the signal selects V2 input, passes through the self-test capacitor C (C11, C12, C13, C14), outputs V3, and then directly passes it to the subsequent processing stage, which is similar to the test channel process, and finally outputs Vout to the AD acquisition board.

[0090] Self-test channel 2 is used to verify the accuracy and stability of the entire test system. By comparing the calculated C test capacitance value with the standard value, it is determined whether the system is working properly and the accuracy meets the standard.

[0091] In this embodiment, the functions of the excitation needle and the receiving needle in the test channel 3 are as follows:

[0092] Function of the excitation pin: The excitation pin is used to apply a signal to the capacitor Cx to be tested in the test channel 3. It transmits the signal (such as Vin) output by the DDS signal source 11 to the capacitor Cx to be tested through physical contact, thereby stimulating the charging and discharging process of the capacitor.

[0093] Function of the receiving pin: The receiving pin is used to receive the signal of the capacitor Cx to be tested. After the excitation pin applies a signal, the capacitor Cx to be tested will generate a corresponding response signal. The receiving pin receives this signal through physical contact and transmits it to the subsequent signal processing circuit 4.

[0094] Working principle: During the test, the excitation pin and the receiving pin work together to form a complete test loop. The signal applied by the excitation pin passes through the capacitor to be tested Cx, is received by the receiving pin and transmitted to the subsequent circuit for processing. By measuring and processing this signal, the capacitance value of the capacitor to be tested Cx can be calculated.

[0095] Workflow of test channel 3:

[0096] Signal application: DDS signal source 11 outputs signal Vin, and the normal test channel input V1 is selected through analog switch 12. The V1 signal selects probe1 as the excitation pin through the relay, and the signal is applied to the capacitor Cx to be tested through physical contact. The other end selects probe2 as the receiving pin, receives the signal of the object to be tested through physical contact, and then transmits it to V4.

[0097] Signal reception: After the capacitor Cx to be tested receives the signal, it will generate a corresponding response signal, which is received by the receiving pin and transmitted to the subsequent signal processing circuit.

[0098] Signal processing: The received signal is processed by multi-stage amplifier circuit, rectifier integration circuit and zero adjustment amplifier circuit, and finally output to AD acquisition circuit. Through formula calculation, the capacitance value of the capacitor Cx to be measured can be obtained.

[0099] More specifically, combined Figure 4 and Figure 5, the working process in the signal processing circuit 4 is as follows:

[0100] V4 is connected to a charge amplifier circuit with gear selection. The gear capacitor C gear (C15, C16, C17, C18, C19) on the circuit and the capacitor to be measured Cx are related by the operational amplifier. files.

[0101] V4out is input to the next amplifier circuit and outputs V5. The relationship is: .

[0102] V5 is input to the rectifier integration circuit and the DC output is V7. The relationship is: (Note that V6 is the intermediate value of V5 after some processing, which is not directly shown in the figure). After V6 passes through a half-wave rectifier circuit, V6out is obtained, whose value is one-fourth of the voltage value of V6, which is specifically determined based on the characteristics of the half-wave rectifier circuit.

[0103] The output of V7 is given to the zero adjustment amplifier circuit and outputs Vout.

[0104] AD acquisition and calculation:

[0105] Vout is output to the AD acquisition circuit and is digitally processed by the AD acquisition circuit.

[0106] It is understandable that the calculation process of the self-test capacitance value is the same as the calculation process of the capacitance value to be measured in the above-mentioned signal processing circuit 4.

[0107] Further preferably, the system further comprises a digital control system, wherein:

[0108] The digital control system is connected to the DDS signal source signal and is used to adjust the test signal of the DDS signal source with a wide frequency range;

[0109] The digital control system is connected to the signal processing circuit signal and is used to control the signal processing circuit to perform signal processing;

[0110] The digital control system is connected to the AD acquisition circuit signal, and is used to receive the output signal of the AD acquisition circuit and perform data analysis to obtain the self-test capacitance value and the capacitance value to be measured.

[0111] Further preferably, the wide-range capacitance test system includes a first processing unit for receiving the self-test capacitance value and comparing it with a preset standard value to determine whether the test system is working normally and whether the accuracy is up to standard. The wide-range capacitance test system also includes a second processing unit for recording the capacitance value to be tested during multiple tests of the test channel and taking the average value as the test output.

[0112] Further preferably, the digital control system communicates with a host computer to upload the data analysis results to the host computer for display or storage.

[0113] According to the above embodiment of the present invention, when the test system is implemented, the test process includes:

[0114] 1. First, perform channel zero adjustment: test the voltage value of VOUT in the empty needle state, and clear the channel through the digital potentiometer U15, that is, , and then start the channel self-check;

[0115] 2. Perform self-test test: Switch to self-test mode, the purpose is to infer the currently selected self-test capacitor value through the final output Vout and compare it with the calibration value of the actual self-test capacitor to determine whether the channel is working properly. The detailed calculation process is as follows:

[0116] Self-test mode selection, Vin is given to V2 (entering the self-test channel), and directly given to the self-test capacitor position (all four positions SW4 / 5 / 6 / 7 must be tested, SW4 can be selected), and the subsequent position capacitor selection and gain position selection are matched according to the capacitance value (self-test capacitor or EUT capacitor) to be tested. The test process proposed here defaults to SW4 position capacitor with SW11 position capacitor and SW12 position gain, and finally a Vout value will be obtained. The calculation formulas for each node are reversed and reflected in the numbers:

[0117] ;

[0118] The above equation calculates the self-test capacitance value tested. Where Vout is the test output value, and the others are known values. The tested C11 is compared with the pre-calibrated C11 value. If it is within the error range, it means that the circuits at all levels are normal and can be used for EUT testing.

[0119] After the self-test capacitance test is completed, the normal EUT capacitance test (test channel) can be performed.

[0120] 3. Perform normal test: As with self-test, Vout is finally obtained, and the EUT capacitance value can be inferred from Vout to complete the EUT capacitance test. The expression is .

[0121] It should be noted here that the above-mentioned self-test capacitors and gear capacitors can be matched according to actual needs, and the above-mentioned test process is only a calculation example for one channel.

[0122] According to the above-mentioned embodiments of the present invention, the wide-range capacitance test system for flying probe testing provided by the present invention can accurately test a wide range of capacitance by setting a self-check channel and a test channel. The setting of the self-check channel ensures the reliability and accuracy of the system before it is put into use; the test channel has high test accuracy and anti-interference ability, and can meet the test requirements under different ranges. At the same time, the introduction of signal processing circuits and digital control systems further improves the automation level and test efficiency of the system. Compared with the prior art, the present invention has the advantages of wide test range, high test accuracy, high automation level and high test efficiency, and has important practical value and application prospects.

[0123] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments can still be modified, or some of the technical features can be replaced by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A wide range capacitance test system for flying probe testing, characterized in that: The system comprises: A switching module, used for switching to a self-test channel or a test channel according to a test signal; A self-test channel, comprising a self-test capacitor, the self-test channel being used to charge and discharge the self-test capacitor in response to the switching module, and outputting a response signal from the self-test capacitor for system self-test; A test channel, used to apply the test signal to the capacitor to be tested through physical contact, charge and discharge the capacitor to be tested, and output a response signal from the capacitor to be tested; The signal processing circuit is connected to the output end of the self-test channel and the test channel, and is used to receive the response signal of the self-test capacitor or the capacitor to be tested, and output the signal after amplifying, rectifying, integrating, zeroing and amplifying the response signal; AD acquisition circuit, connected to the output end of the signal processing circuit, for receiving the output signal and performing data analysis to determine the self-test capacitance value or the capacitance value to be measured; The switching module includes a DDS signal source and an analog switch; The DDS signal source is used to output the test signal Vin with adjustable frequency over a wide range; The analog switch is used to receive the test signal Vin output by the DDS signal source, and switch the output to the self-test channel input terminal V2 or the test channel input terminal V1 according to the test signal; The self-test channel includes a 4-channel analog switch U7, and self-test capacitors C11, C12, C13 and C14 respectively connected to the 4-channel analog switch U7, and switching switches corresponding to the self-test capacitors, and an output terminal V3 of the self-test channel.

2. A wide range capacitance test system for flying probe testing according to claim 1, characterized in that: The signal processing circuit comprises: A multi-stage amplifier circuit, having a gear selection function, is used to amplify the received response signal Vin and output the amplified signal; A rectifier-integrator circuit is connected to the output end of the multi-stage amplifier circuit, and is used to perform rectification and integration processing on the amplified signal and output a DC signal; The zero adjustment amplifier circuit is connected to the output end of the rectifier integration circuit, and is used for performing zero adjustment and amplification processing on the DC signal and outputting the adjusted signal.

3. A wide range capacitance test system for flying probe testing according to claim 2, characterized in that: The multi-stage amplifier circuit includes a charge amplifier circuit and a gain amplifier circuit. The charge amplifier circuit includes gear capacitors C15, C16, C17, C18, C19 and switches corresponding to the gear capacitors, and includes a charge amplifier circuit input terminal V4 and an output terminal V4out; the charge amplifier circuit includes: The output terminal V4 is connected to the negative input terminal of the operational amplifier U11, the first terminal of the resistor R13, the first terminal of the capacitor C19, and any input terminal of the 4-channel analog switch U8, the positive input terminal of the operational amplifier U11 is grounded, the first terminal of the resistor R13 is connected to the first terminal of the resistor R14, the output terminal of the operational amplifier U11 is connected to the second terminal of the resistor R14, any output terminal of the 4-channel analog switch U8, and the output terminal V4out of the charge amplifier circuit; The gain amplifier circuit comprises: The output terminal V4out of the charge amplifier circuit is connected to the first end of the resistor R15, the second end of the resistor R15 is connected to the negative input terminal of the operational amplifier U12A, the first end of the resistor R8 and the first end of the resistor R11, and the positive input terminal of the operational amplifier U12A is grounded; the second end of the resistor R8 is connected to the first end of the switch SW12 through the resistor R9, the second end of the resistor R11 is connected to the first end of the switch SW13 through the resistor R12, and the output terminal of the operational amplifier U12A, the second end of SW12 and the second end of SW13 are connected to the gain gear output terminal V5.

4. A wide range capacitance test system for flying probe testing according to claim 3, characterized in that: The zero adjustment amplifier circuit comprises: The output terminal V7 of the rectifier integrator circuit is connected to the first end of the resistor R22 and the negative input terminal of the operational amplifier U14D, the positive input terminal of the operational amplifier U14D is connected to the first end of the resistor R23, and the second end of the resistor R23 is connected to the digital potentiometer U15; the second end of the resistor R22 and the output terminal of the operational amplifier U14D are connected to the output terminal Vout of the zero adjustment amplifier circuit.

5. A wide range capacitance test system for flying probe testing according to claim 4, characterized in that: The test channel includes an excitation pin and a receiving pin, wherein the excitation pin is used to input the test signal into the capacitor to be tested through physical contact, and the receiving pin is used to receive the response signal generated by the capacitor to be tested through physical contact and transmit it to the signal processing circuit and the AD acquisition circuit.

6. A wide range capacitance test system for flying probe testing according to claim 5, characterized in that: The system also includes a digital control system, wherein: The digital control system is connected to the DDS signal source signal and is used to adjust the test signal of the DDS signal source with a wide frequency range; The digital control system is connected to the signal processing circuit signal and is used to control the signal processing circuit to perform signal processing; The digital control system is connected to the AD acquisition circuit signal, and is used to receive the output signal of the AD acquisition circuit and perform data analysis to obtain the self-test capacitance value and the capacitance value to be measured.

7. A wide range capacitance test system for flying probe testing according to claim 6, characterized in that: The wide-range capacitance test system includes a first processing unit, which is used to receive the self-test capacitance value and compare it with a preset standard value to determine whether the test system is working normally and whether the accuracy meets the standard.

8. A wide range capacitance test system for flying probe testing according to claim 7, characterized in that: The wide-range capacitance test system further includes a second processing unit, which is used to record the capacitance value to be tested when the test channel is tested multiple times, and take the average value as the test output.

9. A wide range capacitance test system for flying probe testing according to claim 8, characterized in that: The digital control system communicates with a host computer and is used to upload data analysis results to the host computer for display or storage.

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