Large-scale addressable critical path test circuit

Abstract

The invention discloses a large-scale addressable critical path test circuit, and the circuit comprises an excitation circuit which is used for generating an input signal VIN and a power supply VDD; the row addressing circuit and the column addressing circuit are respectively used for receiving a row address and a column address, controlling the switching circuit according to a received address signal, selecting a to-be-tested path to be tested from a plurality of to-be-tested paths, enabling an input signal VIN to act on an input end of the to-be-tested path, enabling a power supply VDD to act on the to-be-tested path to be tested, and enabling the to-be-tested path to be tested. Supplying power to the to-be-tested path; each to-be-detected path is connected with a TDC module and is used for detecting delay time required by propagation of an input signal VIN in the corresponding to-be-detected path; and the sensing circuit is connected with each to-be-detected path and is used for detecting the actual power supply voltage VDDSENSE of each to-be-detected path. According to the invention, the sensing circuit is used for sensing the VDD voltage drop condition of the unit to be detected, and the actual working voltage of the circuit can be accurately detected.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductor wafer testing, and in particular to a large-scale addressable critical path testing circuit. Background Art

[0002] As CMOS technology nodes continue to shrink, random fluctuations in the process and unreliability in the circuit operation process will cause the propagation delay of the critical path to change more and more significantly. The timing margin design of the critical path needs to ensure that the circuit can still work properly even in the worst-case combination of process deviations, temperature hot spots and power supply voltage uncertainties, while minimizing the design margin, circuit power consumption, etc.

[0003] When designing the timing margin of a circuit, it is necessary to accurately estimate the real critical path to ensure high reliability of the circuit. Monitoring the impact of random process changes on critical path delays and changes in critical paths during circuit operation requires a fast, accurate, large-scale testing technology that provides sufficient data support for monitoring random changes and operating conditions. Summary of the invention

[0004] In view of the above-mentioned defects and shortcomings of the prior art, the present invention provides a large-scale addressable critical path test circuit, which aims to achieve performance measurement of large-scale critical paths (including propagation delay, leakage, power consumption, etc.), and can also achieve higher area utilization and accuracy.

[0005] To achieve the above objectives, the present invention provides a large-scale addressable critical path test circuit, which includes:

[0006] An excitation circuit, used for generating an input signal VIN and a power supply VDD;

[0007] The row addressing circuit and the column addressing circuit are used to receive the row address and the column address respectively, and control the switch circuit according to the received address signal, select the path to be tested from multiple paths to be tested, apply the input signal VIN to the input end of the path to be tested, and apply the power supply VDD to the path to be tested to supply power to the path to be tested;

[0008] Each path to be tested is connected to a TDC module for detecting the delay time required for the input signal VIN to propagate in the corresponding path to be tested;

[0009] The sensing circuit is connected to each path to be tested and is used to detect the actual power supply voltage VDD of each path to be tested. SENSE .

[0010] A further improvement of the present invention is that: the path to be tested is a transmission path of a signal in a circuit.

[0011] A further improvement of the present invention is that: a plurality of paths to be tested are divided into a plurality of groups, and any two groups of paths to be tested include circuit units of different levels or circuit units of different types.

[0012] A further improvement of the present invention is that the types of the circuit unit include inverters, NAND gates, NOR gates, etc.

[0013] A further improvement of the present invention is that each of the paths to be tested is integrated on a single wafer, and a power supply PAD and an input signal PAD are provided on the wafer, which are used to receive the power supply VDD and the input signal VIN generated by the excitation circuit respectively.

[0014] A further improvement of the present invention is that the switch circuits are all implemented by a combination of a transmission gate and a pull-down tube.

[0015] A further improvement of the present invention is that: the TDC module converts the delay time into a digital signal Q<1:N> in the form of a temperature code; the output end of each TDC module is connected to a transmission gate, and the output end of each transmission gate is connected to an encoding circuit; the encoding circuit converts the digital signal Q<1:N> output by the TDC module into a binary signal S<1:A>.

[0016] The advantages of the present invention are as follows:

[0017] 1) In the present invention, all paths to be tested share one VIN and VDD PAD, which can significantly increase the number of tests per unit area.

[0018] 2) The present invention provides a circuit that allows large-scale testing of different paths and supports efficient monitoring of critical paths.

[0019] 3) The present invention uses a sensing circuit to sense the VDD voltage drop of the unit under test, which can accurately detect the actual working voltage of the circuit and ensure accurate analysis of subsequent test data. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A schematic diagram of a large-scale addressable critical path test circuit of the present invention;

[0021] Figure 2 is a schematic diagram of the sensing circuit in the present invention;

[0022] Figure 3 is a schematic diagram of a transmission gate in a switch circuit of the present invention;

[0023] Figure 4 It is a connection diagram of the TDC module in the present invention;

[0024] Figure 5 It is a schematic diagram of the principle of the TDC module in the present invention;

[0025] Figure 6 It is a schematic diagram of the output circuit attached to the TDC module in the present invention. DETAILED DESCRIPTION

[0026] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0027] While some exemplary embodiments of the present invention have been described for the purpose of illustration, it should be understood that the present invention may be implemented in other ways not specifically shown in the drawings.

[0028] The embodiment of the present invention provides a large-scale addressable critical path test circuit, which is mainly composed of an addressing circuit, a switching circuit, an excitation circuit, a sensing circuit, an array to be tested, and a time-digital conversion circuit (TDC). Considering that the propagation delay cannot be directly output as a time quantity, a TDC circuit is required to convert the time quantity into a digital quantity for output. Specifically:

[0029] The addressing circuit includes a row addressing circuit and a column addressing circuit. Figure 1 As shown, in this embodiment, the row address and column address are both 4 bits. The row and column addresses are RA[0:3] and CA[0:3] respectively, which are converted into 16 bits R[0:15] and C[0:15] by the decoder, so that 16×16=256 paths can be tested.

[0030] The excitation circuit is used to generate an input signal VIN and a power supply VDD. The row addressing circuit and the column addressing circuit are respectively connected to the switch circuit. In addition, the switch circuit is also connected to two output terminals of the excitation circuit. The row addressing circuit and the column addressing circuit control the switch circuit to select a path to be tested from an array of paths to be tested including multiple paths to be tested, apply the input signal VIN to the input terminal of the path to be tested, and apply the power supply VDD to the path to be tested to power the path to be tested. In this way, the power supply VDD and the input signal of the path to be tested can be specified at the same time, so as to perform a more comprehensive multi-dimensional test on the path to be tested.

[0031] like Figure 1 , Figure 2 As shown, each path to be tested is connected to a sensing circuit for respectively sensing the actual power supply voltage VDD of each path to be tested.SENSE The input signal VIN is input to the inverter, that is, the gate end of the MOS tube. The gate current is extremely small, and the voltage drop caused by the transmission gate in the switch circuit can be ignored. VDD is connected to the source end of the PMOS of each inverter in the path to be tested. The current is large, and the voltage drop caused by the transmission gate needs to be considered. Therefore, a sensing circuit is set, that is, the transmission gate is connected to the VDD end to obtain the signal VDD. SENSE .

[0032] The array to be tested includes multiple paths to be tested. In this embodiment, each path to be tested is an inverter chain. The array to be tested includes 256 paths to be tested, which are divided into 8 groups, each with 32 paths to be tested. In these 8 groups, the inverter chains of any two groups of paths to be tested have different inverter levels. In this embodiment, the levels of these 8 groups of inverter chains are 14, 20, 26, 32, 38, 44, 50 and 56, respectively. Using paths to be tested with different levels can ensure the diversity of the paths to be tested. It should be noted that the propagation delays of inverter chain groups with different levels are different. When setting the number of bits of the TDC module output signal, it is necessary to estimate the maximum delay to ensure accurate output.

[0033] Each of the paths to be tested is integrated on a single wafer (die), and a power supply PAD and an input signal PAD are provided on the wafer, which are used to receive the power supply VDD and the input signal VIN generated by the excitation circuit respectively. Each path to be tested reuses a single power supply PAD and an input signal PAD, which can effectively improve the chip area utilization. In this embodiment, the multiplexing is achieved through an addressing circuit and a switching circuit.

[0034] like Figure 3 As shown in the figure, the switch circuit is realized by the combination of the transmission gate and the pull-down tube. When Address[N] = 1, the pull-down tube is closed, the transmission gate is opened, and V OUT =V IN Otherwise, the pull-down tube is turned on, V OUT = 0. In the addressing circuit, R[0:15] and C[0:15] can generate 256 signals, corresponding to the VIN and VDD signals of the excitation circuit, and can generate 256 sets of VIN[N] and VDD[N], which uniquely correspond to the row and column addresses. When the address signal is given, only one set of transmission gates in the switch circuit is controlled to conduct.

[0035] like Figure 4 As shown, the propagation delay of the path to be tested is output in digital form and shares a set of output ports. Apply the VIN signal to the input of the inverter chain to obtain VOUT0, and compare the delay time of the two. However, the test equipment cannot directly obtain the time quantity, and the circuit needs to convert the time quantity into an electrical quantity for output. Apply the TDC circuit, input VIN and VOUT0, and output the time difference between the two in the form of binary code.

[0036] like Figure 5 As shown, this example takes a TDC based on the vernier delay line principle as an example, which consists of two delay lines with slightly different delay times. The start (leading) signal is fed to the delay line with a larger delay, that is, the slow delay line, while the stop (lag) signal is fed to the fast delay line. During the measurement process, the stop signal propagates relatively fast and will eventually catch up with the start signal after passing through a certain number of delay units. Therefore, the resolution of this TDC is the delay difference r = τ between the unit delays in the slow line and the fast line s -τ f , the conversion range is the product of the number of levels N and the resolution r.

[0037] The input and output of the inverter chain are connected to the TDC as the leading signal and the lagging signal, respectively, to obtain Q<1:N>. Assuming that at the Mth stage, the lagging signal catches up with the leading signal, then the output of Q<1:M-1> is low, and Q <m:n>The output is high level, so we get the number of low levels M in Q<1:N>, and we can get the delay time T DELAY = r × M. However, when the number of stages is large, directly outputting Q<1:N> will occupy too many PADs, so it is necessary to convert the N-bit temperature code into Bit( The binary code S<1:A> (rounded up) can effectively reduce the number of PADs.

[0038] like Figure 6 As shown, the outputs of multiple inverter chains are connected together through transmission gates. OUT If the load capacitance driven by the inverter is too large, the capacitance will not be fully charged and discharged, which will cause V OUT The waveform is seriously distorted; the transmission gate is also controlled by the addressing circuit. The digital signal will not be affected by the charge and discharge time, so it needs to be converted into a digital signal Q<1:N> through TDC and isolated. Each inverter chain to be tested is connected to a TDC, connected together through the transmission gate, the address signal is consistent with the switch circuit, and then connected to the encoder Encoder to convert Q<1:N> into binary code S<1:A>, further saving the number of occupied PADs.

[0039] The output data is used to monitor the impact of the process and the changes in the critical path during operation, providing feedback for further adjustment of the circuit operating state. The delay data is fed back to the control unit, which can dynamically adjust the operating voltage and frequency of the circuit. If an increase in the critical path delay is detected, the voltage may need to be increased or the operating frequency may need to be reduced to ensure the stability and reliability of the circuit. Conversely, if the critical path delay decreases, the voltage can be reduced or the frequency can be increased to improve energy efficiency and performance. At the same time, the performance of the critical path needs to be continuously monitored to ensure stable operation of the circuit under the adjusted voltage and frequency.

[0040] The core of the present invention is to improve the integration of the test circuit by sharing the signal ports of all units to be tested and output them in digital form. Other alternatives include changing the number of paths to be tested, changing the number of parallel test arrays, changing the number of row and column address bits, changing the specific composition structure of the path, changing the principle and structure of the TDC circuit, changing the structure of the switch circuit, changing the bit width of the delayed output digital signal, and changing the delayed signal feedback method, all of which are within the scope of protection of the present invention.

[0041] The key point of the present invention is to test the propagation delay of large-scale paths, monitor the influence of the process on the critical path and the changes in the working process, and output the delay in digital form to form feedback for further adjusting the working state of the circuit. The large-scale test circuit uses the switch circuit module to realize the sharing of power supply signals of all paths to be tested, which can improve the area utilization rate when performing fast and accurate testing of different paths. Therefore, the point to be protected is to use the design of sharing power supply signals for all paths and outputting them in digital form when using the addressing method to perform large-scale testing of critical paths.

[0042] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.< / m:n>

Claims

1. A large-scale addressable critical path test circuit, characterized in that include: An excitation circuit, used for generating an input signal VIN and a power supply VDD; The row addressing circuit and the column addressing circuit are used to receive the row address and the column address respectively, and control the switch circuit according to the received address signal, select the path to be tested from multiple paths to be tested, apply the input signal VIN to the input end of the path to be tested, and apply the power supply VDD to the path to be tested to supply power to the path to be tested; Each path to be tested is connected to a TDC module for detecting the delay time required for the input signal VIN to propagate in the corresponding path to be tested; The sensing circuit is connected to each path to be tested and is used to detect the actual power supply voltage VDD of each path to be tested. SENSE .

2. The large-scale addressable critical path test circuit according to claim 1, characterized in that: The path to be tested is a transmission path of a signal in a circuit.

3. The large-scale addressable critical path test circuit according to claim 2, characterized in that: The plurality of paths to be tested are divided into a plurality of groups, and any two groups of paths to be tested include circuit units of different levels or circuit units of different types.

4. The large-scale addressable critical path test circuit according to claim 3, characterized in that: The types of the circuit units include inverters, NAND gates, and NOR gates.

5. The large-scale addressable critical path test circuit according to claim 1, characterized in that: Each of the paths to be tested is integrated on a single wafer, and a power supply PAD and an input signal PAD are provided on the wafer, which are used to receive the power supply VDD and the input signal VIN generated by the excitation circuit respectively.

6. The large-scale addressable critical path test circuit according to claim 1, characterized in that: The switch circuits are all implemented by a combination of a transmission gate and a pull-down tube.

7. The large-scale addressable critical path test circuit according to claim 1, characterized in that: The TDC module converts the delay time into a digital signal Q<1:N> in the form of a temperature code; the output end of each TDC module is connected to a transmission gate, and the output end of each transmission gate is connected to an encoding circuit; the encoding circuit converts the digital signal Q<1:N> output by the TDC module into a binary signal S<1:A>.

Images