VRM communication security encryption method, apparatus and device, and medium
Through the FPGA as an intermediary, the BMC write operation key to VRM is verified, which solves the problem of unauthorized access in communication between BMC and VRM and improves communication security.
Patent Information
- Application Number
- CN202411683319.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-22
- Publication Date
- 2025-03-14
AI Technical Summary
In the prior art, BMC communicates with VRM through I2C/SMBUS channels with unauthorized access and potential security risks.
Through the FPGA as an intermediary, the BMC sends read and write operation commands to the FPGA. The FPGA recognizes the commands and judges whether to perform write operations to VRM based on whether the key input by the BMC is correct.
Effectively prevent unauthorized access, solve potential security risks, and enhance the communication security of BMC to VRM.
Smart Images
Figure CN119622767A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of communication security technology, and in particular to a VRM communication security encryption method, device, equipment and medium. Background Art
[0002] In modern computer systems, the Baseboard Management Controller (BMC) plays a vital role, responsible for monitoring the health of the system, managing power, recording system events, and providing remote management functions. In order to effectively control the system power, the BMC needs to communicate with the power digital controller (VoltageRegulatorModule), which is usually achieved through serial communication protocols such as I2C (Inter-Integrated Circuit) or SMBUS (System Management Bus).
[0003] However, since the main function of BMC is the management port, it has a network port, and the I2C / SMBUS channel from BMC to VRM is always connected, there are certain security risks: hackers may maliciously tamper with the contents of VRM through the BMC network port and I2C control, that is, there is unauthorized access and potential security risks. Summary of the invention
[0004] The purpose of the present invention is to provide a VRM communication security encryption method, device, equipment and medium, aiming to solve the technical problems of unauthorized access and potential security risks in the prior art.
[0005] In order to solve the above technical problems, the purpose of the present invention is achieved through the following technical solutions:
[0006] The first aspect of the present application provides a VRM communication security encryption method, comprising the following steps:
[0007] Send read and write operation commands to FPGA through BMC;
[0008] The FPGA identifies the received read and write operation commands;
[0009] If the command recognized by the FPGA is a read operation command, the BMC performs a read operation on the VRM;
[0010] If the command recognized by the FPGA is a write operation command, the FPGA determines whether to perform a write operation on the VRM based on whether the key input by the BMC is correct.
[0011] In a possible implementation, the step of sending a read / write operation command to the FPGA through the BMC includes:
[0012] Connecting the GPIO interface of the BMC to the input interface of the FPGA;
[0013] The read and write operation commands are transmitted to the FPGA through the GPIO interface.
[0014] In a possible implementation, the step of the BMC performing a read operation on the VRM includes:
[0015] Using the VR status register in the FPGA to collect information in the VRM;
[0016] The BMC reads the VRM information stored in the VR status register.
[0017] In a possible implementation, the step of the FPGA judging whether to perform a write operation on the VRM according to whether the key input by the BMC is correct includes:
[0018] The BMC performs a key write operation on a key register in the FPGA;
[0019] Verifying the key written into the key register by the BMC and the key pre-stored in the key register;
[0020] The FPGA controls the opening and closing of the write channel from the BMC to the VRM according to the key verification result.
[0021] In a possible implementation, the step of the FPGA controlling the opening and closing of the write channel from the BMC to the VRM according to the key verification result includes:
[0022] If the FPGA verifies that the key is correct, the FPGA opens the write channel from the BMC to the VRM;
[0023] If the FPGA checks the key incorrectly, the FPGA closes the write channel from the BMC to the VRM.
[0024] In a possible implementation, if the command recognized by the FPGA is a write operation command, after the FPGA determines whether to perform a write operation on the VRM according to whether the key input by the BMC is correct, the method further includes the following steps:
[0025] After the BMC completes the write operation, the BMC sends a write channel closing notification to the FPGA;
[0026] The FPGA executes a write channel closing operation according to the received write channel closing notification, and switches to a BMC read-only mode.
[0027] In a possible implementation, the method further includes the following steps:
[0028] If the FPGA detects an error in the process of receiving, parsing or executing the read / write operation command, the FPGA records the error information;
[0029] After receiving the error notification from the BMC, the BMC closes the communication channel between the BMC and the VRM.
[0030] A second aspect of the present application provides a VRM communication security encryption device, the device comprising:
[0031] A command acquisition unit, used to acquire the read and write operation commands sent by the BMC to the VRM through the FPGA;
[0032] A parsing unit, used for the FPGA to identify the received read and write operation commands;
[0033] A read command judgment unit, configured to cause the BMC to perform a read operation on the VRM if the command recognized by the FPGA is a read operation command;
[0034] A write command judgment unit is used for judging whether to perform a write operation on the VRM according to whether the key input by the BMC is correct if the command recognized by the FPGA is a write operation command.
[0035] A third aspect of the present application provides a computer device, characterized in that the computer device includes a memory and a processor, the memory stores a computer program, and the processor implements the method described in the first aspect when executing the computer program.
[0036] A fourth aspect of the present application provides a computer-readable storage medium, wherein the storage medium stores a computer program, wherein the computer program includes program instructions, and when the program instructions are executed by a processor, the method described in the first aspect above can be implemented.
[0037] The beneficial effects of the present invention compared with the prior art are as follows: the present invention provides a VRM communication security encryption method, device, equipment and medium, the method comprising the following steps: obtaining the read and write operation commands sent by the BMC to the VRM through the FPGA; the FPGA identifies the received read and write operation commands; if the command identified by the FPGA is a read operation command, the BMC performs a read operation on the VRM; if the command identified by the FPGA is a write operation command, the FPGA determines whether to perform a write operation on the VRM based on whether the key input by the BMC is correct. Compared with the prior art, the present invention introduces FPGA as an intermediary and a key verification mechanism. When the BMC needs to write to the VRM, it needs to check the key with the FPGA. Only after the key is checked correctly can the write mode be switched. If the key is not checked correctly, the BMC can only read the VRM. Through this method, the present invention can prevent unauthorized access and solve potential security risks, thereby strengthening the communication security encryption of the BMC to the VRM. BRIEF DESCRIPTION OF THE DRAWINGS
[0038] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying any creative work.
[0039] Figure 1 A schematic diagram of the hardware structure of a VRM communication security encryption method provided by an embodiment of the present invention;
[0040] Figure 2 A schematic diagram of a VRM communication security encryption method provided by an embodiment of the present invention Figure 1 ;
[0041] Figure 3 A schematic diagram of a VRM communication security encryption method provided by an embodiment of the present invention Figure 2 ;
[0042] Figure 4 A schematic diagram of a VRM communication security encryption method provided by an embodiment of the present invention Figure 3 ;
[0043] Figure 5 A schematic diagram of a VRM communication security encryption method provided by an embodiment of the present invention Figure 4 ;
[0044] Figure 6 A schematic diagram of a VRM communication security encryption method provided by an embodiment of the present invention Figure 5 ;
[0045] Figure 7 A schematic diagram of a VRM communication security encryption method provided by an embodiment of the present invention Figure 6
[0046] Figure 8 A schematic diagram of a VRM communication security encryption method provided by an embodiment of the present invention Figure 7 ;
[0047] Fig. 9 A schematic block diagram of a VRM communication security encryption device provided by an embodiment of the present invention;
[0048] Fig.10 A schematic block diagram of a computer device provided in an embodiment of the present invention. DETAILED DESCRIPTION
[0049] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0050] It should be understood that when used in this specification and the appended claims, the terms "include" and "comprises" indicate the presence of described features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.
[0051] It should also be understood that the terms used in this specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used in the specification of the present invention and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms.
[0052] It should be further understood that the term "and / or" used in the present description and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.
[0053] The embodiments of the present application provide a VRM communication security encryption method, device, equipment and storage medium.
[0054] The executor of the VRM communication security encryption method may be the VRM communication security encryption device provided in the embodiment of the present application, or a computer device integrating the VRM communication security encryption device, wherein the VRM communication security encryption device may be implemented in hardware or software, the computer device may be a terminal or a server, and the terminal may be a smart phone, a tablet computer, a PDA, or a laptop computer, etc.
[0055] Figure 1 Schematic diagram of the hardware framework structure of a VRM communication security encryption method provided by the embodiment of the present application. Figure 1 As shown, the hardware configuration includes: Lan (local area network), BMC (baseboard management controller), FPGA (field programmable gate array), VRM (VRM) and Device IC (integrated circuit device), wherein the FPGA includes a key register and a VR status register, the BMC is connected to Lan, the BMC and the FPGA are communicated, the read and write operations of the VRM are controlled by the FPGA, the BMC and the VRM are connected through the I2C bus (wherein, I2C is a two-wire serial bus used to connect a microcontroller and its peripheral devices, it only requires two bus lines: a serial data line (SDA) and a serial clock line (SCL); SMBus is an extension of I2C, mainly used for system management, such as power management, temperature monitoring, etc.) switch, and the VRM is electrically connected to the Device IC.
[0056] Specifically, this hardware framework structure provides a hardware integration method between VRM, BMC, FPGA and Device IC. Among them, the possibility of remote management and monitoring is realized by connecting BMC to Lan (local area network); the communication connection between BMC and FPGA enables FPGA to act as a control intermediary to read and write operations on VRM. FPGA includes key registers and VR status registers, which are used to store encryption keys and VRM status information, providing a hardware foundation for realizing secure encrypted communication.
[0057] Figure 2 This is a schematic diagram of a VRM communication security encryption method provided in an embodiment of the present application. Figure 1 .
[0058] like Figure 2 As shown, the method includes the following steps S110-S140:
[0059] S110, sending read and write operation commands to FPGA through BMC;
[0060] Specifically, the I2C / SMBUS from BMC to VRM is not directly connected, and information is transferred through FPGA. BMC sends read and write operation commands to FPGA through a specific communication protocol (such as I2C, SPI, etc.), and the command contains the operation type (read or write) and related parameters (such as address, data, etc.).
[0061] S120, FPGA identifies the received read and write operation commands;
[0062] Specifically, after receiving the command sent by the BMC, the FPGA first determines the type of command. If the command is a read operation command, the FPGA will allow the BMC to perform a read operation on the VRM and return the read data to the BMC. If the command is a write operation command, the FPGA will enter the next key verification phase.
[0063] S130: If the command recognized by the FPGA is a read operation command, the BMC performs a read operation on the VRM;
[0064] Specifically, the FPGA collects the information required by the BMC from the VRM information through I2C and puts it into the VR status register in the FPGA. The BMC can only read the VR status register in the FPGA through I2C.
[0065] S140: If the command recognized by the FPGA is a write operation command, the FPGA determines whether to perform a write operation on the VRM based on whether the key input by the BMC is correct.
[0066] Specifically, when the BMC needs to write to the VRM, it enters the write mode, and the BMC notifies the FPGA of the write operation through its own GPIO, and writes the key to the key register through I2C. The key register inside the FPGA stores the correct key or the hash value of the key, which is used to compare with the key provided by the BMC. If the key provided by the BMC matches the key stored in the key register, the FPGA will allow the BMC to perform a write operation on the VRM. If the keys do not match, the FPGA will reject the write operation and return an error prompt to the BMC.
[0067] In summary, the VRM communication security encryption method can effectively protect the data security of the VRM and prevent unauthorized access or tampering. At the same time, the method can also improve the overall security and reliability of the system.
[0068] like Figure 3 As shown, in a more specific embodiment, executing step S110 further specifically includes executing steps S111-S112:
[0069] S111, connecting the GPIO interface of the BMC to the input interface of the FPGA;
[0070] S112, the read and write operation commands are transmitted to the FPGA through the GPIO interface.
[0071] Specifically, on the BMC side, the read and write operation commands are encoded into a signal form that can be recognized by the GPIO interface, which involves converting the command into binary code and adding necessary synchronization or check bits to ensure the accuracy of data transmission. Through the GPIO interface, the encoded read and write operation commands are transmitted to the FPGA. During the transmission process, the stability and integrity of the signal need to be ensured to avoid transmission errors caused by electrical interference or signal attenuation. The FPGA receives the GPIO signal from the BMC and decodes it to restore the original read and write operation command. The decoding process includes removing the synchronization or check bits and converting the binary code into a recognizable command format.
[0072] like Figure 4 As shown, in a more specific embodiment, executing step S130 further specifically includes executing steps S131-S132:
[0073] S131, using the VR status register in the FPGA to collect information in the VRM;
[0074] S132. The BMC reads the VRM information stored in the VR status register.
[0075] Specifically, the FPGA is connected to the VRM via I2C. The FPGA reads relevant information such as voltage, current, power, temperature, etc. from the VRM periodically or according to the request of the BMC. The read request of the BMC usually contains the address or index of the VR status register to be read. After receiving the read request of the BMC, the FPGA reads the information from the corresponding VR status register. Then, the FPGA transmits this information to the BMC through the communication interface. After receiving the information transmitted by the FPGA, the BMC performs necessary processing or analysis. This information is used to monitor the status of the VRM, diagnose faults, optimize power management, etc. Through the above implementation, the BMC can safely and accurately read the VRM information stored in the VR status register in the FPGA, thereby providing the necessary data reading basis for implementing the VRM communication security encryption method.
[0076] like Figure 5 As shown, in a more specific embodiment, executing step S140 further specifically includes executing steps S141-S143:
[0077] S141, BMC performs a write key operation on the key register in the FPGA;
[0078] Specifically, a stable communication is established between the BMC and the FPGA through the I2C communication protocol. The BMC sends key data to the FPGA through the established communication protocol. The FPGA receives the key data and stores it in a designated key register.
[0079] S142, verifying the key written into the key register by the BMC and the key pre-stored in the key register;
[0080] Specifically, the FPGA reads the key that the BMC has just written and the original key pre-stored in the register from the key register. A verification module is set inside the FPGA to compare whether the two keys are consistent. The verification module can use a bit-by-bit comparison method to ensure that the two keys are the same in every bit. If the two keys are consistent, the verification module outputs a signal indicating success (such as a high level). If the two keys are inconsistent, the verification module outputs a signal indicating failure (such as a low level)
[0081] S143. FPGA controls the opening and closing of the write channel from BMC to VRM according to the key verification result.
[0082] Specifically, a control logic module is provided inside the FPGA to control the opening and closing of the write channel according to the key verification result. When the key verification succeeds, the control logic module opens the write channel from the BMC to the VRM. When the key verification fails, the control logic module closes the write channel. When the write channel is open, the BMC can send write operation instructions and data to the VRM, and after receiving the instructions and data, the VRM performs the corresponding write operation.
[0083] like Figure 6 As shown, in a more specific embodiment, executing step S143 further specifically includes executing steps S1431-S1432:
[0084] S1431, if the FPGA verifies that the key is correct, the FPGA opens the write channel from BMC to VRM;
[0085] S1432: If the FPGA verifies the key incorrectly, the FPGA closes the write channel from the BMC to the VRM.
[0086] like Figure 7 As shown, in a more specific embodiment, after executing step S140, the following steps S150-S160 are further specifically executed:
[0087] S150, after the BMC completes the write operation, the BMC sends a write channel closing notification to the FPGA;
[0088] S160: The FPGA executes a write channel closing operation according to the received write channel closing notification, and switches to a BMC read-only mode.
[0089] Specifically, the FPGA continuously monitors the communication channel from the BMC. When the FPGA receives a write channel closure notification from the BMC, it immediately parses the notification. Based on the parsed notification content, the FPGA executes the operation of closing the write channel, which involves updating internal registers, disabling circuits or logic related to write operations, etc. After closing the write channel, the FPGA switches to the BMC read-only mode. In this mode, the FPGA only allows the BMC to read data or status information, but not write operations, which helps protect the system from unauthorized modification or damage. Secondly, the FPGA can send a status signal to the BMC to confirm that the write channel has been closed and switched to read-only mode, which helps the BMC understand the current system status and take corresponding subsequent operations.
[0090] like Figure 8 As shown, in a more specific embodiment, it also includes executing steps S210-S220:
[0091] S210, if the FPGA detects an error in the process of receiving, parsing or executing the read / write operation command, the FPGA records the error information;
[0092] Specifically, when the FPGA receives, parses, or executes the read and write operation commands sent by the BMC, the FPGA will detect in real time whether there are any anomalies or errors. These errors may include communication failures, data format errors, command execution failures, etc. Once the FPGA detects an error, it will immediately record the relevant error information, which includes the error type, error code, timestamp of the error, and the commands and data involved.
[0093] S220: After receiving the error notification from the BMC, the BMC closes the communication channel between the BMC and the VRM.
[0094] Specifically, the BMC continuously listens for error notifications from the FPGA. Once an error notification is received, the BMC will immediately parse and process the error information. Based on the information in the error notification, the BMC will decide whether to close the communication channel with the VRM. If the error is serious enough to affect the security and reliability of communication, the BMC will execute the operation of closing the communication channel, which can be achieved by sending an instruction to close the communication channel to the FPGA, or by other mechanisms to ensure the closure of the communication channel. After closing the communication channel, the BMC can start the fault recovery process, including restarting the FPGA, VRM, or the entire system to try to restore normal communication and operation. At the same time, the BMC can also record relevant information during the fault recovery process for subsequent analysis and improvement.
[0095] Fig. 9is a schematic block diagram of a VRM communication security encryption device provided by an embodiment of the present application. Fig. 9 As shown, corresponding to the above VRM communication security encryption method, the present application also provides a VRM communication security encryption device 200. The VRM communication security encryption device 200 includes a unit for executing the above VRM communication security encryption method, and the device can be configured in a desktop computer, tablet computer, laptop, etc.
[0096] Specifically, see Fig. 9 , the VRM communication security encryption device 200 comprises:
[0097] The command acquisition unit 210 is used to acquire the read and write operation commands sent by the BMC to the VRM through the FPGA;
[0098] The parsing unit 220 is used for the FPGA to identify the received read and write operation commands;
[0099] The read command judgment unit 230 is used for the BMC to perform a read operation on the VRM if the command recognized by the FPGA is a read operation command;
[0100] The write command judgment unit 240 is used to judge whether to perform a write operation on the VRM based on whether the key input by the BMC is correct if the command recognized by the FPGA is a write operation command.
[0101] In addition, more specifically, the command acquisition unit 210 is specifically used to: connect the GPIO interface of the BMC to the input interface of the FPGA; and transmit the read and write operation commands to the FPGA through the GPIO interface.
[0102] The read command judgment unit 230 is specifically used for: collecting information in the VRM by using the VR status register in the FPGA; and the BMC reads the VRM information stored in the VR status register.
[0103] The write command judgment unit 240 is specifically used for: the BMC performs a write key operation on the key register in the FPGA; the key written by the BMC in the key register is checked with the key pre-stored in the key register; the FPGA controls the opening and closing of the write channel from the BMC to the VRM according to the key check result. Among them, the FPGA controls the opening and closing of the write channel from the BMC to the VRM according to the key check result, and is also specifically used for: if the FPGA checks the key correctly, the FPGA opens the write channel from the BMC to the VRM; if the FPGA checks the key incorrectly, the FPGA closes the write channel from the BMC to the VRM.
[0104] Specifically, the VRM communication security encryption device 200 also includes:
[0105] Initialization unit: used for the BMC to send a write channel closing notification to the FPGA after the BMC completes the write operation; the FPGA executes the write channel closing operation according to the received write channel closing notification and switches to the BMC read-only mode.
[0106] Error detection unit: If the FPGA detects an error during the process of receiving, parsing or executing a read or write operation command, the FPGA records the error information; after the BMC receives the error notification from the BMC, the communication channel between the BMC and the VRM is closed.
[0107] It should be noted that technical personnel in the relevant field can clearly understand that the specific implementation process of the above-mentioned VRM communication security encryption device and each unit can refer to the corresponding description in the aforementioned method embodiment, and for the convenience and conciseness of the description, it will not be repeated here.
[0108] The VRM communication security encryption device 200 can be implemented in the form of a computer program. The computer program can be implemented in the form of a computer program. Fig.10 Runs on the computer device shown.
[0109] See also Fig.10 , Fig.10 300 is a schematic block diagram of a computer device provided in an embodiment of the present application. The computer device 300 may be a terminal or a server, wherein the terminal may be an electronic device with communication functions such as a smart phone, a tablet computer, a laptop computer, a desktop computer, a personal digital assistant, and a wearable device. The server may be an independent server or a server cluster composed of multiple servers.
[0110] See also Fig.10 The computer device 300 includes a processor 302 , a memory and a network interface 305 connected via a system bus 301 , wherein the memory may include a non-volatile storage medium 303 and an internal memory 304 .
[0111] The non-volatile storage medium 303 can store an operating system 3031 and a computer program 3032. The computer program 3032 includes program instructions, and when the program instructions are executed, the processor 302 can execute a VRM communication security encryption method.
[0112] The processor 302 is used to provide computing and control capabilities to support the operation of the entire computer device 300 .
[0113] The internal memory 304 provides an environment for the operation of the computer program 3032 in the non-volatile storage medium 303. When the computer program 3032 is executed by the processor 302, the processor 302 can execute a VRM communication security encryption method.
[0114] The network interface 305 is used to communicate with other devices over the network. Fig.10 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device 300 to which the solution of the present application is applied. The specific computer device 300 may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.
[0115] It should be understood that in the embodiment of the present application, the processor 302 may be a central processing unit (CPU), and the processor 302 may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Among them, the general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.
[0116] It can be understood by those skilled in the art that all or part of the processes in the method for implementing the above embodiment can be completed by instructing the relevant hardware through a computer program. The computer program includes program instructions, and the computer program can be stored in a storage medium, which is a computer-readable storage medium. The program instructions are executed by at least one processor in the computer system to implement the process steps of the embodiment of the above method.
[0117] Therefore, the present application also provides a storage medium. The storage medium may be a computer-readable storage medium. The storage medium stores a computer program, wherein the computer program includes program instructions. When the program instructions are executed by a processor, the processor executes the following steps:
[0118] S110, sending read and write operation commands to FPGA through BMC;
[0119] S120, FPGA identifies the received read and write operation commands;
[0120] S130: If the command recognized by the FPGA is a read operation command, the BMC performs a read operation on the VRM;
[0121] S140: If the command recognized by the FPGA is a write operation command, the FPGA determines whether to perform a write operation on the VRM based on whether the key input by the BMC is correct.
[0122] The storage medium may be any computer-readable storage medium that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a magnetic disk, or an optical disk.
[0123] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.
[0124] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of each unit is only a logical function division, and there may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed.
[0125] The steps in the method of the embodiment of the present application can be adjusted in order, combined and deleted according to actual needs. The units in the device of the embodiment of the present application can be combined, divided and deleted according to actual needs. In addition, the functional units in the various embodiments of the present application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.
[0126] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, terminal, or network device, etc.) to perform all or part of the steps of the methods of each embodiment of the present application.
[0127] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, and these modifications or replacements should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.
Claims
1. A VRM communication security encryption method, characterized in that: The following steps are involved: Send read and write operation commands to FPGA through BMC; The FPGA identifies the received read and write operation commands; If the command recognized by the FPGA is a read operation command, the BMC performs a read operation on the VRM; If the command recognized by the FPGA is a write operation command, the FPGA determines whether to perform a write operation on the VRM based on whether the key input by the BMC is correct.
2. The VRM communication security encryption method according to claim 1, characterized in that: The step of sending a read / write operation command to the FPGA through the BMC includes: Connecting the GPIO interface of the BMC to the input interface of the FPGA; The read and write operation commands are transmitted to the FPGA through the GPIO interface.
3. The VRM communication security encryption method according to claim 1, characterized in that: The step of the BMC performing a read operation on the VRM comprises: Using the VR status register in the FPGA to collect information in the VRM; The BMC reads the VRM information stored in the VR status register.
4. The VRM communication security encryption method according to claim 1, characterized in that: The step of the FPGA judging whether to perform a write operation on the VRM according to whether the key input by the BMC is correct includes: The BMC performs a key write operation on a key register in the FPGA; Verifying the key written into the key register by the BMC and the key pre-stored in the key register; The FPGA controls the opening and closing of the write channel from the BMC to the VRM according to the key verification result.
5. The VRM communication security encryption method according to claim 4, characterized in that: The step of the FPGA controlling the opening and closing of the write channel from the BMC to the VRM according to the key verification result includes: If the FPGA verifies that the key is correct, the FPGA opens the write channel from the BMC to the VRM; If the FPGA checks the key incorrectly, the FPGA closes the write channel from the BMC to the VRM.
6. The VRM communication security encryption method according to claim 1, characterized in that: After the FPGA determines whether to perform a write operation on the VRM based on whether the key input by the BMC is correct if the command recognized by the FPGA is a write operation command, the method further includes the following steps: After the BMC completes the write operation, the BMC sends a write channel closing notification to the FPGA; The FPGA executes a write channel closing operation according to the received write channel closing notification, and switches to a BMC read-only mode.
7. The VRM communication security encryption method according to any one of claims 1 to 6, characterized in that: The following steps are also included: If the FPGA detects an error in the process of receiving, parsing or executing the read / write operation command, the FPGA records the error information; After receiving the error notification from the BMC, the BMC closes the communication channel between the BMC and the VRM.
8. A VRM communication security encryption device, characterized in that: The device comprises: A command acquisition unit, used to acquire the read and write operation commands sent by the BMC to the VRM through the FPGA; A parsing unit, used for the FPGA to identify the received read and write operation commands; A read command judgment unit, configured to cause the BMC to perform a read operation on the VRM if the command recognized by the FPGA is a read operation command; A write command judgment unit is used for judging whether to perform a write operation on the VRM according to whether the key input by the BMC is correct if the command recognized by the FPGA is a write operation command.
9. A computer device, characterized in that: The computer device includes a memory and a processor, the memory stores a computer program, and the processor implements the method according to any one of claims 1 to 7 when executing the computer program.
10. A computer-readable storage medium, characterized in that: The storage medium stores a computer program, wherein the computer program includes program instructions, and when the program instructions are executed by a processor, the method according to any one of claims 1 to 7 can be implemented.