Electronic package and fabrication method thereof

Abstract

An electronic package and a manufacturing method thereof are provided, mainly an electronic component stacking structure is arranged on a bearing structure to integrate a plurality of chips in a single package, so that the electronic package can meet the requirement of miniaturization without increasing the layout area of the bearing structure.

Description

Technical Field

[0001] The present invention relates to a semiconductor packaging process, in particular to an electronic package with stacked chips and a manufacturing method thereof. Background Art

[0002] With the evolution of semiconductor packaging technology, semiconductor devices have developed different packaging types. In order to improve electrical functions and save packaging space, different three-dimensional packaging technologies have been developed, such as Fan Out Package on Package (FO PoP), etc., to match the greatly increased number of input / output ports on various chips, and then integrate integrated circuits with different functions into a single package structure. This packaging method can give full play to the heterogeneous integration characteristics of the system package (SiP), and can achieve system integration of electronic components with different functions, such as memory, central processing unit, graphics processor, image application processor, etc. through stacking design, which is suitable for various thin and light electronic products.

[0003] Figure 1 FIG. 1 is a cross-sectional schematic diagram of an existing semiconductor package 1. Figure 1 As shown, the semiconductor package 1 includes a package substrate 10 having at least one circuit layer 101 , and a semiconductor element 11 bonded to the circuit layer 101 by flip chip method.

[0004] Specifically, the semiconductor element 11 has an active surface 11a and an inactive surface 11b opposite to each other. The active surface 11a has a plurality of electrode pads 110 to electrically connect the circuit layer 101 through a plurality of solder bumps 12 , and a primer 13 is formed between the semiconductor element 11 and the circuit layer 101 to cover the solder bumps 12 .

[0005] Furthermore, the semiconductor package 1 forms a packaging colloid 15 on the packaging substrate 10 to cover the base glue 13 and the semiconductor element 11, and a plurality of conductive through holes 14 are formed in the packaging colloid 15 so that the end surfaces of the conductive through holes 14 are exposed from the packaging colloid 15, so as to be subsequently combined with an electronic device (omitted) such as a semiconductor chip, a silicon interposer or a packaging structure through solder balls (omitted).

[0006] However, in the conventional semiconductor package 1, the exposed end surfaces of the conductive vias 14 are used as external contacts. Therefore, when the number of the external contacts increases, the spacing between the conductive vias 14 needs to be reduced. At this time, bridging is likely to occur between the solder balls on the end surfaces of the conductive vias 14.

[0007] Furthermore, if the conventional semiconductor package 1 needs more functions, more types of semiconductor elements 11 need to be disposed on the package substrate 10 , and the disposition area of ​​the package substrate 10 needs to be increased, thus increasing the size of the semiconductor package 1 .

[0008] Therefore, how to overcome the shortcomings of the prior art is a technical problem that all walks of life are eager to solve. Summary of the invention

[0009] In view of the various deficiencies of the above-mentioned prior art, the present invention provides an electronic package, including: a supporting structure, which has a first side and a second side opposite to each other, and a plurality of conductive columns electrically connected to the supporting structure are formed on the first side; a plurality of first electronic components, which are combined and electrically connected to the first side of the supporting structure; a second electronic component, which is combined to the plurality of first electronic components; a coating layer formed on the first side of the supporting structure so that the coating layer covers the plurality of first electronic components, the second electronic components and the plurality of conductive columns; and a circuit structure formed on the coating layer and electrically connecting the plurality of conductive columns and the second electronic components.

[0010] The present invention also provides a method for manufacturing an electronic package, comprising: providing a supporting structure having a first side and a second side opposite to each other, and forming a plurality of conductive pillars electrically connected to the supporting structure on the first side; setting an electronic component stacking structure on the first side of the supporting structure, wherein the electronic component stacking structure includes a plurality of first electronic components combined and electrically connected to the supporting structure and a second electronic component combined to the first electronic components; forming a coating layer on the first side of the supporting structure so that the coating layer covers the electronic component stacking structure and the plurality of conductive pillars, and the end surfaces of the plurality of conductive pillars and the second electronic component are exposed from the coating layer; and forming a circuit structure on the coating layer, and the circuit structure electrically connects the plurality of conductive pillars and the second electronic component.

[0011] In the aforementioned electronic package and its manufacturing method, each of the plurality of first electronic components has an active surface and an inactive surface opposite to each other, and the plurality of first electronic components are all connected to the supporting structure with their active surfaces.

[0012] In the aforementioned electronic package and its manufacturing method, each of the plurality of first electronic components has an active surface and an inactive surface opposite to each other, and one of the plurality of first electronic components is connected to the supporting structure with its active surface, and at least one is connected to the supporting structure with its inactive surface.

[0013] In the aforementioned electronic package and its manufacturing method, each of the plurality of first electronic components has an active surface and an inactive surface opposite to each other, and the plurality of first electronic components are all connected to the supporting structure with their inactive surfaces.

[0014] In the aforementioned electronic package and its manufacturing method, the plurality of first electronic components are electrically connected to the supporting structure by flip chip method or wire bonding method.

[0015] In the aforementioned electronic package and its manufacturing method, the second electronic component is arranged on the plurality of first electronic components through a bonding layer.

[0016] In the aforementioned electronic package and its manufacturing method, the second electronic element has an active surface and an inactive surface opposite to each other, and a plurality of conductive bumps electrically connected to the circuit structure are formed on the active surface.

[0017] In the aforementioned electronic package and its manufacturing method, the width of the second electronic component is smaller than the overall layout width of the plurality of first electronic components.

[0018] The aforementioned electronic package and its manufacturing method also include forming a plurality of solder balls on the second side of the supporting structure.

[0019] The aforementioned electronic package and its manufacturing method also include forming a plurality of conductive elements on the circuit structure.

[0020] As can be seen from the above, the electronic package and its manufacturing method of the present invention mainly integrate multiple chips into a single package through the design of the electronic component stacking structure. Not only does the electronic package meet the miniaturization requirements without increasing the layout area of ​​the supporting structure, but it can also increase the number of external contact points and avoid bridging between the conductive elements when applied to fine-pitch products. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a cross-sectional schematic diagram of a conventional semiconductor package.

[0022] FIG. 2A to FIG. 2E It is a cross-sectional schematic diagram of a method for manufacturing an electronic package of the present invention.

[0023] Figure 3 and Figure 4 for Figure 2E Schematic cross-sectional views of different forms.

[0024] Main component symbols

[0025] 1 Semiconductor Package

[0026] 10 Package substrate

[0027] 101 Circuit Layer

[0028] 11 Semiconductor components

[0029] 11a, 21a, 22a, 31a Action surface

[0030] 11b, 21b, 22b, 31b, 41b Non-active surface

[0031] 110,210,220 Electrode pads

[0032] 12,211 Solder Bumps

[0033] 13 Primer

[0034] 14 Conductive vias

[0035] 15 Encapsulation colloid

[0036] 2,3,4 Electronic packaging

[0037] 2a Electronic component stacking structure

[0038] 20 Load-bearing structure

[0039] 20a First side

[0040] 20b Second side

[0041] 200 Insulation protection layer

[0042] 201 Electrical contact pad

[0043] 202 Ball Planting Pad

[0044] 21,31,41 First Electronic Components

[0045] 211a Copper Block

[0046] 22 Second electronic component

[0047] 222 Conductive bump

[0048] 261,262 Line redistribution layer

[0049] 23 Conductive column

[0050] 24 Bonding layer

[0051] 25 Coating

[0052] 26 Line Structure

[0053] 260 Insulation layer

[0054] 27 Conductive element

[0055] 270 Under Bump Metal

[0056] 28 Passive components

[0057] 29 Solder balls

[0058] 311 welding wire

[0059] A,D Width

[0060] S Cutting path. DETAILED DESCRIPTION

[0061] The following describes the implementation of the present invention through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0062] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions under which the present invention can be implemented, so they have no substantial technical significance. Any structural modification, change in proportional relationship, or adjustment in size should still fall within the scope of the technical contents disclosed by the present invention without affecting the effects and purposes that can be achieved by the present invention. At the same time, the terms such as "on", "first", "second", and "one" quoted in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. Changes or adjustments in their relative relationships should also be regarded as the scope of the implementation of the present invention without substantially changing the technical contents.

[0063] FIG. 2A to FIG. 2E It is a cross-sectional schematic diagram of a method for manufacturing an electronic package 2 of the present invention.

[0064] like Figure 2A As shown, a supporting structure 20 is provided, which has a first side 20a and a second side 20b opposite to each other, and a plurality of conductive pillars 23 are formed on the first side 20a, and a plurality of first electronic components 21 are combined to the first side 20a of the supporting structure 20, and some of the first electronic components 21 are electrically connected to the supporting structure 20.

[0065] The supporting structure 20 is, for example, a package substrate with a core layer and a circuit structure, a package substrate with a coreless circuit structure, a silicon interposer (TSI) with conductive through-silicon via (TSV), or other board types, which include at least one insulating layer and at least one circuit layer combined with the insulating layer, such as at least one fan-out redistribution layer (RDL). It should be understood that the supporting structure 20 can also be other board materials for supporting chips, such as a leadframe, a wafer, or other boards with metal routing, etc., and is not limited to the above.

[0066] In this embodiment, the supporting structure 20 is a package substrate, which has a plurality of electrical contact pads 201 and an insulating protection layer 200 on the first side 20a, so that the insulating protection layer 200 exposes the electrical contact pads 201, and has a plurality of ball pads 202 on the second side 20b, and the supporting structure 20 has a plurality of circuit layers (not shown) inside to electrically connect the electrical contact pads 201 and the ball pads 202. For example, the material forming the electrical contact pads 201 and the ball pads 202 is copper, and the material forming the insulating protection layer 200 is a solder mask or a dielectric material such as polybenzoxazole (PBO), polyimide (PI), prepreg (PP), etc.

[0067] The conductive pillar 23 is disposed on the electrical contact pad 201 to electrically connect the supporting structure 20 , and the conductive pillar 23 is made of a metal material such as copper or a solder material.

[0068] The first electronic component 21 is an active component, a passive component or a combination of the two. The active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor and an inductor.

[0069] In this embodiment, the first electronic component 21 is a semiconductor chip, such as a microcontroller unit (MCU) or an application specific integrated circuit (ASIC), which has a relative active surface 21a and an inactive surface 21b, and the active surface 21a has a plurality of electrode pads 210, and the first electronic components 21 are all electrically connected to the electrical contact pad 201 and the electrode pad 210 in a flip-chip manner (such as through a plurality of solder bumps 211 having copper blocks 211a).

[0070] like Figure 2B As shown, a second electronic component 22 is combined on the first electronic components 21 so that the first electronic components 21 and the second electronic components 22 form an electronic component stacking structure 2 a.

[0071] The second electronic component 22 is an active component, a passive component or a combination of the two. The active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor and an inductor.

[0072] In this embodiment, the second electronic component 22 is a semiconductor chip, such as a dynamic random access memory (DRAM) or a power management chip (PMIC), which has an active surface 22a and an inactive surface 22b opposite to each other. The active surface 22a is provided with a plurality of electrode pads 220, and conductive bumps 222 such as copper pillars or solder balls are formed on the electrode pads 220.

[0073] Furthermore, the second electronic component 22 is bonded to the inactive surfaces 21b of the first electronic components 21 with its inactive surface 22b through a bonding layer 24. For example, the bonding layer 24 is formed on the inactive surface 22b of the second electronic component 22 first, and then the second electronic component 22 is bonded to the first electronic component 21 on the supporting structure 20. It should be understood that the bonding layer 24 can also be formed on the first electronic components 21 first, and then the second electronic component 22 is bonded to the bonding layer 24. Alternatively, the second electronic component 22 is first bonded to the first electronic components 21, and then the electronic component stacking structure 2a is bonded to the first side 20a of the supporting structure 20 with the first electronic components 21. The bonding layer 24 is, for example, a film over wire (FOW). In addition, the present invention can overcome the height difference of the first electronic components 21 due to different thicknesses by disposing the bonding layer 24 on the non-active surface 21 b of the first electronic component 21 , so that the second electronic component 22 can be stably placed on the first electronic components 21 .

[0074] In addition, the width D of the second electronic component 22 is smaller than the overall layout width A of the first electronic components 21 .

[0075] like Figure 2C As shown, a coating layer 25 is formed on the first side 20a of the supporting structure 20 so that the coating layer 25 covers the electronic component stacking structure 2a and the conductive pillars 23, and then through a flattening process, the end surface of the conductive pillar 23 and the conductive bump 222 of the second electronic component 22 are exposed from the coating layer 25.

[0076] In this embodiment, the coating layer 25 is an insulating material, such as polyimide (PI), dry film, or a packaging colloid or molding compound such as epoxy. For example, the coating layer 25 can be formed on the first side 20a of the supporting structure 20 by a process such as liquid compound, injection, lamination, or compression molding.

[0077] Furthermore, the flattening process removes part of the material of the conductive column 23 (part of the material of the conductive bump 222 can be removed as needed) and part of the material of the coating layer 25 by grinding, so that the end surface of the conductive column 23 and the conductive bump 222 of the second electronic component 22 are flush with the upper surface of the coating layer 25.

[0078] like Figure 2D As shown, a circuit structure 26 is formed on the encapsulation layer 25, and the circuit structure 26 electrically connects the conductive pillars 23 and the plurality of conductive bumps 222 of the second electronic component 22, so that the second electronic component 22 can be electrically connected to the first electronic components 21 through the circuit structure 26, the conductive pillars 23 and the supporting structure 20.

[0079] In this embodiment, the circuit structure 26 includes a plurality of insulating layers 260 and a plurality of redistribution layers (RDL) 261 disposed on the insulating layers 260, and the outermost insulating layer 260 can be used as a solder mask so that the outermost redistribution layer 262 is exposed from the solder mask for combining a plurality of conductive elements such as solder bumps 27. Alternatively, the circuit structure 26 can also include only a single insulating layer 260 and a single redistribution layer 261.

[0080] Furthermore, the material forming the redistribution layers 261 and 262 is copper, and the material forming the insulation layer 260 is a dielectric material such as poly(p-oxadiazole) (PBO), polyimide (PI), or prepreg (PP).

[0081] In addition, an under bump metallurgy (UBM) 270 may be formed on the outermost redistribution layer 262 to facilitate the combination of the conductive element 27 .

[0082] like Figure 2E As shown, along Figure 2D The cutting path S shown is used for performing a singulation process to complete the electronic package 2 of the present invention.

[0083] In subsequent manufacturing processes, the electronic package 2 can be connected to an electronic device (not shown) such as a packaging structure or other structures (such as another package or chip) through the conductive elements 27 .

[0084] Furthermore, the electronic package 2 can also form a plurality of solder balls 29 on the ball pad 202 of the second side 20b of the supporting structure 20 for subsequent connection with an electronic device such as a packaging structure or other structures (such as a circuit board, another package or chip) (not shown).

[0085] In addition, the passive component 28 can be combined and electrically connected to the second side 20 b of the supporting structure 20 .

[0086] In addition, if Figure 3 In another embodiment of the electronic package 3 shown, one of the first electronic components 21, 31 can be electrically connected to the supporting structure 20 by wire bonding. For example, the first electronic component 31 is disposed on the first side 20a of the supporting structure 20 with its inactive surface 31b, and connected to the electrical contact pad 201 with a welding wire 311, and the other first electronic component 21 is disposed on the first side 20a of the supporting structure 20 with its active surface 21a, and the second electronic component 22 is bonded to the active surface 31a of the first electronic component 31 and the inactive surface 21b of the first electronic component 21 with its inactive surface 22b through a bonding layer 24, wherein the bonding layer 24 may or may not cover the welding wire 311.

[0087] It should be understandable that Figure 4 In the electronic package 4 shown, the first electronic components 31 , 41 are placed on the supporting structure 20 with their inactive surfaces 31 b , 41 b , and are electrically connected to the supporting structure 20 by wire bonding.

[0088] Therefore, the manufacturing method of the electronic package 2, 3, 4 of the present invention is to stack multiple chips (i.e., the first and second electronic components 21, 31, 41, 22) to form the electronic component stacking structure 2a, so that the electronic package 2, 3, 4 has chips with multiple functions. Therefore, compared with the prior art, the electronic package 2, 3, 4 of the present invention can not only provide more functions, but also does not need to increase the layout area of ​​the first side 20a of the supporting structure 20, and can thus effectively meet the miniaturized size requirements of the electronic package 2, 3, 4.

[0089] Furthermore, the contact pads of the circuit structure 26 (i.e., the circuit redistribution layer 262 exposed on the surface of the insulating layer 260) are used as external contacts to facilitate controlling the distance between the external contacts to meet the requirements of fine pitch and avoid bridging between the conductive elements 27.

[0090] The present invention also provides an electronic package 2 , 3 , 4 , comprising: a supporting structure 20 , a plurality of first electronic components 21 , 31 , 41 , a second electronic component 22 , a coating layer 25 and a circuit structure 26 .

[0091] The supporting structure 20 has a first side 20 a and a second side 20 b opposite to each other. A plurality of conductive pillars 23 electrically connected to the supporting structure 20 are formed on the first side 20 a .

[0092] The first electronic components 21 , 31 , 41 are combined and electrically connected to the supporting structure 20 .

[0093] The second electronic component 22 is coupled to the plurality of first electronic components 21 , 31 , 41 .

[0094] The encapsulation layer 25 is formed on the first side 20 a of the supporting structure 20 , so that the encapsulation layer 25 encapsulates the first electronic components 21 , 31 , 41 , the second electronic component 22 and the conductive pillars 23 , and the end surfaces of the conductive pillars 23 and the second electronic component 22 are exposed from the encapsulation layer 25 .

[0095] The circuit structure 26 is formed on the cladding layer 25 , and the circuit structure 26 electrically connects the conductive pillar 23 and the second electronic component 22 .

[0096] In one embodiment, the plurality of first electronic components 21 have opposite active surfaces 21 a and inactive surfaces 21 b , and the plurality of first electronic components 21 all face the supporting structure 20 with their active surfaces 21 a .

[0097] In one embodiment, one of the first electronic components 21 is connected to the supporting structure 20 with its active surface 21 a, and at least one first electronic component 31 is connected to the supporting structure 20 with its inactive surface 31 b.

[0098] In one embodiment, the first electronic components 31 , 41 are all connected to the supporting structure 20 with their inactive surfaces 31 b , 41 b .

[0099] In one embodiment, at least one of the first electronic components 21 is electrically connected to the supporting structure 20 by flip chip method.

[0100] In one embodiment, at least one of the first electronic components 31 , 41 is electrically connected to the supporting structure 20 by wire bonding.

[0101] In one embodiment, the second electronic component 22 is stacked on the first electronic components 21 , 31 , 41 via a bonding layer 24 .

[0102] In one embodiment, the second electronic component 22 has a plurality of conductive bumps 222 electrically connected to the circuit structure 26 .

[0103] In one embodiment, a width D of the second electronic component 22 is smaller than an overall layout width A of the first electronic components 21 .

[0104] In one embodiment, the electronic package 2 , 3 , 4 further includes a plurality of solder balls 29 formed on the second side 20 b of the supporting structure 20 .

[0105] In one embodiment, the electronic package 2 , 3 , 4 further includes a plurality of conductive elements 27 formed on the circuit structure 26 .

[0106] In summary, the electronic package and its manufacturing method of the present invention integrate multiple chips into a single package through the design of the electronic component stacking structure, which not only makes the size of the electronic package meet the needs of miniaturization, but also increases the number of external contact points, and when applied to fine-pitch products, it can avoid bridging between the conductive elements.

[0107] The above embodiments are only used to illustrate the principles and effects of the present invention, and are not used to limit the present invention. Any person skilled in the art may modify the above embodiments without violating the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as listed in the claims.

Claims

1. An electronic package, comprising: A supporting structure having a first side and a second side opposite to each other, and a plurality of conductive posts electrically connected to the supporting structure are disposed on the first side; a plurality of first electronic components combined and electrically connected to the first side of the supporting structure; a second electronic component bonded to the plurality of first electronic components; A coating layer formed on the first side of the supporting structure so that the coating layer covers the first electronic components, the second electronic components and the conductive pillars; as well as A circuit structure is formed on the cladding layer and electrically connects the plurality of conductive pillars and the second electronic element.

2. The electronic package of claim 1, wherein: Each of the plurality of first electronic components has an active surface and an inactive surface opposite to each other, and the plurality of first electronic components are all connected to the supporting structure with their active surfaces.

3. The electronic package of claim 1, wherein: Each of the plurality of first electronic components has an active surface and an inactive surface opposite to each other, and one of the plurality of first electronic components is connected to the supporting structure with its active surface, and at least one of the plurality of first electronic components is connected to the supporting structure with its inactive surface.

4. The electronic package of claim 1, wherein: Each of the plurality of first electronic components has an active surface and an inactive surface opposite to each other, and the plurality of first electronic components are all connected to the supporting structure with their inactive surfaces.

5. The electronic package of claim 1, wherein: The plurality of first electronic components are electrically connected to the supporting structure by flip chip method or wire bonding method.

6. The electronic package of claim 1, wherein: The second electronic component is arranged on the plurality of first electronic components through a bonding layer.

7. The electronic package of claim 1, wherein: The second electronic element has an active surface and an inactive surface opposite to each other. A plurality of conductive bumps electrically connected to the circuit structure are formed on the active surface.

8. The electronic package of claim 1, wherein: The width of the second electronic component is smaller than the overall layout width of the plurality of first electronic components.

9. The electronic package of claim 1, wherein: The electronic package also includes a plurality of solder balls formed on the second side of the carrier structure.

10. The electronic package of claim 1, wherein: The electronic package also includes a plurality of conductive elements formed on the circuit structure.

11. A method for manufacturing an electronic package, comprising: Providing a supporting structure having a first side and a second side opposite to each other, wherein a plurality of conductive pillars electrically connected to the supporting structure are formed on the first side; Disposing an electronic component stacking structure on the first side of the supporting structure, wherein the electronic component stacking structure includes a plurality of first electronic components combined and electrically connected to the supporting structure and a second electronic component combined to the plurality of first electronic components; forming a coating layer on the first side of the supporting structure, so that the coating layer covers the electronic component stacking structure and the plurality of conductive pillars, and the end surfaces of the plurality of conductive pillars and the second electronic component are exposed from the coating layer; and A circuit structure is formed on the cladding layer, and the circuit structure is electrically connected to the plurality of conductive pillars and the second electronic element.

12. The method for manufacturing an electronic package according to claim 11, wherein: Each of the plurality of first electronic components has an active surface and an inactive surface opposite to each other, and the plurality of first electronic components are all connected to the supporting structure with their active surfaces.

13. The method for manufacturing an electronic package according to claim 11, wherein: Each of the plurality of first electronic components has an active surface and an inactive surface opposite to each other, and one of the plurality of first electronic components is connected to the supporting structure with its active surface, and at least one of the plurality of first electronic components is connected to the supporting structure with its inactive surface.

14. The method for manufacturing an electronic package according to claim 11, wherein: Each of the plurality of first electronic components has an active surface and an inactive surface opposite to each other, and the plurality of first electronic components are all connected to the supporting structure with their inactive surfaces.

15. The method for manufacturing an electronic package according to claim 11, wherein: The plurality of first electronic components are electrically connected to the supporting structure by flip chip method or wire bonding method.

16. The method for manufacturing an electronic package according to claim 11, wherein: The second electronic component is arranged on the plurality of first electronic components through a bonding layer.

17. The method for manufacturing an electronic package according to claim 11, wherein: The second electronic element has an active surface and an inactive surface opposite to each other. A plurality of conductive bumps electrically connected to the circuit structure are formed on the active surface.

18. The method for manufacturing an electronic package according to claim 11, wherein: The width of the second electronic component is smaller than the overall layout width of the plurality of first electronic components.

19. The method for manufacturing an electronic package according to claim 11, wherein: The method also includes forming a plurality of solder balls on the second side of the supporting structure.

20. The method for manufacturing an electronic package according to claim 11, wherein: The manufacturing method also includes forming a plurality of conductive elements on the circuit structure.

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