Memory, preparation method of memory and electronic equipment

Abstract

The embodiment of the invention provides a memory, a preparation method of the memory and electronic equipment. Relates to the technical field of semiconductor storage. The purpose is to improve the storage density. The memory comprises a semiconductor substrate, a front-channel device layer and a rear-channel device layer, the front-channel device layer is arranged in the semiconductor substrate, and the rear-channel device layer is arranged above the front-channel device layer; a storage array and a logic circuit are integrated in the memory, and the logic circuit comprises at least one P-type field effect transistor and at least one N-type field effect transistor. At least one P-type field effect transistor is formed in the front channel device layer; at least one N-type field effect transistor is formed in the back-end device layer. The vertical projection area of the logic circuit on the semiconductor substrate is reduced by three-dimensionally stacking the P-type field effect transistor and the N-type field effect transistor in the logic circuit, so that the vertical projection area of the storage array can be increased, and the storage density and capacity are improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor storage technology, and in particular to a memory, an electronic device including the memory, and a method for preparing the memory. Background Art

[0002] With the continuous development of artificial intelligence (AI) and high performance computing (HPC), computing technology has gradually increased the demand for large-capacity and high-density storage devices.

[0003] The current mainstream memory, in addition to the memory array composed of memory cells for storing bits, also has a large number of peripheral circuits composed of logic circuits, such as control circuits (Control Logic), decoding circuits (Decoder circuit), data selection circuits (Data Mux Logic) and driver circuits (Drivers) and sense amplifier circuits (Sense Amplifier circuit). These logic circuits, together with the memory array, constitute the memory.

[0004] However, a large number of logic circuits occupy a large area of ​​the memory, making it impossible to further improve the storage density and storage capacity of the memory. For example, in mainstream DDR chips, the effective area of ​​the storage array (also known as array efficiency) accounts for less than 60%; the effective area of ​​the storage array of SRAM memory is less than 50%, which seriously restricts the improvement of storage capacity. Summary of the invention

[0005] The present application provides a memory integrated with a memory array and a logic circuit, a method for preparing the memory, and an electronic device including the memory, with the purpose of improving storage density and storage capacity.

[0006] In order to achieve the above purpose, this application adopts the following technical solutions:

[0007] On the one hand, the present application provides a memory, for example, the memory may be an SRAM memory, or a DRAM memory, or other types of memory.

[0008] The memory includes a semiconductor substrate, a front-end device layer and a back-end device layer, wherein the front-end device layer is arranged in the semiconductor substrate and the back-end device layer is arranged above the front-end device layer; the memory integrates a storage array and a logic circuit for controlling the reading and writing of the storage array, wherein the logic circuit includes, for example, a CMOS circuit, and the logic circuit includes at least one P-type field effect transistor and at least one N-type field effect transistor; at least one P-type field effect transistor is formed in the front-end device layer; and at least one N-type field effect transistor is formed in the back-end device layer.

[0009] In the memory provided in the present application, since the P-type field effect transistors in the logic circuit are manufactured in the front-end device layer using the front-end process, and the N-type field effect transistors are manufactured in the back-end device layer using the back-end process, that is, the P-type field effect transistors and the N-type field effect transistors are manufactured on the semiconductor substrate in a three-dimensional stacking manner. Compared with manufacturing all the P-type field effect transistors and the N-type field effect transistors using the front-end process, the present application can reduce the area occupied by the logic circuit (the area occupied on the semiconductor substrate), so that more space can be avoided for the layout of the storage array, the effective area of ​​the storage array can be increased, and the storage density and storage capacity can be increased.

[0010] In one achievable manner, an orthographic projection of the N-type field effect transistor on the semiconductor substrate at least partially overlaps with an orthographic projection of the P-type field effect transistor on the semiconductor substrate.

[0011] It can be understood that the P-type field effect transistor is basically located directly below the N-type field effect transistor. In this way, compared with manufacturing all P-type field effect transistors and N-type field effect transistors using front-end processes, the area of ​​the logic circuit of the present application can be reduced to half of the existing area, which significantly increases the effective area of ​​the storage array and improves the storage capacity density.

[0012] In one achievable manner, the at least one N-type field effect transistor includes a first N-type field effect transistor and a second N-type field effect transistor, and the first N-type field effect transistor and the second N-type field effect transistor are located in the same back-end device layer.

[0013] The N-type field effect transistors are arranged in the same back-end device layer, which can not only simplify the preparation process of each back-end device layer, but also reduce the number of stacked layers of the back-end device layer.

[0014] In one achievable manner, at least one N-type field effect transistor is located in a first back-end device layer; a first interconnect routing layer is formed between the front-end device layer and the first back-end device layer; and at least one P-type field effect transistor is electrically connected to at least one N-type field effect transistor through the first interconnect routing layer.

[0015] The electrical connection between the P-type field effect transistor and the N-type field effect transistor in the logic circuit is realized by using the interconnection wiring layer stacked in the front-end device layer and the back-end device layer.

[0016] In one achievable manner, a second interconnection wiring layer is formed on a side of the first back-end device layer facing away from the front-end device layer; the input end, output end and voltage control end of the logic circuit are electrically connected to the peripheral circuit through the second interconnection wiring layer.

[0017] In one achievable manner, at least one P-type field effect transistor includes a first P-type field effect transistor and a second P-type field effect transistor; at least one N-type field effect transistor includes a first N-type field effect transistor and a second N-type field effect transistor; an orthographic projection of the first N-type field effect transistor on the semiconductor substrate at least partially overlaps with an orthographic projection of the first P-type field effect transistor on the semiconductor substrate; and an orthographic projection of the second N-type field effect transistor on the semiconductor substrate at least partially overlaps with an orthographic projection of the second P-type field effect transistor on the semiconductor substrate.

[0018] In some process structures, when there are M P-type field effect transistors in the front-end device layer, correspondingly, M N-type field effect transistors of the same number can be set in the back-end device layer, and each N-type field effect transistor is basically located directly above the P-type field effect transistor, that is, the vertical projections on the semiconductor substrate overlap. In this way, the vertical projection area of ​​the logic circuit on the semiconductor substrate can be further compressed.

[0019] In one achievable manner, a first P-type field effect transistor and a second P-type field effect transistor are coupled in parallel between a first voltage terminal and an output terminal; a first N-type field effect transistor and a second N-type field effect transistor are coupled in series between a second voltage terminal and an output terminal; a gate of the first P-type field effect transistor and a gate of the first N-type field effect transistor are electrically connected to a first input terminal, respectively; and a gate of the second P-type field effect transistor and a gate of the second N-type field effect transistor are electrically connected to a second input terminal, respectively.

[0020] In one achievable manner, the gate of the first P-type field effect transistor is electrically connected to the gate of the first N-type field effect transistor through the first interconnect routing layer; the gate of the second P-type field effect transistor is electrically connected to the gate of the second N-type field effect transistor through the first interconnect routing layer; the first electrode of the first N-type field effect transistor is electrically connected to the first electrode of the second N-type field effect transistor; the first electrode of the first P-type field effect transistor is electrically connected to the first electrode of the second P-type field effect transistor; and the second electrode of the first P-type field effect transistor is electrically connected to the second electrode of the second P-type field effect transistor.

[0021] In one achievable manner, a first P-type field effect transistor and a first N-type field effect transistor are coupled in series between a first voltage terminal and a second voltage terminal; a second P-type field effect transistor and a second N-type field effect transistor are coupled in series between the first voltage terminal and the second voltage terminal; a gate of the second P-type field effect transistor and a gate of the second N-type field effect transistor are electrically connected to a series coupling point of the first P-type field effect transistor and the first N-type field effect transistor, respectively.

[0022] In one achievable manner, the gate of the first P-type field effect transistor is electrically connected to the gate of the first N-type field effect transistor through a first interconnect routing layer; the first electrode of the first P-type field effect transistor is electrically connected to the first electrode of the first N-type field effect transistor through the first interconnect routing layer; the gate of the second P-type field effect transistor is electrically connected to the gate of the second N-type field effect transistor through the first interconnect routing layer; the first electrode of the second P-type field effect transistor is electrically connected to the first electrode of the second N-type field effect transistor through the first interconnect routing layer; and the first electrode of the first P-type field effect transistor is electrically connected to the gate of the second P-type field effect transistor.

[0023] The above examples show two different logic circuit structures. Of course, the logic circuit of the present application may also be other logic circuits. For example, in one implementable method, the logic circuit includes at least one of a control circuit, a decoding circuit, a data selection circuit, a drive circuit, and a sensitive amplifier circuit.

[0024] In one achievable manner, a memory array includes a plurality of memory cells, each memory cell including: a P-type field effect transistor and an N-type field effect transistor; the P-type field effect transistor in the memory cell is formed in a front-end device layer; and the N-type field effect transistor in the memory cell is formed in a back-end device layer.

[0025] The storage array structure of this memory is similar to the above-mentioned logic circuit. The P-type field effect transistor in the storage unit is manufactured in the front-end device layer using the front-end process, while the N-type field effect transistor is manufactured in the back-end device layer using the back-end process. Forming multiple field effect transistors in a storage unit in a three-dimensional stacking manner can also improve the storage density. In addition, since the multiple field effect transistors of the logic circuit are also formed in a three-dimensional stacking manner, more space is left for the layout of the storage array, thereby further improving the storage capacity.

[0026] In one achievable manner, the N-type field effect transistor in the memory cell and the N-type field effect transistor in the logic circuit are located in the same back-end device layer.

[0027] In the process, the same process can be used to manufacture storage cells and logic circuits.

[0028] In one achievable manner, an orthographic projection of an N-type field effect transistor in a memory cell on a semiconductor substrate at least partially overlaps with an orthographic projection of a P-type field effect transistor in the memory cell on a semiconductor substrate.

[0029] By adopting this process structure, the vertical projection area of ​​a memory cell can be reduced to 2 / N of the existing structure (all transistors of a memory cell are made by the front-end process). The storage density can be significantly improved. In one possible implementation, the channel material of at least one N-type field effect transistor includes an oxide semiconductor material.

[0030] When making N-type field effect transistors based on oxide semiconductor materials, it can be compatible with the back-end process.

[0031] On the other hand, the present application provides a method for preparing a memory, the method comprising:

[0032] Producing a storage array;

[0033] A logic circuit is prepared, and the logic circuit is used for reading and writing operations on the storage array;

[0034] The obtained logic circuit includes:

[0035] A front-end device layer is formed in a semiconductor substrate by a front-end process, wherein at least one P-type field effect transistor in a logic circuit is formed in the front-end device layer;

[0036] A back-end device layer is formed on the front-end device layer by adopting a back-end process, and at least one N-type field effect transistor in a logic circuit is formed in the back-end device layer.

[0037] In the preparation method of the memory provided in the present application, when preparing the logic circuit, the P-type field effect transistor in the logic circuit is manufactured using the front-end process, while the N-type field effect transistor is manufactured using the back-end process, so that the P-type field effect transistor and the N-type field effect transistor are stacked in three dimensions, which will compress the area of ​​the logic circuit projected onto the semiconductor substrate, thereby increasing the area of ​​the storage array projected onto the semiconductor substrate and improving the storage capacity density.

[0038] In one achievable method, when an N-type field effect transistor is manufactured using a back-end process, the method includes: manufacturing an N-type field effect transistor above a P-type field effect transistor in a front-end device layer, so that an orthographic projection of the N-type field effect transistor on a semiconductor substrate at least partially overlaps with an orthographic projection of the P-type field effect transistor on the semiconductor substrate.

[0039] Compared with the P-type field effect transistor and the N-type field effect transistor, the projected area of ​​the logic circuit on the semiconductor substrate can be reduced by half.

[0040] In one achievable manner, when a back-end device layer is formed on a front-end device layer using a back-end process, the method includes: forming a first N-type field effect transistor and a second N-type field effect transistor on the front-end device layer using a back-end process, and the first N-type field effect transistor and the second N-type field effect transistor are located in the same back-end device layer.

[0041] In one achievable manner, the first N-type field effect transistor and the second N-type field effect transistor are located in a first back-end device layer; after forming the front-end device layer and before forming the first back-end device layer, the preparation method further includes: forming a first interconnect routing layer so that at least one P-type field effect transistor is electrically connected to at least one N-type field effect transistor through the first interconnect routing layer.

[0042] That is, the P-type field effect transistor and the N-type field effect transistor in the logic circuit are electrically connected by using the interconnection wiring layer located in the front-end device layer and the back-end device layer.

[0043] In one possible implementation, manufacturing a storage array includes:

[0044] At least one P-type field effect transistor of a memory cell of a memory array is formed in the front-end device layer;

[0045] At least one N-type field effect transistor of a memory cell of a memory array is formed in the back-end device layer, and a channel material of the N-type field effect transistor includes an oxide semiconductor material.

[0046] When preparing a memory array using the method exemplified in the present application, the P-type field effect transistor in the memory cell is fabricated in a front-end device layer, and the N-type field effect transistor is fabricated in a back-end device layer. In this way, the projected area of ​​each memory cell on the semiconductor substrate can be compressed, thereby improving the storage capacity density of the memory array.

[0047] On the other hand, the present application also provides an electronic device, including a processor and the above-mentioned memory, wherein the processor is electrically connected to the memory, and the memory is used to store data generated by the processor.

[0048] The electronic device provided in the embodiment of the present application includes the memory in any of the above-mentioned implementation methods. Therefore, the electronic device provided in the embodiment of the present application and the memory of the above-mentioned technical solution can solve the same technical problems and achieve the same expected effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 A circuit diagram of an electronic device;

[0050] Figure 2 A circuit diagram of a memory;

[0051] Figure 3 A packaging structure diagram of a storage array and a controller;

[0052] Figure 4 A simple circuit diagram of a memory;

[0053] Figure 5 A simplified process structure diagram of a memory provided in an embodiment of the present application;

[0054] Figure 6 A circuit diagram of a logic circuit provided in an embodiment of the present application;

[0055] Figure 7 A process structure diagram of a memory provided in an embodiment of the present application;

[0056] Figure 8 A layout of a logic circuit provided in an embodiment of the present application;

[0057] Fig. 9 An existing layout of a logic circuit;

[0058] Fig.10 A circuit diagram of a logic circuit provided in an embodiment of the present application;

[0059] Fig.11 A layout of a logic circuit provided in an embodiment of the present application;

[0060] Fig.12 A circuit diagram of a 6T memory cell provided in an embodiment of the present application;

[0061] Fig.13 A circuit diagram of an 8T memory cell provided in an embodiment of the present application;

[0062] Fig.14A A layout of a front-end device layer of a memory array provided in an embodiment of the present application;

[0063] Fig. 14B and Fig. 14C A layout of a back-end device layer of a memory array provided in an embodiment of the present application;

[0064] Fig.15 A flowchart of a method for preparing a memory provided in an embodiment of the present application. DETAILED DESCRIPTION

[0065] Before introducing the embodiments provided in this application, the relevant technical terms are first introduced.

[0066] Pull-up means clamping the signal at a high level.

[0067] Pull-down means clamping the signal at a low level.

[0068] Oxide semiconductor: a type of oxide with semiconductor properties.

[0069] The following embodiments of the present application are described below in conjunction with the drawings in the embodiments of the present application.

[0070] The technical solution of the present application can be applied to various electronic devices using memory, such as: Figure 1 This is a circuit block diagram of an electronic device 100 provided in an embodiment of the present application. The electronic device 100 can be a terminal device, such as a mobile phone, a tablet computer, a smart bracelet, or a personal computer (PC), a server, a workstation, etc.

[0071] like Figure 1 , the electronic device 100 may include a bus 205, and a system on chip (SOC) 210 connected to the bus 205. The SOC 210 may be used to process data, such as processing application data, processing image data, and caching temporary data. In one embodiment, the SOC 210 may include an application processor (AP) 211 for processing applications, a graphics processing unit (GPU) 212 for processing image data, and a first random access memory (RAM) 213 for caching high-speed data. The first RAM 213 may be a static random access memory (SRAM) or an embedded flash (EFlash), etc. The above-mentioned AP 211, GPU 212 and first RAM 213 may be integrated into a die, or may be separately set in multiple dies.

[0072] For example Figure 1 As shown, the electronic device 100 may further include a second RAM 220 connected to the SOC 210 via the bus 205. The second RAM 220 may be a dynamic random access memory (DRAM). The second RAM 220 may be used to store volatile data, such as temporary data generated by the SOC 210. The storage capacity of the second RAM 220 is generally greater than that of the first RAM 213, but the reading speed is generally slower than that of the first RAM 213.

[0073] In addition, the electronic device 100 may also include a communication chip 230 and a power management chip 240 connected to the SOC 210 via the bus 205. The communication chip 230 can be used for processing the protocol stack, or amplifying and filtering analog radio frequency signals, or realizing the above functions at the same time. The power management chip 240 can be used to power other chips. In one embodiment, the SOC 210 and the second RAM 220 can be packaged in a packaging structure, such as using 2.5D (dimension) or 3D packaging, etc., to obtain a faster data transmission rate between chips.

[0074] like Figure 2 As shown, the memory 300 includes a storage array 31 and a controller 32 for accessing the storage array 31 , wherein the controller 32 is used to control the read and write operations of the storage array 31 .

[0075] Figure 3 This is a structure of a storage array 31 and a controller 32 given in an embodiment of the present application. In this exemplary structure, the storage array 31 and the controller 32 are integrated into the same chip 3, and the chip 3 is integrated on a substrate 33. Therefore, the storage array 31 can be called an embedded memory.

[0076] In one embodiment, the storage array 31 in the memory may include Figure 4 The memory cells 400 shown are arranged in a plurality of arrays, wherein each memory cell 400 can be used to store 1 bit (bit) or multiple bits of data. The memory array 31 can also include electrode lines such as word lines (WL) and bit lines (BL). Each memory cell 400 is electrically connected to the corresponding word line WL and bit line BL. Different memory cells 400 can be electrically connected through word lines WL and bit lines BL. One or more of the above-mentioned word lines WL and bit lines BL are used to select the memory cell 400 to be read or written in the memory array by receiving the control level output by the control circuit, thereby realizing the read and write operation of the data.

[0077] The controller 32 in the memory may include a plurality of logic circuits, for example, Figure 4 One or more logic circuit structures in the decoder 320, driver 330, timing controller 340, buffer 350 or input / output driver 360 are shown.

[0078] exist Figure 4In the memory 300 structure shown, the decoder 320 is used to decode according to the received address to determine the storage unit 400 that needs to be accessed. The driver 330 is used to control the level of the signal line according to the decoding result generated by the decoder 320, so as to achieve access to the specified storage unit 400. The buffer 350 is used to cache the read data, for example, it can be cached using a first-in first-out (FIFO). The timing controller 340 is used to control the timing of the buffer 350, and control the driver 330 to drive the signal lines in the storage array 310. The input and output driver 360 is used to drive the transmission signal, such as driving the received data signal and driving the data signal to be sent, so that the data signal can be transmitted over a long distance.

[0079] In some examples, the memory 300 may be electrically connected to the processor, and the memory is used to store data generated by the processor.

[0080] When the storage array 31 and the controller 32 are Figure 3 When the morphology shown is formed in a chip, Figure 5 As shown, a storage area and a logic area can be formed on a semiconductor substrate, a storage array 31 is integrated in the storage area, and a logic circuit for controlling the reading and writing of the storage array is integrated in the logic area.

[0081] The logic circuit includes, but is not limited to, inverters, AND gates, NOT gates, OR gates and various CMOS logic gates composed of them, transmission gates, tri-state gates, multi-way switches, as well as various timing circuits such as latches and triggers. The above various logic combinations are used in the peripheral circuits of the memory to realize all functions except the storage bit in the memory, such as command control, decoding, data selection, driving and signal amplification.

[0082] for example, Figure 6 1 is a circuit diagram of a NAND gate of the present application. The NAND gate circuit includes: a field effect transistor P1, a field effect transistor P2, a field effect transistor N1 and a field effect transistor N2. The field effect transistor P1 and the field effect transistor P2 are both P-type field effect transistors, and the field effect transistor N1 and the field effect transistor N2 are both N-type field effect transistors.

[0083] Some other logic circuits also include electrically connected P-type field effect transistors and N-type field effect transistors, such as inverters, latches, triggers, etc.

[0084] In some existing process steps, for example, the P-type field effect transistor and the N-type field effect transistor in the above logic circuit are both fabricated in the semiconductor substrate using the front of the line (FEOL) process. Figure 5The logic area including the logic circuit shown has a larger positive projection area on the semiconductor substrate, thereby reducing the effective area of ​​the storage array in the storage area, which will inhibit the improvement of storage density and storage capacity.

[0085] In order to increase the effective area of ​​the storage array, the embodiments of the present application provide some examples, by changing the process structure of the logic circuit in the logic area, compressing the effective area of ​​the logic circuit to leave more space for the storage area, thereby increasing the capacity of the storage array.

[0086] like Figure 7 In an embodiment of the present application, the memory includes a front-end device layer formed in a semiconductor substrate, and also includes a back-end device layer arranged above the front-end device layer.

[0087] At least one P-type field effect transistor in the logic circuit of the logic area of ​​the present application is formed in the front-end device layer. At least one N-type field effect transistor in the logic circuit is formed in the back-end device layer. For example, see Figure 6 In the exemplary NAND gate circuit, field effect transistors P1 and P2 are integrated in a front-end device layer using a front-end-of-line (FEOL) process, and field effect transistors N1 and N2 are integrated in a back-end-of-line (BEOL) device layer using a back-end-of-line (BEOL) process.

[0088] In the example of this application, the P-type field effect transistor is manufactured in the semiconductor substrate using the front-end process FEOL, and the N-type field effect transistor is manufactured using the back-end process. It can be understood that: Figure 7 In the chip manufacturing process, a front-end device layer can be first manufactured in a semiconductor substrate using a front-end process, and the source and drain of the P-type field effect transistor in the front-end device layer can be formed by doping in the semiconductor substrate; after the front-end device layer is manufactured, a back-end device layer can be manufactured using a back-end process.

[0089] like Figure 7 Since the N-type field effect transistor in the logic circuit of the present application is integrated in the back-end device layer, and the P-type field effect transistor is integrated in the front-end device layer, that is, the N-type field effect transistor and the P-type field effect transistor are integrated on the semiconductor substrate in a three-dimensional stacking manner, rather than being formed in the semiconductor substrate in the existing two-dimensional integration method, the three-dimensional stacking method can reduce the projection area of ​​the logic circuit on the semiconductor substrate, for example, Figure 6 The logic circuit shown can reduce the projected area to half of the existing integration method, so that the projected area occupied by the storage area can be increased, and the storage capacity density of the memory can be improved.

[0090] The channel material of the N-type field effect transistor in the back-end device layer of the present application example includes an oxide semiconductor material, which may include at least one of ZnO, CdO, TiO2, Al2O3, and SnO. Alternatively, in some other examples, the channel material of the N-type field effect transistor may include polysilicon.

[0091] The field-effect transistor (OS-FET) process based on oxide semiconductor as the channel material is compatible with the back-end process, that is, the active device N-type field-effect transistor can be placed in the back-end device layer without complicating the process.

[0092] like Figure 7 , the back-end device layer is used to integrate electronic devices, such as active devices or passive devices, such as Figure 6 The N-type field effect transistor of the example can be integrated in the back-end device layer. In addition, the interconnection wiring layer can also be made by back-end process, for example, Figure 7 An interconnection routing layer can be formed between the front-end device layer and the back-end device layer, and the interconnection routing layer can be used to electrically connect different devices in the front-end device layer, or the interconnection routing layer can be used to interconnect the electronic devices in the front-end device layer and the electronic devices in the back-end device layer.

[0093] An interconnection wiring layer may also be formed between two adjacent back-end device layers to electrically connect the electronic devices in the two adjacent back-end device layers.

[0094] See Figure 6 An exemplary NAND gate circuit includes a field effect transistor P1 and a field effect transistor P2 connected in parallel, and a field effect transistor N1 and a field effect transistor N2 connected in series.

[0095] Field effect transistor P1 and field effect transistor P2 are coupled in parallel between the first voltage terminal and the output terminal; field effect transistor N1 and field effect transistor N2 are coupled in series between the second voltage terminal and the output terminal; the gate of field effect transistor P1 and the gate of field effect transistor N1 are electrically connected to the first input terminal respectively; the gate of field effect transistor P2 and the gate of field effect transistor N2 are electrically connected to the second input terminal respectively.

[0096] The gate of the field effect transistor P1 is electrically connected to the gate of the field effect transistor N1 and serves as an input terminal InputB of the NAND gate circuit.

[0097] The gate of the field effect transistor P2 is electrically connected to the gate of the field effect transistor N2 and serves as an input terminal InputA of the NAND gate circuit.

[0098] The first electrode of the field effect transistor P1 is electrically connected to the first electrode of the field effect transistor P2. For example, the electrical connection point between the first electrode of the field effect transistor P1 and the first electrode of the field effect transistor P2 may be electrically connected to VDD.

[0099] The second electrode of the field effect transistor P1 is electrically connected to the second electrode of the field effect transistor P2. For example, the second electrode of the field effect transistor P1 is electrically connected to the second electrode of the field effect transistor P2 to be electrically connected to the output terminal Output.

[0100] The first electrode of the field effect transistor N2 is electrically connected to the first electrode of the field effect transistor N1 .

[0101] A second electrode of the field effect transistor N2 is electrically connected to a second electrode of the field effect transistor P2.

[0102] A second electrode of the field effect transistor N1 may be electrically connected to VSS.

[0103] The first electrode of the field effect transistor involved in the example of the present application refers to one of the source and the drain, and the second electrode of the field effect transistor refers to the other of the source and the drain.

[0104] Figure 8 An example is given Figure 6 A layout of a NAND gate circuit is shown. It includes a front-end device layer, a first interconnection routing layer, a first back-end device layer, a second interconnection routing layer and a third interconnection routing layer formed in a semiconductor substrate. The first interconnection routing layer, the first back-end device layer, the second interconnection routing layer and the third interconnection routing layer are stacked in sequence along a direction perpendicular to the surface of the semiconductor substrate.

[0105] The field effect transistor P1 and the field effect transistor P2 are located in the front-end device layer. The source and drain of the field effect transistor P1 and the field effect transistor P2 can be made by a doping process to form corresponding Figure 8 The PMOS active area is shown.

[0106] exist Figure 8 In the figure, a first PMOS gate of the field effect transistor P1 and a second PMOS gate of the field effect transistor P2 are exemplarily shown.

[0107] The field effect transistor N1 and the field effect transistor N2 are located in the first back-end device layer. The source and drain of the field effect transistor P1 and the field effect transistor P2 can be made by a deposition process, and the channel of the field effect transistor N1 and the field effect transistor N2 can be made of an oxide semiconductor material to form Figure 8 The NMOS active region is shown.

[0108] In the example of the present application, the field effect transistor N1 and the field effect transistor N2 may be a ring gate structure; or, may adopt a ring channel structure; or, may also be other structures.

[0109] In the first back-end device layer, a Figure 8 The first NMOS gate of the field effect transistor N1 and the second NMOS gate of the field effect transistor N2.

[0110] A first interconnection wiring layer disposed between the front-end device layer and the first back-end device layer has a plurality of metal wirings. The plurality of metal wirings, contact holes electrically connected to the PMOS active region, contact holes electrically connected to the first PMOS gate and the second PMOS gate, contact holes electrically connected to the NMOS active region, contact holes electrically connected to the first NMOS gate and the second NMOS gate, and silicon through-holes Via penetrating the dielectric layer are used to connect the field effect transistors P1 and the field effect transistors P2, and the field effect transistors N1 and the field effect transistors N2 as follows: Figure 6 The electrical connections shown are interconnected.

[0111] See you next time Figure 8 A second interconnect routing layer and a third interconnect routing layer are stacked in sequence on one side of the first back-end device layer away from the first interconnect routing layer. The second interconnect routing layer and the second interconnect routing layer can be used to electrically connect the field effect transistor N1 and the field effect transistor N2, as well as the field effect transistor P1 and the field effect transistor P2 to the peripheral control circuit, for example, to the input terminal InputA, the input terminal InputB, the output terminal Output, and the power supply voltages VDD and VSS.

[0112] exist Figure 8 In the layout structure of the NOT gate circuit shown, the field effect transistor P1 and the field effect transistor P2 are arranged in the front-end device layer, and the field effect transistor N1 and the field effect transistor N2 are in the same back-end device layer. The field effect transistor N1 can be located above the field effect transistor P1, and the field effect transistor N2 can be located above the field effect transistor P2.

[0113] Alternatively, in some examples, the orthographic projection of the field effect transistor N1 on the semiconductor substrate overlaps at least partially with the orthographic projection of the field effect transistor P1 on the semiconductor substrate; the orthographic projection of the field effect transistor N2 on the semiconductor substrate overlaps at least partially with the orthographic projection of the field effect transistor P2 on the semiconductor substrate. In this way, the vertical projection area of ​​the NAND gate circuit on the semiconductor substrate can be compressed.

[0114] Fig. 9 In the prior art, Figure 6The layout is formed when the field effect transistor N1 and the field effect transistor N2, as well as the field effect transistor P1 and the field effect transistor P2 are all prepared by the front-end process.

[0115] exist Fig. 9 In the invention, a front-end device layer is formed in a semiconductor substrate, and a first interconnection routing layer and a second interconnection routing layer are sequentially stacked on the front-end device layer. The front-end device layer includes field effect transistors N1 and N2, and field effect transistors P1 and P2. The field effect transistors N1 and N2, and field effect transistors P1 and P2 can be electrically connected to a peripheral control circuit by using the stacked first interconnection routing layer and the second interconnection routing layer, for example, connected to an input terminal InputA, an input terminal InputB, an output terminal Output, and power supply voltages VDD and VSS.

[0116] Compared with the examples given in this application Figure 8 , and the prior art Fig. 9 , we can know that: Fig. 9 In the example, the area of ​​the logic circuit structure is the area of ​​two tracks. Figure 8 In the example, the area of ​​the logic circuit structure is the area of ​​one Track, compared to Fig. 9 , the area is reduced by half. In this way, more area can be saved for the storage array and the storage capacity can be increased.

[0117] Figure 8 Only Figure 6 The illustrated circuit is a layout structure of a NAND gate circuit, and in a selectable process structure, it may also be a layout design of other structures.

[0118] Fig.10 This is a circuit diagram of a D-Latch given in an embodiment of the present application. The circuit diagram is the main unit of the timing circuit and is widely used in digital integrated circuits. For example, the circuit includes 8 P-type field effect transistors and 8 N-type field effect transistors.

[0119] Fig.11 It shows Fig.10 A layout of a circuit diagram of a D-Latch is shown. It includes a front-end device layer, a first interconnect routing layer, a first back-end device layer, a second interconnect routing layer, and a third interconnect routing layer formed in a semiconductor substrate. The first interconnect routing layer, the first back-end device layer, the second interconnect routing layer, and the third interconnect routing layer are stacked in sequence along a direction perpendicular to the surface of the semiconductor substrate.

[0120] Fig.10The field effect transistors P1 to P8 are located in the front-end device layer, and the field effect transistors N1 to N8 are located in the first back-end device layer. The field effect transistors N1 to N8 and the field effect transistors P1 to P8 can be electrically connected to the peripheral control circuit by using the first interconnection wiring layer and the second interconnection wiring layer, for example, connected to the input terminal Input, the output terminal Output, and the power supply voltages VDD and VSS.

[0121] The field effect transistors P1 to P8 arranged in the front-end device layer can be interconnected with N1 to N8 in the first back-end device layer through the first interconnection wiring layer. For example, through contact holes, silicon through vias penetrating the dielectric layer, and metal wiring in the first interconnection wiring layer, the Fig.10 The D-Latch circuit is shown.

[0122] and the above Figure 8 Similar to the example shown, compared with integrating all P-type field effect transistors and N-type field effect transistors in the front-end device layer, the present application can compress the area occupied by the logic circuit by half, reduce the effective area occupied by the logic circuit, and increase the effective area of ​​the storage array.

[0123] like Fig.10 As shown, in the D-Latch circuit, the field effect transistor P1 and the field effect transistor N1 are coupled in series between VDD and VSS, the series coupling point is the node gn, and the gate of the field effect transistor P1 and the gate of the field effect transistor N1 are electrically connected to the enable terminal Enable of the circuit.

[0124] The field effect transistor P2 and the field effect transistor N2 are coupled in series between VDD and VSS, with the series coupling point being a node g, and the gate of the field effect transistor P1 and the gate of the field effect transistor N1 are coupled as a node gn.

[0125] See you next time Fig.10 , field effect transistors P3, P4, N3 and N4 are coupled in series between VDD and VSS, the gate of field effect transistor P3 is electrically connected to node g, and the gate of field effect transistor N3 is electrically connected to node gn.

[0126] Field effect transistor P5, field effect transistor P6, field effect transistor N5 and field effect transistor N6 are coupled in series between VDD and VSS, the gate of field effect transistor P6 is electrically connected to node gn, the gate of field effect transistor N5 is electrically connected to node g, and the gate of field effect transistor P5 and the gate of field effect transistor N6 are electrically connected to the input terminal Input of the circuit.

[0127] Field effect transistor P7 and field effect transistor N7 are coupled in series between VDD and VSS.

[0128] The field effect transistor P8 and the field effect transistor N8 are coupled in series between VDD and VSS, and the series coupling point is electrically connected to the output terminal Output of the circuit.

[0129] The gate of the field effect transistor P7 and the gate of the field effect transistor N7 are electrically connected to the series coupling point of the field effect transistor P6 and the field effect transistor N5, respectively.

[0130] The gate of the field effect transistor P8 and the gate of the field effect transistor N8 are electrically connected to the series coupling point of the field effect transistor P6 and the field effect transistor N5, respectively.

[0131] A series coupling point between the field effect transistor P6 and the field effect transistor N5 is electrically connected to a series coupling point between the field effect transistor P4 and the field effect transistor N3 .

[0132] The gate of the field effect transistor P4 and the gate of the field effect transistor N4 are electrically connected to the series coupling point of the field effect transistor P7 and the field effect transistor N7, respectively.

[0133] In the above example, the effective area of ​​the memory array is increased by compressing the effective area of ​​the logic circuit located in the logic area. In addition, the present application also provides some process structures that can improve the storage density and capacity, as shown below.

[0134] The storage array in the example of the present application may be an SRAM storage array, a DRAM storage array, a FLASH storage array, a NAND storage array or an eDRAM storage array, etc.

[0135] Some memory cells of memory arrays include N-type field effect transistors and P-type field effect transistors, such as SRAM memory cells.

[0136] like Fig.12 and Fig.13 , Fig.12 The figure shows a 6T SRAM memory cell. Fig.13 An 8T SRAM memory cell is shown.

[0137] like Fig.12 The exemplary 6T memory cell 400 includes field effect transistors MP1, MN1, MP2, MN2, MA1 and MA2. Field effect transistors MP1 and MP2 are P-type field effect transistors, and the rest are N-type field effect transistors.

[0138] For example, Fig.13The exemplary 8T memory cell 400 includes field effect transistors MP1, FET MN1, FET MP2, FET MN2, FET MA1 and FET MA2, and field effect transistors MR1 ​​and FET MR2. Field effect transistors MP1 and MP2 are P-type field effect transistors, and the rest are N-type field effect transistors.

[0139] In some examples given in this application, Fig.12 and Fig.13 , P-type field effect transistors are manufactured in the front-end device layer in the semiconductor substrate using the front-end process FEOL. For example, Fig.12 and Fig.13 The field effect transistors MP1 and MP2 are manufactured in the front-end device layer by using the front-end process FEOL, and the remaining N-type field effect transistors are manufactured in the back-end device layer by using the back-end process BEOL. The channel material of the N-type field effect transistors includes an oxide semiconductor material.

[0140] like Fig.12 and Fig.13 , multiple field effect transistors in a storage unit are formed in a three-dimensional stacking manner to form a three-dimensional stacked storage array. Compared with all field effect transistors in a storage unit being manufactured using a front-end process, this application can significantly improve the storage density.

[0141] In the example of this application, the P-type field effect transistor that can be used as a pull-up tube is manufactured using a front-end process, and the N-type field effect transistor that can be used as a pull-down tube is manufactured using a back-end process. Compared with the existing method in which both the P-type field effect transistor and the N-type field effect transistor are manufactured using the front-end process, when the same process node is used, this application can not only ensure the high conduction performance of the pull-down tube, but also improve the storage density.

[0142] This application takes a 6T memory cell as an example to introduce a process structure that can be implemented in the memory cell.

[0143] like Fig.12 A 6T memory cell includes a first inverter 501 and a second inverter 502, wherein the input end of the first inverter 501 is electrically connected to the output end of the second inverter 502, and the output end of the first inverter 501 is electrically connected to the input end of the second inverter 502, and the first inverter 501 and the second inverter 502 form a cross-coupled circuit structure.

[0144] The first inverter 501 includes a field effect transistor MP1 and a field effect transistor MN1 which are electrically connected, and the second inverter 502 includes a field effect transistor MP2 and a field effect transistor MN2 which are electrically connected.

[0145] The field effect transistor MP1 and the field effect transistor MP2 are respectively arranged in the semiconductor substrate by the front-end process and are located in the front-end device layer of the semiconductor substrate; the field effect transistor MN1 and the field effect transistor MN2 are respectively manufactured in the back-end device layer above the semiconductor substrate by the back-end process.

[0146] In order to further improve the storage density, such as Fig.12 , the field effect transistor MP1 and the field effect transistor MP2 are located in the front-end device layer, and the field effect transistor MN1 and the field effect transistor MN2 can be arranged in the same back-end device layer, for example, Fig.12 The OSL1 device layer is shown.

[0147] In some achievable process structures, in the first inverter 501, the field effect transistor MN1 is formed on the side of the field effect transistor MP1 away from the semiconductor substrate using a back-end process. In some examples, the orthographic projections of the field effect transistor MN1 and the field effect transistor MP1 on the semiconductor substrate partially overlap. In the second inverter 502, the field effect transistor MN2 is formed on the side of the field effect transistor MP2 away from the semiconductor substrate using a back-end process. In some examples, the orthographic projections of the field effect transistor MN2 and the field effect transistor MP2 on the semiconductor substrate partially overlap. In this way, the orthographic projection area of ​​each storage unit on the semiconductor substrate can be further compressed, further improving the storage density.

[0148] See also Fig.12 The gate of the field effect transistor MP1 is electrically connected to the first electrode of the field effect transistor MP2, the gate of the field effect transistor MP2 is electrically connected to the first electrode of the field effect transistor MP1, and the second electrode of the field effect transistor MP1 is electrically connected to the second electrode of the field effect transistor MP2. For example, the second electrode of the field effect transistor MP1 and the second electrode of the field effect transistor MP2 can both be electrically connected to VDD.

[0149] The gate of field effect transistor MN1 is electrically connected to the first electrode of field effect transistor MN2, the gate of field effect transistor MN2 is electrically connected to the first electrode of field effect transistor MN1, and the second electrode of field effect transistor MN1 is electrically connected to the second electrode of field effect transistor MN2. For example, the second electrode of field effect transistor MN1 and the second electrode of field effect transistor MN2 can both be electrically connected to VSS.

[0150] The first electrode of the field effect transistor MP1 is electrically connected to the first electrode of the field effect transistor MN1, and the electrical connection node forms the output terminal of the first inverter 501; the gate of the field effect transistor MP1 is electrically connected to the gate of the field effect transistor MN1, and the electrical connection node forms the input terminal of the first inverter 501.

[0151] The first electrode of the field effect transistor MP2 is electrically connected to the first electrode of the field effect transistor MN2, and the electrical connection node forms the output terminal of the second inverter 502; the gate of the field effect transistor MP2 is electrically connected to the gate of the field effect transistor MN2, and the electrical connection node forms the input terminal of the second inverter 502.

[0152] In the example of the present application, the first electrode is one of the source electrode and the drain electrode, and the second electrode is the other of the source electrode and the drain electrode.

[0153] In conjunction with the process structure diagram, the process structures that can be implemented by each field effect transistor in the first inverter 501 and the second inverter 502 and the process connection structures between different electrodes are described in detail below.

[0154] Fig.14A , Fig. 14B and Fig. 14C This is the layout structure of each device layer given in the embodiments of the present application.

[0155] The storage array comprises a stacked front-end device layer, an interconnection wiring layer, a back-end device layer, an interconnection wiring layer, a back-end device layer and an interconnection wiring layer.

[0156] like Fig.14A The field effect transistor MP1 and the field effect transistor MP2 are arranged along a first direction (eg, X direction) parallel to a surface of a semiconductor substrate (not shown in the figure).

[0157] In the first inverter 501, as Fig.14A The first electrode 11A and the second electrode 12A of the field effect transistor MP1 are arranged along a second direction (such as the Y direction) parallel to the surface of the semiconductor substrate, and a channel of the field effect transistor MP1 is formed between the first electrode 11A and the second electrode 12A. The gate 13A of the field effect transistor MP1 is arranged above the channel and can be isolated from the channel by a gate dielectric layer.

[0158] In the second inverter 502, as Fig.14A The first electrode 11B and the second electrode 12B of the field effect transistor MP2 are arranged along the second direction, and a channel of the field effect transistor MP2 is formed between the first electrode 11B and the second electrode 12B. The gate 13B of the field effect transistor MP2 is arranged above the channel and can be isolated from the channel by a gate dielectric layer.

[0159] The source, drain and channel of the field effect transistor MP1 are in the front-end device layer, and the source, drain and channel of the field effect transistor MP2 are also in the front-end device layer. In some examples, the source and drain of the field effect transistor MP1 and the field effect transistor MP2 can be made by ion implantation.

[0160] Since the field effect transistor MP1 and the field effect transistor MP2 need to be electrically connected, in some process structures, an interconnection wiring layer 1 may be provided above the front-end device layer of the semiconductor substrate. Fig.14A The gate 13A of the field effect transistor MP1 is electrically connected to the first electrode 11B of the field effect transistor MP2 through the metal wiring 1, the gate 13B of the field effect transistor MP2 is electrically connected to the first electrode 11A of the field effect transistor MP1 through the metal wiring 2, and the second electrode 12A of the field effect transistor MP1 is electrically connected to the second electrode 12B of the field effect transistor MP2 through the metal wiring 3. The metal wiring 1, the metal wiring 2 and the metal wiring 3 are part of the wiring in the interconnect wiring layer 1.

[0161] There is a dielectric layer between the front-end device layer and the interconnect wiring layer 1. The metal wiring can be electrically connected to the corresponding structure through a conductive via (e.g., silicon through via) that penetrates the dielectric layer. For example, the gate 13A of the field effect transistor MP1 can be connected to the metal wiring 1 through the conductive via 11.

[0162] In the front-end device layer, a plurality of field effect transistors MP1 and field effect transistors MP2 are integrated. These field effect transistors MP1 and field effect transistors MP2 are arranged in an array. In order to electrically connect the second electrode of the field effect transistor MP1 and the second electrode of the field effect transistor MP2 in the same direction, as shown in FIG. Fig.14A The metal wiring 3 can be extended along the X direction to electrically connect the second electrodes of the plurality of field effect transistors MP1 and the second electrodes of the plurality of field effect transistors MP2 in the X direction. For example, the metal wiring 3 can be electrically connected to VDD.

[0163] The field effect transistor MN1 of the first inverter 501 and the field effect transistor MN2 of the second inverter 502 are both arranged in the back-end device layer 1. Fig. 14B , the field effect transistor MN1 and the field effect transistor MN2 are arranged along the X direction.

[0164] like Fig. 14B In the first inverter 501, the first electrode 11C and the second electrode 12C of the field effect transistor MN1 are arranged along the Y direction. In the example of the present application, the field effect transistor MN1 is a ring gate structure. In other examples, a ring channel structure may also be used.

[0165] like Fig. 14B In the second inverter 502, the first electrode 11D and the second electrode 12D of the field effect transistor MN2 are also arranged in the Y direction. The field effect transistor MN2 is similar to the field effect transistor MN1 in the example, both of which have a ring gate structure. Other structures may also be used.

[0166] The orthographic projection of the field effect transistor MN1 on the semiconductor substrate at least partially overlaps with the orthographic projection of the field effect transistor MP1 on the semiconductor substrate; that is, the field effect transistor MN1 is located above the vertical projection of the field effect transistor MP1. The orthographic projection of the field effect transistor MN2 on the semiconductor substrate at least partially overlaps with the orthographic projection of the field effect transistor MP2 on the semiconductor substrate, and the field effect transistor MN2 is located above the vertical projection of the field effect transistor MP2. In this way, the orthographic projection area of ​​the first inverter and the second inverter in the storage unit on the semiconductor substrate can be reduced by half compared with the prior art, thereby improving the storage density and storage capacity.

[0167] like Fig. 14B An interconnection wiring layer 2 is provided above the back-end device layer 1 , and the field effect transistor MN1 can be electrically connected to the field effect transistor MN2 through the interconnection wiring layer 2 .

[0168] For example, the gate 13C of the field effect transistor MN1 is electrically connected to the first electrode 11D of the field effect transistor MN2 through the metal wiring 4, the gate 13D of the field effect transistor MN2 is electrically connected to the first electrode 11C of the field effect transistor MN1 through the metal wiring 5, and the second electrode 12C of the field effect transistor MN1 is electrically connected to the second electrode 12D of the field effect transistor MN2 through the metal wiring 6. The metal wiring 4, the metal wiring 5 and the metal wiring 6 are part of the wiring in the second interconnect wiring layer.

[0169] There is a dielectric layer between the back-end device layer 1 and the interconnection wiring layer 2, and the metal wiring in the interconnection wiring layer 2 can be electrically connected to the corresponding structure in the back-end device layer 1 through the conductive through-holes penetrating the dielectric layer.

[0170] The field effect transistor MP1 located in the front-end device layer needs to be electrically connected to the field effect transistor MN1 located in the back-end device layer. The field effect transistor MP2 located in the front-end device layer needs to be electrically connected to the field effect transistor MN2 located in the back-end device layer.

[0171] The first electrode 11A of the field effect transistor MP1 is electrically connected to the first electrode 11C of the field effect transistor MN1. In some examples, the first electrode 11A and the first electrode 11C may be interconnected via a conductive through hole penetrating through the dielectric layer.

[0172] The first electrode 11B of the field effect transistor MP2 is electrically connected to the first electrode 11D of the field effect transistor MN2. In some structures, the first electrode 11B and the first electrode 11D may be interconnected via a conductive through hole 13 penetrating through the dielectric layer.

[0173] In some other process structures, the first electrode 11A is interconnected with the first electrode 11C, and the first electrode 11B is interconnected with the first electrode 11D. Other wiring methods may also be used.

[0174] like Fig.12 The exemplary 6T memory cell further includes a field effect transistor MA1 and a field effect transistor MA2. The field effect transistor MA1 and the field effect transistor MA2 may be N-type field effect transistors, which may be manufactured using a back-end process. For example, the channel material of the field effect transistor MA1 and the field effect transistor MA2 includes an oxide semiconductor material.

[0175] In some examples, the field effect transistor MA1 and the field effect transistor MA2 may be formed in the same back-end device layer using a back-end process, for example. Fig.12 The example is located in the OSL2 device layer.

[0176] The field effect transistor MA2 is electrically connected to the output terminal of the first inverter 501 , and the field effect transistor MA1 is electrically connected to the output terminal of the second inverter 502 .

[0177] The field effect transistor MA1 and the field effect transistor MA2 are disposed in the back-end device layer 2 .

[0178] like Fig. 14C , the field effect transistor MA1 and the field effect transistor MA2 are arranged along the X direction.

[0179] like Fig. 14C The first electrode 11E and the second electrode 12E of the field effect transistor MA1 are arranged along the Y direction. In the example of the present application, the field effect transistor MA1 is a ring gate structure. In other examples, a ring channel structure may also be used.

[0180] like Fig. 14C The first electrode 11F and the second electrode 12F of the field effect transistor MA2 are also arranged in the Y direction. The field effect transistor MA2 is similar to the field effect transistor MA1 in the example, both of which have a ring gate structure. Other structures may also be used.

[0181] like Fig. 14C , the gate 13E of the field effect transistor MA1 and the gate 13F of the field effect transistor MA2 are electrically connected.

[0182] For example, the first electrode of the field effect transistor MA2 is electrically connected to the gate of the field effect transistor MN1, or the first electrode of the field effect transistor MA2 is electrically connected to the first electrode of the field effect transistor MN2.

[0183] The first electrode of the field effect transistor MA1 is electrically connected to the gate of the field effect transistor MN2 , or the first electrode of the field effect transistor MA1 is electrically connected to the first electrode of the field effect transistor MN1 .

[0184] The 6T memory cell of the example of the present application distributes the six field effect transistors in one memory cell in three device layers, wherein two P-type field effect transistors are arranged in the front-end device layer, and the other four N-type field effect transistors are arranged in two back-end device layers, so that three-dimensionally stacked three-layer device layers can produce one memory cell, and the metal interconnection layer arranged between two adjacent device layers is used to realize the interconnection of different field effect transistors.

[0185] like Fig.12 The exemplary 6T memory cell also includes electrode lines for controlling the reading and writing of the memory cell, for example, including a word line WL, a first bit line BL, and a second bit line BLB. Among them, the second electrode of the field effect transistor MA1 is electrically connected to the first bit line BL, the second electrode of the field effect transistor MA2 is electrically connected to the second bit line BLB, and the gate of the field effect transistor MA1 and the gate of the field effect transistor MA2 are both electrically connected to the word line WL.

[0186] In the achievable process structure, an interconnection routing layer 3 is provided above the back-end device layer 2 where the field effect transistors MA1 and MA2 are located, the first bit line BL and the second bit line BLB are located in the interconnection routing layer 3 , and the word line WL is located in the back-end device layer 2 .

[0187] In some examples given in the present application, the first bit line BL and the second bit line BLB may be parallel to each other, and the word line WL may be perpendicular to both the first bit line BL and the second bit line BLB.

[0188] In a memory chip, not only a memory array but also a logic circuit is included, and when the memory cells and logic circuits of the memory array both contain P-type field effect transistors and N-type field effect transistors, the P-type field effect transistors in the memory cells and the P-type field effect transistors in the logic circuits are both integrated in a front-end device layer, and at least part of the N-type field effect transistors in the memory cells and at least part of the N-type field effect transistors in the logic circuits are located in the same back-end device layer.

[0189] for example, Figure 6 The field effect transistor N2 and field effect transistor N1 in the Fig.12 The field effect transistor MN1 and the field effect transistor MN2 in the embodiment may be integrated in the same back-end device layer. For example, they are integrated in a first back-end device layer above the front-end device layer.

[0190] In other examples, Figure 6The back-end device layer where the field effect transistor N2 and the field effect transistor N1 are located can be Fig.12 The back-end device layer where the field effect transistor MN1 and the field effect transistor MN2 are located do not belong to the same back-end device layer.

[0191] The present application also provides a method for preparing a memory device, such as Fig.15 , Fig.15 The flowchart of the method for preparing the memory is shown as an example, and the method for preparing the memory includes:

[0192] Step S1: Prepare a storage array.

[0193] Step S2: Produce a logic circuit, which is used for reading and writing operations on the storage array.

[0194] The manufacturing of the memory array in step S1 and the manufacturing of the logic circuit in step S2 do not constitute an absolute limitation on the specific process steps. In some optional process steps, the memory array and the logic circuit can be manufactured first, or the logic circuit can be manufactured first and then the memory array.

[0195] Wherein, the obtained logic circuit comprises:

[0196] A front-end device layer is formed in a semiconductor substrate by adopting a front-end process, and at least one P-type field effect transistor in a logic circuit is formed in the front-end device layer.

[0197] A back-end device layer is formed on the front-end device layer by adopting a back-end process, and at least one N-type field effect transistor in a logic circuit is formed in the back-end device layer.

[0198] In the logic circuit manufactured by the preparation method provided in the present application, the P-type field effect transistor is manufactured in the front-end device layer, and the N-type field effect transistor is manufactured in the back-end device layer. That is, the multiple field effect transistors of the logic circuit are integrated on the semiconductor substrate in a three-dimensional stacking manner, thereby reducing the vertical projection area of ​​the logic circuit on the semiconductor substrate and leaving more setting space for the storage array, thereby improving the storage density.

[0199] In the back-end device layer, when an N-type field effect transistor is manufactured, the N-type field effect transistor can be directly above the P-type field effect transistor in the front-end device layer. It can be understood that the orthographic projection of the N-type field effect transistor on the semiconductor substrate at least partially overlaps with the orthographic projection of the P-type field effect transistor on the semiconductor substrate, so as to further reduce the vertical projection area of ​​the logic circuit.

[0200] In some process steps, the number of P-type field effect transistors in a front-end device layer can be the same as the number of N-type field effect transistors in a back-end device layer. For example, if the six P-type field effect transistors in the logic circuit are located in the front-end device layer, then the six N-type field effect transistors in the logic circuit can be arranged in the same back-end device layer and correspond one-to-one to the positions of the six P-type field effect transistors in the front-end device layer.

[0201] In order to realize interconnection between P-type field effect transistors, or interconnection between a P-type field effect transistor and an N-type field effect transistor, an interconnection routing layer may be provided between a front-end device layer and a back-end device layer, or between adjacent back-end device layers.

[0202] In addition, when manufacturing a memory array, the P-type field effect transistors in the memory array can be arranged in the front-end device layer, and the N-type field effect transistors can be arranged in the back-end device layer. In this way, the storage density and storage capacity can be further improved.

[0203] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0204] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A memory, characterized in that: include: Semiconductor substrate; A front-end device layer and a back-end device layer, wherein the front-end device layer is arranged in the semiconductor substrate, and the back-end device layer is arranged above the front-end device layer; The memory also includes a storage array and a logic circuit, wherein the logic circuit is used for reading and writing operations on the storage array; The logic circuit includes: at least one P-type field effect transistor and at least one N-type field effect transistor; The at least one P-type field effect transistor is formed in the front-end device layer; The at least one N-type field effect transistor is formed in the back-end device layer.

2. The memory according to claim 1, characterized in that: The orthographic projection of the N-type field effect transistor on the semiconductor substrate at least partially overlaps with the orthographic projection of the P-type field effect transistor on the semiconductor substrate.

3. The memory according to claim 1 or 2, characterized in that: The at least one N-type field effect transistor is located in a first back-end device layer in the same back-end device layer; A first interconnection wiring layer is formed between the front-end device layer and the first back-end device layer; The at least one P-type field effect transistor is electrically connected to the at least one N-type field effect transistor through the first interconnect wiring layer.

4. The memory according to claim 3, characterized in that: A second interconnection wiring layer is formed on a side of the first back-end device layer facing away from the front-end device layer; The input terminal, the output terminal and the voltage control terminal of the logic circuit are electrically connected to the peripheral circuit through the second interconnection wiring layer.

5. The memory according to claim 3 or 4, characterized in that: The at least one P-type field effect transistor includes a first P-type field effect transistor and a second P-type field effect transistor; The at least one N-type field effect transistor includes a first N-type field effect transistor and a second N-type field effect transistor; The orthographic projection of the first N-type field effect transistor on the semiconductor substrate at least partially overlaps with the orthographic projection of the first P-type field effect transistor on the semiconductor substrate; An orthographic projection of the second N-type field effect transistor on the semiconductor substrate at least partially overlaps with an orthographic projection of the second P-type field effect transistor on the semiconductor substrate.

6. The memory according to claim 5, characterized in that: The first P-type field effect transistor and the second P-type field effect transistor are coupled in parallel between the first voltage terminal and the output terminal; The first N-type field effect transistor and the second N-type field effect transistor are coupled in series between the second voltage terminal and the output terminal; The gate of the first P-type field effect transistor and the gate of the first N-type field effect transistor are electrically connected to the first input terminal respectively; The gate of the second P-type field effect transistor and the gate of the second N-type field effect transistor are electrically connected to the second input terminal respectively.

7. The memory according to claim 5, characterized in that: The first P-type field effect transistor and the first N-type field effect transistor are coupled in series between a first voltage terminal and a second voltage terminal; The second P-type field effect transistor and the second N-type field effect transistor are coupled in series between the first voltage terminal and the second voltage terminal; A gate of the second P-type field effect transistor and a gate of the second N-type field effect transistor are electrically connected to a series coupling point of the first P-type field effect transistor and the first N-type field effect transistor, respectively.

8. The memory according to any one of claims 1 to 7, characterized in that: The logic circuit includes at least one of a control circuit, a decoding circuit, a data selection circuit, a driving circuit, and a sensitive amplifier circuit.

9. The memory according to any one of claims 1 to 8, characterized in that: The memory array includes a plurality of memory cells, each of which includes: a P-type field effect transistor and an N-type field effect transistor; The P-type field effect transistor in the memory cell is formed in the front-end device layer; The N-type field effect transistor in the memory cell is formed in the back-end device layer.

10. The memory according to claim 9, characterized in that: At least part of the N-type field effect transistors in the memory cell and at least part of the N-type field effect transistors in the logic circuit are located in the same back-end device layer.

11. The memory according to claim 9 or 10, characterized in that: An orthographic projection of the N-type field effect transistor in the memory cell on the semiconductor substrate at least partially overlaps with an orthographic projection of the P-type field effect transistor in the memory cell on the semiconductor substrate.

12. The memory according to any one of claims 1 to 11, characterized in that: A channel material of the at least one N-type field effect transistor includes an oxide semiconductor material.

13. A method for preparing a memory, characterized in that: The preparation method comprises: Producing a storage array; Producing a logic circuit, wherein the logic circuit is used for reading and writing operations on the storage array; The obtained logic circuit comprises: Forming a front-end device layer in a semiconductor substrate by a front-end process, wherein at least one P-type field effect transistor in the logic circuit is formed in the front-end device layer; A back-end device layer is formed on the front-end device layer by a back-end process, and at least one N-type field effect transistor in the logic circuit is formed in the back-end device layer.

14. The method for preparing a memory according to claim 13, characterized in that: When the N-type field effect transistor is manufactured by adopting the back-end process, it includes: The N-type field effect transistor is manufactured above the P-type field effect transistor in the front-end device layer, so that the orthographic projection of the N-type field effect transistor on the semiconductor substrate at least partially overlaps with the orthographic projection of the P-type field effect transistor on the semiconductor substrate.

15. The method for preparing a memory according to claim 13 or 14, characterized in that: When the back-end process is used to form the back-end device layer on the front-end device layer, the method includes: A first N-type field effect transistor and a second N-type field effect transistor are formed on the front-end device layer by using a back-end process, and the first N-type field effect transistor and the second N-type field effect transistor are located in the same back-end device layer.

16. The method for preparing a memory according to claim 15, characterized in that: The first N-type field effect transistor and the second N-type field effect transistor are located in a first back-end device layer; After forming the front-end device layer and before forming the first back-end device layer, the preparation method further includes: A first interconnection wiring layer is formed so that the at least one P-type field effect transistor is electrically connected to the at least one N-type field effect transistor through the first interconnection wiring layer.

17. The method for preparing a memory according to any one of claims 13 to 16, characterized in that: The prepared storage array comprises: At least one P-type field effect transistor of a memory cell of the memory array is formed in the front-end device layer; At least one N-type field effect transistor of a memory cell of the memory array is formed in the back-end interconnect layer, and a channel material of the N-type field effect transistor includes an oxide semiconductor material.

18. An electronic device, characterized in that: include: processor; The memory according to any one of claims 1 to 12, or the memory made by the method for making the memory according to any one of claims 13 to 17; The processor is electrically connected to the memory, and the memory is used to store data generated by the processor.

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