Transverse MOS device and preparation method thereof

Abstract

The invention provides a transverse MOS (Metal Oxide Semiconductor) device and a preparation method thereof. A buried oxide layer and a P-type drift region are grown on the upper surface of a P-type substrate in an upward variable doping epitaxial manner in sequence; the bottom of the gate is connected with the upper surface of the buried oxide layer; a dielectric layer is filled in the trench structure on the P-type drift region; the gate electrode is arranged on one side of the dielectric layer, a first P + region is arranged on the other side of the dielectric layer, the upper surface of the gate electrode and the upper surface of the first P + region are flush with the upper surface of the dielectric layer, and the drain electrode is arranged on the upper portion of the first P + region; an N-type well region is arranged between the dielectric layer and the gate electrode; the upper part of the N-type well region is provided with a second P + region and an N + region, the second P + region and the N + region are both located between the gate electrode and the dielectric layer, and the second P + region is located between the N + region and the gate electrode; the source electrode is arranged at the upper part of the N + region; the problem that the transverse electric field is low due to the fact that the surface of a traditional LDMOS high-voltage device depends on a silicon layer for voltage withstanding is solved, and the voltage withstanding capacity of the device in the transverse unit length is enhanced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device manufacturing, and in particular to a lateral MOS device and a preparation method thereof. Background Art

[0002] In recent years, semiconductor devices have been widely used in integrated circuits such as gate drive circuits, high-voltage switch control circuits and radio frequency circuits, and have considerable application prospects in various industries. Since the conductive channel of the lateral double-diffused metal oxide semiconductor (LDMOS) is lateral, and the source, gate and drain electrodes are all on the surface of the chip, it is convenient for internal connection and integration of low-voltage signals. The control circuit of LDMOS devices is simple, and it has great advantages in high frequency, gain and switching characteristics, and has become a hot topic of research in domestic and foreign academic circles.

[0003] Silicon On Insulator Lateral Double-diffused Metal Oxide Semiconductor (SOI LDMOS) is widely used in smart power integrated circuits (SPIC) due to its low power consumption, high frequency, high integration and other characteristics, such as automotive electronics, medical electronics, smart home appliances and aerospace. At present, most of the research on SOI MOSFET is focused on nLDMOS. As a high-side driver of the circuit, pLDMOS can simplify the complexity of power integrated circuits and reduce the chip area, which is also of great research significance. However, the majority hole mobility of pLDMOS is much lower than that of nLDMOS, making its conductivity only about 1 / 3 of that of nLDMOS. When SOI pLDMOS is applied to high-side circuits, it will be affected by the back gate bias, and its reduced surface electric field (RESURF) effect will be suppressed, making it difficult to achieve high withstand voltage. Summary of the invention

[0004] The present invention provides a lateral MOS device and a preparation method thereof, the purpose of which is to enhance the lateral pressure resistance per unit length of the device.

[0005] In order to achieve the above object, the present invention provides a lateral MOS device, comprising:

[0006] P-type substrate, gate, source, drain;

[0007] The upper surface of the P-type substrate is doped upwards in sequence and epitaxially grown with a buried oxide layer and a P-type drift region;

[0008] The bottom of the gate is connected to the upper surface of the buried oxide layer;

[0009] A trench structure is provided on the P-type drift region, and a dielectric layer is filled inside the trench structure;

[0010] The gate is arranged on one side of the dielectric layer, a first P+ region is arranged on the other side of the dielectric layer, the upper surface of the gate electrode and the upper surface of the first P+ region are both flush with the upper surface of the dielectric layer, and the drain is arranged on the upper part of the first P+ region;

[0011] An N-type well region is provided between the dielectric layer and the gate electrode;

[0012] A second P+ region and an N+ region are provided on the upper portion of the N-type well region, the second P+ region and the N+ region are both located between the gate electrode and the dielectric layer, the second P+ region is located between the N+ region and the gate electrode, and the upper surfaces of the second P+ region and the N+ region are both flush with the upper surface of the dielectric layer;

[0013] The source is disposed on the upper portion of the N+ region, and a portion of the source is located on the upper portion of the second P+ region.

[0014] Further, it also includes a gate oxide layer;

[0015] The gate oxide layer is arranged between the gate and the N-type well region;

[0016] The lower surface of the gate oxide layer is connected to the upper surface of the buried oxide layer, and the side wall of the gate oxide layer close to the N-type well region is connected to the side wall of the P-type drift region, the side wall of the N-type well region, and the side wall of the second P+ region from bottom to top;

[0017] The upper surface of the gate oxide layer is flush with the upper surface of the gate.

[0018] Specifically, the dielectric in the dielectric layer is silicon dioxide.

[0019] Furthermore, it also includes a back gate (3;

[0020] The back gate is arranged on the lower surface of the P-type substrate 1 .

[0021] The present invention also provides a method for preparing a lateral MOS device, which is used to prepare a lateral MOS device. The preparation method comprises:

[0022] Step 1, preparing a P-type substrate;

[0023] Step 2, growing a gradually doped drift region upward in sequence on a P-type substrate by adopting a variable doping epitaxial method of multiple growths to form a buried oxide layer and a P-type drift region;

[0024] Step 3, etching the P-type drift region to form a trench structure, and filling the trench structure with a dielectric layer;

[0025] Step 4, coating a photoresist on the upper surface of the dielectric layer and the P-type drift region, and injecting ions on one side of the dielectric layer through the photoresist to form a P-type well region;

[0026] Step 5, etching the edge of the P-type well region away from the dielectric layer to form a silicon groove, and forming a gate in the silicon groove;

[0027] Step 6, performing ion implantation and annealing processes on the upper surfaces of the P-type well region and the P-type drift region to form a second P+ region and an N+ region;

[0028] Step 7, respectively etching contact hole regions on the upper surface of the N+ region and the upper surface of the first P+ region and growing aluminum electrodes to form a source and a drain.

[0029] Furthermore, step 5 also includes:

[0030] A gate oxide layer is grown in the silicon trench, and the gate oxide layer is located between the gate and the N-type well region.

[0031] Furthermore, before coating the photoresist on the upper surface of the dielectric layer and the P-type drift region, the process further includes:

[0032] The dielectric layer is planarized by chemical mechanical polishing, so that the upper surface of the dielectric layer is flush with the upper surface of the P-type drift region.

[0033] Furthermore, the medium filled in the dielectric layer is silicon dioxide.

[0034] Furthermore, after step 7, the following steps are also included:

[0035] A back gate is grown on the lower surface of the P-type substrate.

[0036] Furthermore, the material used for the gate is polysilicon.

[0037] The above scheme of the present invention has the following beneficial effects:

[0038] The lateral MOS device provided by the present invention comprises a P-type substrate, a gate, a source and a drain; a buried oxide layer and a P-type drift region are sequentially grown on the upper surface of the P-type substrate by doping and epitaxial growth, so as to reduce leakage and lower the conduction voltage drop; the bottom of the gate is connected to the upper surface of the buried oxide layer; a groove structure is arranged on the P-type drift region, and a dielectric layer is filled inside the groove structure; the gate is arranged on one side of the dielectric layer, and a first P+ region is arranged on the other side of the dielectric layer, the upper surface of the gate electrode and the upper surface of the first P+ region are both flush with the upper surface of the dielectric layer, and the drain is arranged on the upper part of the first P+ region; an N-type well region is arranged between the dielectric layer and the gate electrode; a second P+ region and an N+ region are arranged on the upper part of the N-type well region, and the second P+ region and the N+ region are both located at the gate electrode The gate electrode is provided between the source and drain electrodes and the dielectric layer, the second P+ region is provided between the N+ region and the gate electrode, and the upper surfaces of the second P+ region and the N+ region are both flush with the upper surface of the dielectric layer; the source electrode is provided on the upper part of the N+ region, and a part of the source electrode is provided on the upper part of the second P+ region; compared with the prior art, the present invention has the source and drain electrodes and the buried oxide layer jointly bear the device withstand voltage, uses the dielectric layer as the actual withstand voltage structure, transfers the electric field peak from the surface electric field to the body, and the electric field on the surface of the dielectric layer and inside the dielectric layer is relatively low, so that the device will not break down prematurely on the surface, thereby changing the withstand voltage mechanism of the lateral high-voltage device, avoiding the problem of low lateral electric field caused by the surface of the traditional LDMOS high-voltage device relying on the silicon layer to withstand voltage, and enhancing the lateral withstand voltage capability of the device per unit length.

[0039] Other beneficial effects of the present invention will be described in detail in the subsequent specific implementation section. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 is a structural cross-sectional view of an embodiment of the present invention;

[0041] Figure 2 Schematic diagram of the preparation method in the embodiment of the present invention;

[0042] Figure 3 Schematic diagram of the process steps of the preparation method in an embodiment of the present invention.

[0043] Description of reference numerals:

[0044] 1-P-type substrate 2-gate 3-source 4-drain 5-buried oxide layer

[0045] 6-P-type drift region 7-dielectric layer 8-first P+ region 9-N-type well region

[0046] 10 - second P+ region 11 - N+ region 12 - gate oxide layer 13 - back gate. DETAILED DESCRIPTION

[0047] In order to make the technical problems, technical solutions and advantages to be solved by the present invention clearer, the following will be described in detail with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0048] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0049] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a locking connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0050] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0051] In view of the existing problems, the present invention provides a lateral MOS device and a preparation method thereof.

[0052] like Figure 1 As shown, an embodiment of the present invention provides a lateral MOS device, comprising:

[0053] P-type substrate 1, gate 2, source 3, drain 4;

[0054] The upper surface of the P-type substrate 1 is doped and epitaxially grown with a buried oxide layer 5 and a P-type drift region 6 in sequence;

[0055] The bottom of the gate 2 is connected to the upper surface of the buried oxide layer 5;

[0056] A trench structure is provided on the P-type drift region 6, and a dielectric layer 7 is filled inside the trench structure;

[0057] The gate 2 is arranged on one side of the dielectric layer 7, and a first P+ region 8 is arranged on the other side of the dielectric layer 7. The upper surface of the gate 2 and the upper surface of the first P+ region 8 are flush with the upper surface of the dielectric layer 7, and the drain 4 is arranged on the upper part of the first P+ region 8;

[0058] An N-type well region 9 is provided between the dielectric layer 7 and the gate 2;

[0059] A second P+ region 10 and an N+ region 11 are provided on the upper portion of the N-type well region 9. The second P+ region 10 and the N+ region 11 are both located between the gate 2 and the dielectric layer 7. The second P+ region 10 is located between the N+ region 11 and the gate 2. The upper surfaces of the second P+ region 10 and the N+ region 11 are both flush with the upper surface of the dielectric layer 7.

[0060] The source 3 is disposed on the upper portion of the N+ region 11 , and a portion of the source 3 is located on the upper portion of the second P+ region 10 .

[0061] In the embodiment of the present invention, the doping ions in the P-type drift region 6 are N-type doping ions with a gradient concentration, so that the doping concentration of the N+ region 11 near the source is relatively low, thereby achieving a low on-resistance.

[0062] The working principle of the lateral MOS device provided in the embodiment of the present invention is:

[0063] Under the action of an external electric field, the dielectric layer 7 adaptively introduces positive and negative charges from the source 3 and drain 4 partitions, so as to realize self-balance between the charges and the ionized donors in the drift region of the device and the positive and negative charges of the substrate. By changing the voltage-withstanding mechanism of the lateral high-voltage device, the voltage-withstanding capacity of the device is transferred from the source and drain ends to the P-type drift region 6 and the buried oxide layer 5 to jointly bear the voltage-withstanding capacity of the device, thereby realizing an improvement in the voltage-withstanding capacity. The dielectric layer 7 is used as the actual voltage-withstanding structure to avoid the problem of low lateral electric field caused by the surface voltage-withstanding capacity of the traditional LDMOS high-voltage device relying on the silicon layer, thereby enhancing the voltage-withstanding capacity of the device per unit length in the lateral direction.

[0064] Due to the existence of adaptive charges, the dielectric layer 7 introduces another electric field peak at the drain end to modulate the surface electric field; therefore, the electric field on the surface of the silicon layer and inside is low, and the device will not break down prematurely on the surface, thereby improving the lateral withstand voltage of the device. In addition, the charge balance between the positive and negative charges and the electron holes in the substrate greatly increases the electric flux of the buried oxide layer; in the buried oxide layer 5, the enhancement of the electric field leads to a higher longitudinal withstand voltage; in the depletion diffusion process, the depletion layer outside the trench gate structure expands toward the drain, effectively reducing the on-resistance of the device.

[0065] Most preferably, it further includes a gate oxide layer 12;

[0066] The gate oxide layer 12 is disposed between the gate 2 and the N-type well region 9;

[0067] The lower surface of the gate oxide layer 12 is connected to the upper surface of the buried oxide layer 5, and the side wall of the gate oxide layer 12 close to the N-type well region is connected to the side wall of the P-type drift region 6, the side wall of the N-type well region 9, and the side wall of the second P+ region 10 from bottom to top;

[0068] The upper surface of the gate oxide layer 12 is flush with the upper surface of the gate 2 .

[0069] Most preferably, silicon dioxide is selected as the medium in the dielectric layer 7 because silicon dioxide has a higher pressure resistance.

[0070] Most preferably, a back gate 13 is further included, which is arranged on the lower surface of the P-type substrate 1 and is used to control the electrical performance of the device by changing the electric field strength on the back side of the P-type substrate in the lateral MOS device.

[0071] In the embodiment of the present invention, the doping ions in the P-type drift region 6 are N-type doping ions with a gradient concentration, so that the ion doping concentration in the N-type drift region close to the source 3 is relatively low.

[0072] like Figure 2 and Figure 3 As shown, an embodiment of the present invention further provides a method for preparing a lateral MOS device, which is used to prepare a lateral MOS device. The preparation method includes:

[0073] Step 1, preparing a P-type substrate;

[0074] Step 2: On the P-type substrate, a gradient doping drift region is grown upward in sequence by using a variable doping epitaxial method of multiple growths to form a buried oxide layer and a P-type drift region, such as Figure 3 (a)

[0075] Step 3, etching the P-type drift region to form a trench structure, and filling the trench structure with a dielectric layer, such as Figure 3 (b)

[0076] Step 4: Coat photoresist on the upper surface of the dielectric layer and the P-type drift region, and inject ions on one side of the dielectric layer through the photoresist to form a P-type well region, such as Figure 3 (d)

[0077] Step 5, etching the edge of the P-type well region away from the dielectric layer to form a silicon groove, and forming a gate in the silicon groove, such as Figure 3 (e)

[0078] Step 6, performing ion implantation and annealing processes on the upper surfaces of the P-type well region and the P-type drift region to form a first P+ region, a second P+ region and an N+ region, such as Figure 3 (g) as shown;

[0079] Step 7, respectively etch the contact hole area on the upper surface of the N+ region and the upper surface of the first P+ region and grow aluminum electrodes to form a source and a drain, such as Figure 3 (h) shown.

[0080] It should be noted that the etching method adopted in the embodiment of the present invention is the etching commonly used in the semiconductor device manufacturing process. The embodiment of the present invention does not involve any improvement to the etching process, so the etching process is not described in detail in the embodiment.

[0081] In the embodiment of the present invention, the trench structure is located in the middle of the P-type drift region 6 , and its depth is smaller than the height of the P-type drift region 6 .

[0082] In an embodiment of the present invention, the dielectric layer is filled into the groove structure by low-pressure chemical vapor deposition. Low-pressure chemical vapor deposition is to introduce a gaseous reactant containing elements constituting a thin film into a reaction chamber, and a chemical reaction occurs on the surface of the wafer, thereby generating a desired solid thin film and depositing it on its surface. The reaction pressure is usually several hundred Pa, and the film formation speed can also be changed by adjusting the pressure. It has the advantages of low deposition temperature, easy control of film composition and thickness, film thickness being proportional to deposition time, good uniformity and repeatability, good step coverage, and easy operation.

[0083] In the embodiment of the present invention, by selecting the window position through photoresist and then performing etching, only the P-type drift region on one side of the dielectric layer 7 can be etched, and the other side will not be etched.

[0084] Specifically, step 5 also includes:

[0085] A gate oxide layer is grown in the silicon trench, and the gate oxide layer is located between the gate and the N-type well region, such as Figure 3 (f) as shown.

[0086] Most preferably, before coating the photoresist on the upper surface of the dielectric layer and the P-type drift region, the method further comprises:

[0087] The dielectric layer is flattened by chemical mechanical polishing so that the upper surface of the dielectric layer is flush with the upper surface of the P-type drift region. Figure 3 (c) as shown.

[0088] Most preferably, the dielectric filled in the dielectric layer is silicon dioxide.

[0089] Most preferably, after step 7, the method further comprises:

[0090] A back gate is grown on the lower surface of the P-type substrate. Figure 3 (h) shown.

[0091] Most preferably, the material used for the gate is polysilicon.

[0092] The lateral MOS device provided by the embodiment of the present invention comprises a P-type substrate, a gate, a source, and a drain; a buried oxide layer and a P-type drift region are sequentially grown on the upper surface of the P-type substrate by doping and epitaxial growth, which can reduce leakage and reduce the conduction voltage drop; the bottom of the gate is connected to the upper surface of the buried oxide layer; a trench structure is arranged on the P-type drift region, and a dielectric layer is filled inside the trench structure; the gate is arranged on one side of the dielectric layer, and a first P+ region is arranged on the other side of the dielectric layer, the upper surface of the gate electrode and the upper surface of the first P+ region are both flush with the upper surface of the dielectric layer, and the drain is arranged on the upper part of the first P+ region; an N-type well region is arranged between the dielectric layer and the gate electrode; a second P+ region and an N+ region are arranged on the upper part of the N-type well region, and the second P+ region and the N+ region are both located at the gate electrode The gate electrode is located between the source and drain electrodes and the dielectric layer, the second P+ region is located between the N+ region and the gate electrode, and the upper surfaces of the second P+ region and the N+ region are flush with the upper surface of the dielectric layer; the source electrode is arranged on the upper part of the N+ region, and a part of the source electrode is located on the upper part of the second P+ region; compared with the prior art, in the embodiment of the present invention, the source and drain electrodes and the buried oxide layer jointly bear the device withstand voltage, and the dielectric layer is used as the actual withstand voltage structure to transfer the electric field peak from the surface electric field to the body. The electric field on the surface of the dielectric layer and inside the dielectric layer is low, so that the device will not break down prematurely on the surface, thereby changing the withstand voltage mechanism of the lateral high-voltage device, avoiding the problem of low lateral electric field caused by the surface of the traditional LDMOS high-voltage device relying on the silicon layer to withstand voltage, and enhancing the lateral withstand voltage capability of the device per unit length.

[0093] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A lateral MOS device, characterized in that: include: P-type substrate (1), gate (2), source (3), drain (4); The upper surface of the P-type substrate (1) is doped and epitaxially grown with a buried oxide layer (5) and a P-type drift region (6) in sequence; The bottom of the gate (2) is connected to the upper surface of the buried oxide layer (5); A trench structure is provided on the P-type drift region (6), and a dielectric layer (7) is filled inside the trench structure; The gate electrode (2) is arranged on one side of the dielectric layer (7), a first P+ region (8) is arranged on the other side of the dielectric layer (7), the upper surface of the gate electrode (2) and the upper surface of the first P+ region (8) are both flush with the upper surface of the dielectric layer (7), and the drain electrode (4) is arranged on the upper part of the first P+ region (8); An N-type well region (9) is provided between the dielectric layer (7) and the gate (2); A second P+ region (10) and an N+ region (11) are provided on the upper portion of the N-type well region (9); the second P+ region (10) and the N+ region (11) are both located between the gate (2) and the dielectric layer (7); the second P+ region (10) is located between the N+ region (11) and the gate (2); and the upper surfaces of the second P+ region (10) and the N+ region (11) are both flush with the upper surface of the dielectric layer (7); The source electrode (3) is arranged on the upper part of the N+ region (11), and a part of the source electrode (3) is located on the upper part of the second P+ region (10).

2. The lateral MOS device according to claim 1, characterized in that: Also includes: Gate oxide layer (12); The gate oxide layer (12) is arranged between the gate (2) and the N-type well region (9); The lower surface of the gate oxide layer (12) is connected to the upper surface of the buried oxide layer (5), and the side wall of the gate oxide layer (12) close to the N-type well region is connected from bottom to top to the side wall of the P-type drift region (6), the side wall of the N-type well region (9), and the side wall of the second P+ region (10); The upper surface of the gate oxide layer (12) is flush with the upper surface of the gate (2).

3. The lateral MOS device according to claim 2, characterized in that: The medium in the medium layer (7) is silicon dioxide.

4. The lateral MOS device according to claim 3, characterized in that: Also includes: A back gate (13) is arranged on the lower surface of the P-type substrate (1).

5. A method for preparing a lateral MOS device, characterized in that: Used to prepare the lateral MOS device according to any one of claims 1 to 4, the preparation method comprising: Step 1, preparing a P-type substrate; Step 2, growing a gradually doped drift region upward in sequence on the P-type substrate by adopting a variable doping epitaxial method of multiple growths to form a buried oxide layer and a P-type drift region; Step 3, etching the P-type drift region to form a trench structure, and filling a dielectric layer in the trench structure; Step 4, coating a photoresist on the upper surface of the dielectric layer and the P-type drift region, and injecting ions on one side of the dielectric layer through the photoresist to form a P-type well region; Step 5, etching the edge of the P-type well region away from the dielectric layer to form a silicon groove, and forming a gate in the silicon groove; Step 6, performing ion implantation and annealing processes on the upper surfaces of the P-type well region and the P-type drift region to form a second P+ region and an N+ region; Step 7: etching contact hole regions on the upper surface of the N+ region and the upper surface of the first P+ region respectively and growing aluminum electrodes to form a source and a drain.

6. The method for preparing a lateral MOS device according to claim 5, characterized in that: Step 5 also includes: A gate oxide layer is grown in the silicon trench, and the gate oxide layer is located between the gate and the N-type well region.

7. The method for preparing a lateral MOS device according to claim 6, characterized in that: Before coating the photoresist on the upper surface of the dielectric layer and the P-type drift region, the method further comprises: The dielectric layer is planarized by chemical mechanical polishing, so that the upper surface of the dielectric layer is flush with the upper surface of the P-type drift region.

8. The method for preparing a lateral MOS device according to claim 7, characterized in that: The medium filled in the dielectric layer is silicon dioxide.

9. The method for preparing a lateral MOS device according to claim 8, characterized in that: After step 7, the following steps are also included: A back gate is grown on the lower surface of the P-type substrate.

10. The method for preparing a lateral MOS device according to claim 9, characterized in that: The gate is made of polysilicon.

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