Virtual system on chip, IO pin multiplexing simulation method and device and storage medium

Abstract

The invention relates to the technical field of virtual systems on chip, and discloses a virtual system on chip, an I-O pin multiplexing simulation method and device thereof and a storage medium. Wherein each virtual on-chip device of the virtual on-chip system comprises a plurality of virtual ports, the virtual I O module comprises a plurality of virtual off-chip ports, a plurality of virtual on-chip ports and a plurality of input and output marks, and the plurality of virtual off-chip ports and the input and output marks are in one-to-one correspondence with a plurality of pins of a virtualized chip. The plurality of virtual on-chip ports are in one-to-one correspondence with a plurality of functions of a plurality of pins of a virtualized chip. The on-chip port configuration module is used for recording the pairing relationship between the virtual on-chip ports and the virtual ports, and the pin configuration detection module is used for confirming the pairing relationship between the virtual off-chip ports and the virtual on-chip ports according to a user program. And the input driving module and the output driving module are respectively used for driving data input and output. The system can truly simulate the multiplexing function of the I-O pin of the SoC chip, and can completely verify the user program.

Description

Technical Field

[0001] The present invention relates to the technical field of virtual system-on-chip, and in particular to a virtual system-on-chip, an IO pin multiplexing simulation method, a device and a storage medium. Background Art

[0002] System on Chip (SoC) is a technology that integrates most or all electronic components in a traditional computer or other electronic system into a single integrated circuit (chip). The IO module (input-output module) is an important bridge for the interaction between the SoC and external devices. It is responsible for processing data transmission and signal conversion between the internal devices of the chip and external devices. In practical applications, most IO pins of the IO module often have multiple functions. They can be used as ordinary input and output pins, or they can be assigned to internal devices as functional pins through configuration.

[0003] As the design complexity and integration of SoCs continue to increase, the interaction between user code (such as drivers, firmware, etc.) and SoC hardware becomes more and more complex, resulting in the increasing cost of traditional direct use of hardware prototypes to verify user code, and there are problems such as long verification cycle and poor flexibility, which makes it difficult to meet the development needs of rapid iteration. In order to solve the above problems, user code is often verified by building a virtual system-on-chip that can simulate the behavior, structure and timing of SoCs using a modeling language. In current virtual systems-on-chip, the pin reuse function of the IO module is usually ignored. Designers usually make virtual on-chip devices communicate directly with off-chip devices without forwarding through the multiplexing function of the IO module, resulting in the lack of functions of the virtual system-on-chip. This neglect may cause the simulation system to be unable to fully verify all functions of the SoC design, especially those advanced functions that rely on IO pin reuse. To this end, it is necessary to propose a pin reuse simulation method for the IO module to improve the accuracy and reliability of the simulation of the virtual system-on-chip. Summary of the invention

[0004] In order to overcome the deficiencies of the prior art, the object of the present invention is to provide a virtual system on chip that can truly simulate the pin multiplexing function of the IO module of the system on chip and improve the reliability and accuracy of the simulation of the virtual system on chip to the real SoC chip.

[0005] To solve the above problems, the technical solution adopted by the present invention is as follows: a virtual system on chip, comprising: a plurality of virtual on-chip devices, used to simulate the functions of the on-chip devices of a virtualized chip, each of the virtual on-chip devices comprising a plurality of virtual ports; a virtual IO module, comprising a plurality of virtual off-chip ports, a plurality of virtual on-chip ports and a plurality of input / output flags, the plurality of virtual off-chip ports corresponding one-to-one to a plurality of pins of a virtualized chip, the plurality of virtual on-chip ports corresponding one-to-one to a plurality of functions of a plurality of pins of a virtualized chip, and the plurality of input / output flags corresponding one-to-one to a plurality of pins of a virtualized chip; an on-chip port configuration module, used to record the pairing relationship between the plurality of virtual on-chip ports and the plurality of virtual ports; a pin configuration detection module, used to confirm the pairing relationship between the plurality of virtual off-chip ports and the plurality of virtual on-chip ports according to a user program; An input driver module is used to monitor the values ​​of the plurality of virtual off-chip ports and the values ​​of the plurality of input / output flags, and when the input / output flag is an input flag, drive the value of the corresponding virtual on-chip port to the corresponding virtual on-chip port according to the pairing relationship confirmed by the pin configuration detection module, and drive the value of the virtual on-chip port to the corresponding virtual port according to the pairing relationship recorded by the on-chip port configuration module; an output driver module is used to monitor the values ​​of the plurality of virtual ports and the values ​​of the plurality of input / output flags, and when the input / output flag is an output flag, drive the value of the virtual port to the corresponding virtual on-chip port according to the pairing relationship recorded by the on-chip port configuration module, and drive the value of the virtual on-chip port to the corresponding virtual off-chip port according to the pairing relationship confirmed by the pin configuration detection module.

[0006] Compared with the prior art, the beneficial effect of the present invention lies in: by establishing a virtual IO module including multiple virtual on-chip ports and virtual off-chip ports to imitate the IO module in a real SoC chip, and by simulating the forwarding mechanism of the IO module through a pin configuration detection module, an input driver module and an output driver module, the pin multiplexing function of the real SoC chip is realized, thereby improving the accuracy and reliability of the simulation of the virtual on-chip system to the real SoC, being able to more accurately verify the functional integrity of the user code, and reducing the R&D cost of the SoC supporting program.

[0007] In the above-mentioned virtual system on chip, the virtual on-chip ports include virtual on-chip input ports and virtual on-chip output ports.

[0008] In the above-mentioned virtual on-chip system, the multiple virtual off-chip ports are a group of off-chip registers with defined serial numbers, and the serial numbers of the multiple off-chip registers correspond one-to-one to the serial numbers of the multiple pins of the virtualized chip. The multiple virtual on-chip input ports are a group of input on-chip register groups with defined serial numbers, and the serial numbers of the multiple input on-chip register groups correspond one-to-one to the serial numbers of the multiple pins of the virtualized chip. Each of the input on-chip register groups includes multiple input on-chip registers with defined serial numbers, and each of the input on-chip registers corresponds one-to-one to the multiple input functions of each corresponding pin. The multiple virtual on-chip output ports are a group of output on-chip register groups with defined serial numbers, and each of the output on-chip register groups includes multiple output on-chip registers with defined serial numbers, and each of the output on-chip registers corresponds one-to-one to the multiple output functions of each corresponding pin.

[0009] In the above-mentioned virtual on-chip system, the pin configuration detection module includes a group of configuration registers with defined serial numbers, and the serial numbers of multiple configuration registers correspond one-to-one to the serial numbers of multiple pins of the virtualized chip. The pin configuration detection module confirms the function selected by each pin according to the user program, and writes the serial number of the output on-chip register or the input on-chip register corresponding to the selected function into the corresponding configuration register.

[0010] A virtual system-on-chip IO pin multiplexing simulation method, comprising:

[0011] A group of off-chip registers and at least one group of on-chip registers are defined, each off-chip register corresponds to a pin of a virtualized chip, and each on-chip register corresponds to a function of a pin of a virtualized chip;

[0012] According to the pairing relationship between the pins of the virtualized chip and the ports of the on-chip device, the plurality of on-chip registers are paired with the virtual ports of the plurality of virtual on-chip devices;

[0013] Obtain the real-time functional configuration of the pins of the virtualized chip according to the executed user program;

[0014] According to the confirmed function configuration of each pin of the virtualized chip, pair the off-chip register corresponding to the same pin with the on-chip register;

[0015] Monitor the input and output status of each pin, drive the value of the off-chip register corresponding to the pin of the input status to the paired on-chip register, and drive the value of the on-chip register corresponding to the pin of the input status to the paired virtual port; drive the value of the virtual port to the on-chip register corresponding to the paired output status pin, and drive the value of the on-chip register corresponding to the pin of the output status to the off-chip register.

[0016] The above-mentioned IO pin multiplexing simulation method, wherein the step of defining a group of off-chip registers and at least one group of on-chip registers, each off-chip register corresponds to a pin of a virtualized chip, and each on-chip register corresponds to a function of a pin of a virtualized chip specifically includes:

[0017] Define a group of off-chip registers and number them consecutively. The maximum serial number of the off-chip register is equal to the maximum pin number of the virtualized chip.

[0018] Define a group of input on-chip register groups, number the input on-chip register groups consecutively, the maximum serial number of the input on-chip register group is equal to the maximum pin serial number of the virtualized chip, and the number of registers in each group of input on-chip register groups is the same as the number of types of input functions of the corresponding pins;

[0019] Define a group of output on-chip register groups, number the output on-chip register groups consecutively, the maximum serial number of the output on-chip register group is equal to the maximum pin serial number of the virtualized chip, and the number of registers in each group of output on-chip register groups is the same as the number of types of output functions of the corresponding pins;

[0020] Assigning the serial number of the input function of each pin of the virtualized chip to each input on-chip register in the corresponding input on-chip register group;

[0021] The serial number of the output function of each pin of the virtualized chip is assigned to each input on-chip register in the corresponding output on-chip register group.

[0022] In the above-mentioned IO pin multiplexing simulation method, the step of obtaining the functional configuration of the pins of the virtualized chip in real time according to the executed user program comprises:

[0023] Define a group of configuration registers, number the configuration registers consecutively, and the maximum number of the configuration register is equal to the maximum pin number of the virtualized chip;

[0024] Obtain the real-time functional configuration of each virtualized chip pin according to the executed user program;

[0025] Get the input and output flags of each pin, and determine the input and output status of each pin according to the input and output flags;

[0026] Query the corresponding function number according to the function configuration and input and output status of each pin;

[0027] Write the function number of each pin into the configuration register with the same number as the pin.

[0028] The above-mentioned IO pin multiplexing simulation method, the step of pairing the off-chip register corresponding to the same pin with the on-chip register according to the confirmed functional configuration of each pin of the virtualized chip includes:

[0029] According to the pin number, query the value of the input and output flag corresponding to the pin, and obtain the value pin_afr[x] stored in the configuration register with the same number as the pin;

[0030] If the value of the input / output flag of the pin indicates the output state, the off-chip register with the same serial number as the pin is paired with the output on-chip register with the serial number pin_afr[x] in the output on-chip register group with the same serial number as the pin;

[0031] If the value of the input / output flag of the pin indicates the input state, the off-chip register with the same serial number as the pin is paired with the input on-chip register with the serial number pin_afr[x] in the input on-chip register group with the same serial number as the pin.

[0032] A storage medium stores a computer program, wherein when the computer program is called and executed by a processor, the IO pin multiplexing simulation method of the virtual system on chip is implemented.

[0033] A virtual device of a system on chip includes a processor and a memory, wherein the memory is electrically connected to the processor, and the processor can implement the above-mentioned virtual system on chip IO pin multiplexing simulation method by calling and executing a computer program in the memory.

[0034] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 is a principle block diagram of a virtual system on chip according to an embodiment of the present invention;

[0036] Figure 2 Flow chart of the IO pin multiplexing simulation method of the virtual system on chip according to the embodiment of the present invention DETAILED DESCRIPTION

[0037] The embodiments of the present invention are described in detail below. Figure 1The embodiment of the present invention provides a virtual system on chip, including multiple virtual on-chip devices, a virtual IO module, an on-chip port configuration module, a pin configuration detection module, an input driver module and an output driver module. The virtual on-chip device is used to simulate the function of the on-chip device of the virtualized SoC chip, such as serial port, SPI, I2C or ADC on-chip devices. Each on-chip device includes several virtual ports, and the virtual ports serve as input and output ports of the virtual on-chip device. The virtual IO module includes multiple virtual off-chip ports, multiple virtual on-chip ports and multiple input and output flags. The virtual off-chip ports correspond one-to-one to multiple pins of the virtualized SoC chip, the virtual on-chip ports correspond one-to-one to multiple functions of multiple pins of the virtualized SoC chip, and the input and output flags correspond one-to-one to multiple pins of the virtualized SoC chip. The on-chip port configuration module is used to record the pairing relationship between the virtual on-chip port and the virtual port of the virtual on-chip device. The pairing relationship is determined according to the function of each pin of the virtualized SoC chip, and the on-chip virtual port is paired with the virtual port of the virtual on-chip device that performs the corresponding function according to the pin function corresponding to the on-chip virtual port. The pin configuration detection module is used to confirm the pairing relationship between the virtual off-chip port and the virtual off-chip port according to the executed user program, obtain the real-time function configuration of each pin according to the user program, and pair the virtual off-chip port corresponding to the pin with the virtual on-chip port corresponding to the function configured by the pin according to the function configured by the pin. The input driver module and the output module are used to monitor the values ​​of the virtual port, the virtual on-chip port, the virtual off-chip port and the input and output flags, judge the input and output status of the pin according to the input and output flags, and drive the value to be transmitted between the paired virtual port, the virtual on-chip port and the virtual off-chip port according to the input and output status, simulating the interaction of data signals between the virtual on-chip device and the external device.

[0038] The virtual system on chip of the embodiment of the present invention simulates the forwarding mechanism of the IO module of the real SoC chip when implementing the pin multiplexing function by setting a virtual IO module and a pin configuration detection module, thereby simulating the IO pin multiplexing function of the real SoC chip, and can more completely and reliably realize the simulation of the SoC chip to be verified. The virtual system on chip is used to verify the user program, and the configuration function of the IO pin function in the user program can be verified, and the complete function of the user program can be verified, thereby ensuring the reliability and accuracy of the verification and reducing the user's development cost.

[0039] It is understandable that virtual on-chip devices, virtual IO modules, on-chip port configuration modules, pin configuration detection modules, input driver modules and output driver modules are all constructed using SystemC language. SystemC is a high-level modeling language based on C++, developed specifically for system-level design and modeling, with a rich set of class libraries that enable designers to describe and simulate system behavior, structure and timing at a higher level of abstraction.

[0040] In this embodiment, for the convenience of description, the virtual port, virtual off-chip port, virtual on-chip port and input / output flag are all described and defined in the form of registers. The virtual off-chip port is a group of off-chip registers that are numbered consecutively, and the maximum serial number of the off-chip register is equal to the maximum pin serial number of the pin of the virtualized SoC chip, and each on-chip register corresponds to the pin with the same serial number. The virtual on-chip port includes a group of consecutively numbered input on-chip register groups and a group of consecutively numbered output on-chip register groups, and the maximum serial numbers of the input on-chip register groups and the output on-chip register groups are also equal to the maximum pin serial number of the pin of the virtualized SoC chip. Each group of input on-chip register groups corresponds to multiple input functions of the pins with the same serial number, and the number of input on-chip registers in each group of input on-chip register groups is equal to the type of input function of the pins with the same serial number. Each group of output on-chip register groups corresponds to multiple output functions of the pins with the same serial number, and the number of output on-chip registers in each group of output on-chip register groups corresponds to the output function of the pins with the same serial number. Taking the virtual system on chip of the SoC chip model MM32F5270 as an example, its IO module contains 16 pins, each pin has 16 multiplexed input and output functions, it is necessary to define an off-chip register group pin

[16] with 16 off-chip registers, a two-dimensional input on-chip register group afio_pin_in

[16]

[16] consisting of 16 input on-chip register groups with 16 input on-chip registers, and a two-dimensional output on-chip register group afio_pin_out

[16]

[16] consisting of 16 output on-chip register groups with 16 output on-chip registers.

[0041] The input and output flags are multiple consecutively numbered input and output flag registers. The maximum number of the input and output flag registers is equal to the maximum pin number of the virtualized chip pin. The input and output status of the pin can be determined by querying the value of the input and output flag register with the same number. The pin configuration detection module includes multiple consecutively numbered configuration registers. The maximum number of the configuration register is equal to the maximum pin number of the virtualized chip. Taking the virtual system on chip of the SoC chip model MM32F5270 as an example, it is necessary to define an input and output flag register group pin_cnf

[16] consisting of 16 input and output flag registers, and a configuration register group pin_afr

[16] consisting of 16 configuration registers.

[0042] In this embodiment, the pin configuration detection function pin_check-func is defined by the SystemC language to detect the input and output status and function configuration of each pin, and the value of the input and output flag register and the configuration register of each pin is modified according to the input and output status and function configuration of each pin, so as to realize the function of the pin configuration detection module. The input driver function pin_in_fun and the output driver function pin_out_fun are defined by the SystemC language to respectively realize the functions of the input driver function and the output driver function, drive the value of the off-chip register to the paired virtual port through the paired input on-chip register, and drive the value of the virtual port to the off-chip register through the paired output on-chip register, so as to realize the simulation of the forwarding mechanism of the pin multiplexing function of the IO module of the real SoC chip.

[0043] It is understandable that, usually, a corresponding flag register is set inside a real SoC chip to mark the input and output status and function configuration of the pin. The pin configuration detection function can obtain the real-time function configuration and input and output configuration of the pin by monitoring the write operation of the pin flag register in the user program, and synchronize the written value to the corresponding input and output flag register and configuration register. And usually, the real SoC chip realizes the configuration of the pin function by modifying the value of the pin function configuration register. The system on chip will pre-define the function number for each function of the pin, and realize the configuration of a specific function by writing the required function number into the function configuration register. Therefore, the serial number of the pin function can be defined to the corresponding input on-chip register or input off-chip register, and the input driver function pin_in_fun and the output driver function pin_out_fun can query the input on-chip register or output on-chip register paired with the off-chip register by using the configuration register as a pointer.

[0044] Reference Figure 2Based on the same inventive concept, the IO pin multiplexing simulation method of the virtual system on chip of the present application includes the following steps:

[0045] A group of off-chip registers and at least one group of on-chip registers are defined, each off-chip register corresponds to a pin of a virtualized chip, and each on-chip register corresponds to a function of a pin of a virtualized chip;

[0046] According to the pairing relationship between the pins of the virtualized chip and the ports of the on-chip device, the plurality of on-chip registers are paired with the virtual ports of the plurality of virtual on-chip devices;

[0047] Obtain the real-time functional configuration of the pins of the virtualized chip according to the executed user program;

[0048] According to the confirmed function configuration of each pin of the virtualized chip, pair the off-chip register corresponding to the same pin with the on-chip register;

[0049] Monitor the input and output status of each pin, drive the value of the off-chip register corresponding to the pin of the input status to the paired on-chip register, and drive the value of the on-chip register corresponding to the pin of the input status to the paired virtual port; drive the value of the virtual port to the on-chip register corresponding to the paired output status pin, and drive the value of the on-chip register corresponding to the pin of the output status to the off-chip register.

[0050] Specifically, it is necessary to define the number of off-chip registers and on-chip registers according to the number of pins of the virtualized real SoC chip and the multiplexed functions of the pins, so that each pin has a corresponding off-chip register, each function of each pin has a corresponding on-chip register, the output function of the same pin corresponds to an output on-chip register group, and the input function of the same pin corresponds to an input on-chip register group, so as to simulate the input and output functions of the pins. Since the pins of the real SoC chip are usually numbered consecutively, and each function of each pin also has a corresponding function serial number, in this embodiment, the on-chip registers, input on-chip registers, and output on-chip registers can be numbered consecutively to make them correspond to the pins one by one. At the same time, since each function of the pins of the real SoC chip is also assigned a function serial number under normal circumstances, the input function serial number and the output function serial number of each pin of the SoC chip can be directly assigned to the registers in the corresponding input on-chip register group and the output on-chip register group, respectively, so that the on-chip registers and the functions of the pins can correspond one by one.

[0051] Taking the virtual system on chip of the SoC chip model MM32F5270 as an example, the defined pin configuration detection function pin_check_func is used to monitor the input and output status and function configuration of the pins by the user program, and synchronize them to the input and output flag register group pin_cnf

[16] and the configuration register group pin_afr

[16] . Then, according to the input and output status marked in the input and output flag registers of each pin, the input driver function pin_in_fun and the output driver function pin_out_fun are called to drive the value to be transferred between the off-chip register group pin

[16] , the two-dimensional input on-chip register group afio_pin_in

[16]

[16] , the two-dimensional output on-chip register group afio_pin_out

[16]

[16] and the virtual port of the virtual on-chip device.

[0052] In this embodiment, the pin configuration check function includes 16 sub-pin configuration check functions pin_check_func0 to pin_check_func15, the input drive function pin_in_fun includes 16 sub-input drive functions pin_in_fun0 to pin_in_fun15, and the output drive function pin_out_fun includes 16 output drive functions pin_out_fun0 to pin_out_fun15.

[0053] The value in the input / output flag register group pin_cnf is 0 to indicate the input state, and 1 to indicate the output state. Assuming that the sub-pin configuration detection function pin_check_func6 of the 6th pin and the sub-pin configuration detection function pin_check_func7 of the 7th pin respectively obtain the user program's need to configure the 6th pin as the input of the 7th function and the 7th pin as the output of the 7th function, then the sub-pin configuration detection function pin_check_func6 writes 0 and 7 to the input / output flag register pin_cnf[6] and the configuration register pin_afr[6] respectively, and the sub-pin configuration detection function pin_check_func7 writes 1 and 7 to the input / output flag registers pin_cnf[7] and pin_afr[7] respectively. Subsequently, after detecting that the value in the input / output flag register pin_cnf[6] is 0, the sub-input driver function pin_in_fun6 drives the value in the off-chip register pin[6] to the input on-chip register afio_pin_in[6][7] according to the value in the configuration register pin_afr[6], and drives the value in the input on-chip register afio_pin_in[6][7] to the virtual port of the paired virtual on-chip device. After detecting that the value in the input / output flag register pin_cnf[7] is 1, the sub-output driver function pin_in_fun7 drives the virtual port value of the paired virtual on-chip device afio_pin_out[7][7] to the register according to the value in the configuration register pin_afr[7], and drives the value of the output on-chip register afio_pin_out[7][7] to the off-chip register pin[7].

[0054] Based on the same inventive concept, an embodiment of the present invention further provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the IO pin multiplexing simulation method of the virtual system on chip can be implemented.

[0055] In some possible embodiments, various aspects of the IO pin multiplexing simulation method for a virtual system on chip provided by the present invention can also be implemented in the form of a program product, which includes a program code. When the program product is run on an apparatus, the program code is used to enable the control device to execute the steps of the IO pin multiplexing simulation method for a virtual system on chip described above in this specification according to various exemplary embodiments of the present application.

[0056] Based on the same inventive concept, an embodiment of the present invention also provides a virtual device for implementing the above-mentioned virtual system-on-chip IO pin multiplexing simulation method, including a processor and a memory, the memory is electrically connected to the processor, and when the processor is used to execute a computer program stored in the memory, the above-mentioned virtual system-on-chip IO pin multiplexing simulation method is implemented.

[0057] In one possible design, the processor may include one or more processing units, and the processor and memory may be implemented on the same chip or separately on independent chips. The processor may be a general-purpose processor, such as a central processing unit (CPU), a digital signal processor, an application-specific integrated circuit, a field programmable gate array or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, and may implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of the present application. The general-purpose processor may be a microprocessor or any conventional processor, etc. The steps of the IO pin multiplexing simulation method of the virtual system-on-chip disclosed in the embodiments of the present application may be directly embodied as being executed by a hardware processor, or executed by a combination of hardware and software modules in the processor.

[0058] As a non-volatile computer-readable storage medium, the memory can be used to store non-volatile software programs, non-volatile computer executable programs and modules. The memory can include at least one type of storage medium, for example, it can include flash memory, hard disk, multimedia card, card-type memory, random access memory (Random Access Memory, RAM), static random access memory (Static RandomAccess Memory, SRAM), programmable read-only memory (Programmable Read Only Memory, PROM), read-only memory (Read Only Memory, ROM), electrically erasable programmable read-only memory (Electrically Erasable Programmable Read-Only Memory, EEPROM), magnetic memory, disk, CD, etc. The memory is any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory in the embodiment of the present application can also be a circuit or any other device that can realize a storage function, for storing program instructions and / or data.

[0059] By designing and programming the processor, the code corresponding to the IO pin multiplexing simulation method of the virtual system on chip introduced in the above embodiment can be fixed into the chip, so that the chip can execute the steps of the IO pin multiplexing simulation method of the virtual system on chip in the embodiment shown in the present invention when running. How to design and program the processor is a technology well known to those skilled in the art and will not be described in detail here.

[0060] The present application is described with reference to the flowcharts and / or block diagrams of the methods, apparatus (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0061] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0062] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0063] In the description of the present invention, unless otherwise clearly defined, terms such as setting, installing, connecting, etc. should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in the present invention based on the specific content of the technical solution.

[0064] The above-mentioned embodiments are only preferred embodiments of the present invention and cannot be used to limit the scope of protection of the present invention. Any non-substantial changes and substitutions made by technicians in this field on the basis of the present invention shall fall within the scope of protection required by the present invention.

Claims

1. A virtual system on chip, characterized in that: include: A plurality of virtual on-chip devices, used to simulate the functions of the on-chip devices of the virtualized chip, each of the virtual on-chip devices comprising a plurality of virtual ports; A virtual IO module, comprising a plurality of virtual off-chip ports, a plurality of virtual on-chip ports and a plurality of input / output flags, wherein the plurality of virtual off-chip ports correspond one-to-one to a plurality of pins of a virtualized chip, the plurality of virtual on-chip ports correspond one-to-one to a plurality of functions of a plurality of pins of a virtualized chip, and the plurality of input / output flags correspond one-to-one to a plurality of pins of a virtualized chip; An on-chip port configuration module, used for recording the pairing relationship between the plurality of virtual on-chip ports and the plurality of virtual ports; A pin configuration detection module, used for confirming the pairing relationship between the plurality of virtual off-chip ports and the plurality of virtual on-chip ports according to a user program; an input driver module, used for monitoring the values ​​of the plurality of virtual off-chip ports and the values ​​of the plurality of input / output flags, and for driving the value of the corresponding virtual on-chip port to the corresponding virtual on-chip port according to the pairing relationship confirmed by the pin configuration detection module when the input / output flag is an input flag, and driving the value of the virtual on-chip port to the corresponding virtual port according to the pairing relationship recorded by the on-chip port configuration module; The output driver module is used to monitor the values ​​of the multiple virtual ports and the values ​​of the multiple input-output flags, and is used to drive the value of the virtual port to the corresponding virtual on-chip port according to the pairing relationship recorded by the on-chip port configuration module when the input-output flag is an output flag, and drive the value of the virtual on-chip port to the corresponding virtual off-chip port according to the pairing relationship confirmed by the pin configuration detection module.

2. The virtual system on chip according to claim 1, characterized in that: The virtual on-chip ports include virtual on-chip input ports and virtual on-chip output ports.

3. The virtual system on chip according to claim 2, characterized in that: The multiple virtual off-chip ports are a group of off-chip registers with defined serial numbers, and the serial numbers of the multiple off-chip registers correspond one-to-one to the serial numbers of the multiple pins of the virtualized chip. The multiple virtual on-chip input ports are a group of input on-chip register groups with defined serial numbers, and the serial numbers of the multiple input on-chip register groups correspond one-to-one to the serial numbers of the multiple pins of the virtualized chip. Each of the input on-chip register groups includes multiple input on-chip registers with defined serial numbers, and each of the input on-chip registers corresponds one-to-one to the multiple input functions of each corresponding pin. The multiple virtual on-chip output ports are a group of output on-chip register groups with defined serial numbers, and each of the output on-chip register groups includes multiple output on-chip registers with defined serial numbers, and each of the output on-chip registers corresponds one-to-one to the multiple output functions of each corresponding pin.

4. The virtual system on chip according to claim 3, characterized in that: The pin configuration detection module includes a group of configuration registers with defined serial numbers, and the serial numbers of multiple configuration registers correspond one-to-one to the serial numbers of multiple pins of the virtualized chip. The pin configuration detection module confirms the function selected by each pin according to the user program, and writes the serial number of the output on-chip register or the input on-chip register corresponding to the selected function into the corresponding configuration register.

5. A method for simulating IO pin multiplexing of a virtual system on chip, characterized in that: include: A group of off-chip registers and at least one group of on-chip registers are defined, each off-chip register corresponds to a pin of a virtualized chip, and each on-chip register corresponds to a function of a pin of a virtualized chip; According to the pairing relationship between the pins of the virtualized chip and the ports of the on-chip device, the plurality of on-chip registers are paired with the virtual ports of the plurality of virtual on-chip devices; Obtain the real-time functional configuration of the pins of the virtualized chip according to the executed user program; According to the confirmed function configuration of each pin of the virtualized chip, pair the off-chip register corresponding to the same pin with the on-chip register; Monitor the input and output status of each pin, drive the value of the off-chip register corresponding to the pin of the input status to the paired on-chip register, and drive the value of the on-chip register corresponding to the pin of the input status to the paired virtual port; The value of the virtual port is driven to the on-chip register corresponding to the paired output state pin, and the value of the on-chip register corresponding to the output state pin is driven to the off-chip register.

6. The IO pin multiplexing simulation method according to claim 5, characterized in that: The step of defining a group of off-chip registers and at least one group of on-chip registers, each off-chip register corresponds to a pin of a virtualized chip, and each on-chip register corresponds to a function of a pin of a virtualized chip specifically includes: Define a group of off-chip registers and number them consecutively. The maximum serial number of the off-chip registers is equal to the maximum pin number of the virtualized chip. Define a group of input on-chip register groups, number the input on-chip register groups consecutively, the maximum serial number of the input on-chip register group is equal to the maximum pin serial number of the virtualized chip, and the number of registers in each group of input on-chip register groups is the same as the number of types of input functions of the corresponding pins; Define a group of output on-chip register groups, number the output on-chip register groups consecutively, the maximum serial number of the output on-chip register group is equal to the maximum pin serial number of the virtualized chip, and the number of registers in each group of output on-chip register groups is the same as the number of types of output functions of the corresponding pins; Assigning the serial number of the input function of each pin of the virtualized chip to each input on-chip register in the corresponding input on-chip register group; The serial number of the output function of each pin of the virtualized chip is assigned to each input on-chip register in the corresponding output on-chip register group.

7. The IO pin multiplexing simulation method according to claim 6, characterized in that: The step of obtaining the functional configuration of the pins of the virtualized chip in real time according to the executed user program comprises: Define a group of configuration registers, number the configuration registers consecutively, and the maximum number of the configuration register is equal to the maximum pin number of the virtualized chip; Obtain the real-time functional configuration of each virtualized chip pin according to the executed user program; Get the input and output flags of each pin, and determine the input and output status of each pin according to the input and output flags; Query the corresponding function number according to the function configuration and input and output status of each pin; Write the function number of each pin into the configuration register with the same number as the pin.

8. The IO pin multiplexing simulation method according to claim 7, characterized in that: The step of pairing the off-chip register corresponding to the same pin with the on-chip register according to the confirmed functional configuration of each pin of the virtualized chip comprises: According to the pin number, query the value of the input and output flag corresponding to the pin, and obtain the value pin_afr[x] stored in the configuration register with the same number as the pin; If the value of the input / output flag of the pin indicates the output state, the off-chip register with the same serial number as the pin is paired with the output on-chip register with the serial number pin_afr[x] in the output on-chip register group with the same serial number as the pin; If the value of the input / output flag of the pin indicates the input state, the off-chip register with the same serial number as the pin is paired with the input on-chip register with the serial number pin_afr[x] in the input on-chip register group with the same serial number as the pin.

9. A storage medium storing a computer program, characterized in that: When the computer program is called and executed by a processor, the IO pin multiplexing simulation method of the virtual system on chip according to any one of claims 1 to 8 is implemented.

10. A virtual device of a system on chip, characterized in that: It comprises a processor and a memory, the memory is electrically connected to the processor, and the processor can implement the IO pin multiplexing simulation method of the virtual system on chip according to any one of claims 1 to 8 by calling and executing a computer program in the memory.

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