Nanoelectrode preparation method of two-dimensional material memristor

Abstract

The invention provides a nanoelectrode preparation method of a two-dimensional material memristor, and relates to the technical field of semiconductor device preparation, and the method comprises the steps: carrying out the spin coating of a PMMA diluent on a substrate, carrying out the electron beam exposure, carrying out the low-temperature development, and forming a patterned bottom contact electrode; performing physical vapor deposition, photoresist removal and stripping on the patterned bottom contact electrode to obtain a bottom contact electrode; preparing an insulating layer on the substrate for preparing the bottom contact electrode by using an atomic layer deposition mode; copper substrate etching is carried out on the two-dimensional material with the copper substrate, and the two-dimensional material with the copper substrate is transferred to the position above the insulating layer; performing patterning treatment on the transferred two-dimensional material to obtain a patterned two-dimensional material electrode; pMMA diluent is spin-coated on the surface of the substrate after patterning of the two-dimensional material, electron beam exposure and low-temperature development are carried out after baking and glue solidification, and a patterned top contact electrode is formed; and performing physical vapor deposition on the patterned top contact electrode to obtain the top contact electrode. The size of the device can be greatly reduced, and the performance uniformity of the device is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device preparation, and in particular to a method for preparing a nano-electrode of a two-dimensional material memristor. Background Art

[0002] In order to overcome the limitations of the von Neumann architecture in terms of speed and power consumption, it is necessary to achieve the integration of data storage and computing on the same architecture, so in-memory computing has become a research hotspot in the field of brain-like computing. Memristors have a simple structure and store data in a resistive state. Their cross-array structure can naturally store data and perform calculations. They have unique advantages in in-memory computing applications and can greatly simplify the neural network structure, increase computing speed, and reduce power consumption. Due to their high mobility, surface area ratio, and atomic-level thickness, two-dimensional materials can be used in memristors to further reduce device area and power consumption.

[0003] However, the characteristic size of two-dimensional material memristors has remained at the micron level, which is still a big gap from the integrated size of silicon-based circuits. It is necessary to further miniaturize the device size, reduce power consumption, and promote high-density integration of in-memory computing architectures. In addition, the uniformity of two-dimensional materials is poor, which seriously limits the yield of devices in memory computing circuits. It is urgent to significantly reduce the device size and improve the uniformity of device performance. Summary of the invention

[0004] The present invention provides a method for preparing a nano-electrode of a two-dimensional material memristor, which is used to solve the defects of the two-dimensional material memristor in the prior art, namely, large characteristic size and poor uniformity, and realize miniaturization of device size and high uniformity of device performance.

[0005] The present invention provides a method for preparing a nano-electrode of a two-dimensional material memristor, wherein the structure of the two-dimensional material memristor comprises, from bottom to top, a first substrate, a second substrate, a bottom contact electrode, an insulating layer, a two-dimensional material electrode layer, and a top contact electrode, wherein the second substrate is obtained by growing on the first substrate, and the method comprises the following steps: S1: spin coating a pre-prepared PMMA dilution on the second substrate, performing electron beam exposure of a first mask pattern on the second substrate according to a pre-designed contact electrode layout, and performing low-temperature development to form a patterned bottom contact electrode, wherein the size of the first mask pattern is nanometer-scale; S2: subjecting the patterned bottom contact electrode to a first physical vapor deposition, and then stripping and peeling to obtain a bottom contact electrode of nanometer size; S3: preparing an insulating layer on the second substrate on which the bottom contact electrode is prepared by atomic layer deposition; S4: etching the copper substrate of the two-dimensional material with the copper substrate and transferring the two-dimensional material to above the insulating layer; S5: performing patterning on the transferred two-dimensional material to obtain a patterned two-dimensional material electrode; S6: Spin-coating the PMMA dilution on the surface of the second substrate after the two-dimensional material is patterned, baking the solid glue, performing electron beam exposure of the second mask pattern, and performing low-temperature development to form a top contact electrode pattern; wherein the size of the second mask pattern is nanometer-level, and the second mask pattern and the patterned bottom contact electrode are arranged in a cross shape; S7: subjecting the top contact electrode pattern to a second physical vapor deposition, and then removing the adhesive and peeling off to obtain a top contact electrode.

[0006] According to the method for preparing nanoelectrodes of two-dimensional material memristors provided by the present invention, the first substrate is a silicon substrate, and the second substrate is a silicon dioxide substrate; the material of the bottom contact electrode includes metal palladium and gold; the material of the insulating layer includes hafnium oxide, tantalum oxide, and boron nitride; the material of the two-dimensional material electrode is graphene; and the material of the top contact electrode includes titanium nitride and silver.

[0007] According to the method for preparing nanoelectrodes of two-dimensional material memristors provided by the present invention, the thickness of the PMMA dilution solution is less than 100 nm; The preparation method of the PMMA diluent comprises: Select PMMA photoresist from the PMMA300.07.5 series; PMMA photoresist and anisole are mixed in a ratio of 2:1 to obtain a PMMA dilution solution, wherein the thickness of the dilution solution under this ratio is 70-75 nm.

[0008] According to the method for preparing nanoelectrodes of two-dimensional material memristors provided by the present invention, the design line sizes of the first mask pattern and the second mask pattern are 1nm, 5nm, 10nm, 15nm, 20nm, 25nm and 30nm respectively.

[0009] According to the method for preparing nano-electrodes of two-dimensional material memristors provided by the present invention, the method of preparing an insulating layer on the second substrate on which the bottom contact electrode is prepared by atomic layer deposition specifically includes: A 5-7nm hafnium oxide insulating layer is grown using atomic layer deposition.

[0010] According to the method for preparing nano-electrodes of two-dimensional material memristors provided by the present invention, the first physical vapor deposition is magnetron sputtering; The vacuum degree of the magnetron sputtering is lower than 1E-6 Torr, and the deposition rate is 1Å / s.

[0011] According to the method for preparing nano-electrodes of two-dimensional material memristors provided by the present invention, the method of preparing an insulating layer on the second substrate on which the bottom contact electrode is prepared by atomic layer deposition specifically includes: Atomic layer deposition is used to grow an 8-10nm hafnium oxide insulating layer.

[0012] According to the method for preparing nano-electrodes of two-dimensional material memristors provided by the present invention, the first physical vapor deposition is electron beam evaporation; The vacuum degree of the electron beam evaporation is lower than 1E-6 Torr, and the deposition rate is 1Å / s.

[0013] According to the method for preparing nanoelectrodes of two-dimensional material memristors provided by the present invention, the dose of the electron beam exposure is greater than 1000 mJ / cm 2 .

[0014] According to the method for preparing nano-electrodes of two-dimensional material memristors provided by the present invention, the developer for low-temperature development is a PMMA dilution solution stored in a refrigerated environment below 5°C.

[0015] According to the method for preparing nanoelectrodes of two-dimensional material memristors provided by the present invention, before spin coating the pre-prepared PMMA dilution on the second substrate, the method further comprises: forming alignment marks and bottom test electrodes on the second substrate; The specific process of making the alignment mark and the bottom test electrode includes: A layer of negative photoresist is spin-coated on the second substrate with coating parameters of 700r / 9s and 4000r / 40s, pre-baked at 150°C for 60s, exposed using a chrome mask, mid-baked at 100°C for 120s, developed, evaporated or sputtered 10nm of metal titanium and 30nm of metal palladium, and stripped using acetone to form alignment marks and bottom test electrodes.

[0016] According to the method for preparing the nano-electrode of the two-dimensional material memristor provided by the present invention, spin coating the pre-prepared PMMA dilution on the second substrate specifically comprises: A layer of the PMMA dilution solution was spin-coated on the second substrate and the alignment mark at the coating parameters of 700r / 9s and 3000r / 40s respectively, and baked at 170° C. for 5 minutes.

[0017] According to the method for preparing a nano-electrode of a two-dimensional material memristor provided by the present invention, etching the copper substrate of the two-dimensional material with a copper substrate specifically comprises: A 3% ammonium persulfate solution is prepared and allowed to stand for 24 hours, and a chemical vapor deposited single-layer two-dimensional material electrode with a copper substrate is placed in the ammonium persulfate solution after the standing time; After the copper substrate is etched clean, transfer the single-layer two-dimensional material electrode to deionized water and let it stand for more than 5 minutes, then transfer it to new deionized water and let it stand for more than 5 minutes, and repeat this five times.

[0018] According to the method for preparing nanoelectrodes of two-dimensional material memristors provided by the present invention, the second physical vapor deposition is magnetron sputtering; the vacuum degree of the magnetron sputtering is lower than 1E-6Torr, and the deposition rate is 1Å / s.

[0019] According to the method for preparing nano-electrodes of two-dimensional material memristors provided by the present invention, after preparing the top contact electrode, the method further comprises: preparing a top test electrode; The specific process of preparing the top test electrode includes: A layer of negative photoresist was spin-coated on the top contact electrode with coating parameters of 700r / 9s and 4000r / 40s, pre-baked at 150°C for 60s, exposed using a chrome mask, mid-baked at 100°C for 120s, developed, sputtered 10nm of metal titanium and 30nm of metal palladium, and peeled off with acetone to form a top test electrode.

[0020] The present invention also provides a nano-electrode of a two-dimensional material memristor, which is obtained by any of the above methods for preparing the nano-electrode of a two-dimensional material memristor.

[0021] The nano-electrode preparation method of the two-dimensional material memristor provided by the present invention comprises the following steps: S1: spin coating a pre-prepared PMMA dilution on the second substrate, performing electron beam exposure of a first mask pattern on the second substrate according to a pre-designed contact electrode layout, and performing low-temperature development to form a patterned bottom contact electrode, wherein the size of the first mask pattern is nanometer-scale; S2: subjecting the patterned bottom contact electrode to a first physical vapor deposition, and obtaining a nanometer-scale bottom contact electrode after degumming and peeling; S3: preparing an insulating layer on the second substrate on which the bottom contact electrode is prepared by using an atomic layer deposition method; S4: applying a copper substrate to the second substrate; The two-dimensional material is etched on a copper substrate and transferred to the top of the insulating layer; S5: the transferred two-dimensional material is patterned to obtain a patterned two-dimensional material electrode; S6: the PMMA dilution is spin-coated on the surface of the second substrate after the two-dimensional material is patterned, and after baking the solid glue, the second mask pattern is electron-beam exposed, and low-temperature development is performed to form a top contact electrode pattern; wherein the size of the second mask pattern is nanometer-scale, and the second mask pattern and the patterned bottom contact electrode are arranged in a cross shape; S7: the top contact electrode pattern is subjected to a second physical vapor deposition, and the top contact electrode is obtained after the glue is removed and peeled off. The bottom contact electrode and the top contact electrode of the two-dimensional material memristor in the present invention are both nanometer-scale in size, and the nanometer-scale memristor electrode is prepared by the electron beam exposure technology, diluting the PMMA solution to reduce the thickness of the photoresist, increasing the electron beam exposure dose, and low-temperature development. The technology of the present invention has low cost and simple preparation method, and is compatible with traditional semiconductor device preparation and photolithography processes. The nanometer-sized lines are used as electrodes in two-dimensional material memristors. On the one hand, they can cooperate with the two-dimensional materials to reduce the on-state current and realize low-power neuromorphic devices. On the other hand, they can greatly reduce the device size and promote high-density integration of neuromorphic devices and storage-computing integrated circuits. In addition, they can improve the uniformity of device performance within the array and have great development prospects in storage-computing integrated circuit and integrated circuit applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0023] Figure 1 It is a schematic flow chart of the method for preparing the nano-electrode of the two-dimensional material memristor provided by the present invention.

[0024] Figure 2 It is a schematic diagram of the structure of the two-dimensional material memristor provided by the present invention.

[0025] Figure 3 This is a top view of the structure of the two-dimensional material memristor based on nanoelectrodes provided by the present invention.

[0026] Figure 4 This is a transmission electron microscope photograph of a memristor with a characteristic size of 20 nm provided by the present invention. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0028] The present invention is described in detail below in conjunction with the accompanying drawings of the specification. The specific operating method in the method embodiment can also be applied to the device embodiment or the system embodiment. In the description of the present invention, unless otherwise specified, "at least one" includes one or more. "Multiple" refers to two or more. For example, at least one of A, B and C includes: A exists alone, B exists alone, A and B exist at the same time, A and C exist at the same time, B and C exist at the same time, and A, B and C exist at the same time. In the present invention, " / " means or, for example, A / B can mean A or B; "and / or" in this article is only a kind of association relationship that describes the associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone.

[0029] The present invention will be described in detail below in conjunction with specific implementation modes.

[0030] In some specific embodiments of the present invention, Figure 1 As shown, this solution provides a method for preparing a nano-electrode of a two-dimensional material memristor, wherein the structure of the two-dimensional material memristor includes, from bottom to top, a first substrate, a second substrate, a bottom contact electrode, an insulating layer, a two-dimensional material electrode layer, and a top contact electrode, wherein the second substrate is grown by growing the first substrate; Methods include: S1: spin coating a pre-prepared PMMA dilution on the second substrate, performing electron beam exposure of a first mask pattern on the second substrate according to a pre-designed contact electrode layout, and performing low-temperature development to form a patterned bottom contact electrode, wherein the size of the first mask pattern is nanometer-scale; S2: subjecting the patterned bottom contact electrode to a first physical vapor deposition, and then stripping and peeling to obtain a bottom contact electrode of nanometer size; S3: preparing an insulating layer on the second substrate on which the bottom contact electrode is prepared by atomic layer deposition; S4: etching the copper substrate of the two-dimensional material with the copper substrate and transferring the two-dimensional material to above the insulating layer; S5: performing patterning on the transferred two-dimensional material to obtain a patterned two-dimensional material electrode; S6: spin-coating the PMMA dilution on the surface of the second substrate after the two-dimensional material is patterned, baking the solid glue, performing electron beam exposure of the second mask pattern, and performing low-temperature development to form a top contact electrode pattern; wherein, the size of the second mask pattern is nanometer level, and the second mask pattern and the patterned bottom contact electrode are arranged in a cross shape. S7: subjecting the top contact electrode pattern to a second physical vapor deposition, and obtaining the top contact electrode after degumming and peeling.

[0031] It should be noted that the existing electrode preparation scheme for two-dimensional material memristors has a characteristic size of micrometers, which is different from silicon-based circuit integration. It is necessary to shrink the device size, reduce power consumption, and promote high-density integration of in-memory computing architectures. In addition, the uniformity of two-dimensional materials is poor, which limits the yield of devices in memory computing circuits.

[0032] Therefore, the present invention is based on the method for preparing nano-electrodes of two-dimensional material memristors, based on electron beam exposure technology, by diluting PMMA solution to reduce the thickness of photoresist, increasing electron beam exposure dose and low-temperature development method to prepare nano-scale memristor electrodes, and the bottom contact electrode and top contact electrode of the two-dimensional material memristor are both nano-scale in size. The preparation method of the nano-scale characteristic size electrode of the present invention is simple, easy to operate, and low in cost. It can be applied to two-dimensional material memristors to reduce the on-state current on the one hand, realize low-power neuromorphic devices, and on the other hand, greatly reduce the size of the device, and promote the high-density integration of neuromorphic devices and storage-computing integrated circuits.

[0033] In some specific embodiments of the present invention, a nano-electrode of a two-dimensional material memristor is also provided, which is obtained by any of the above methods for preparing a nano-electrode of a two-dimensional material memristor.

[0034] In some possible embodiments of the present invention, Figure 2 As shown, the structure of the two-dimensional material memristor is, from bottom to top, a silicon substrate 101 (first substrate), a silicon dioxide substrate 102 (second substrate), a bottom contact electrode 103, an insulating layer 104, a two-dimensional material 105, and a top contact electrode 106, wherein the silicon dioxide substrate 102 is obtained by growing on the silicon substrate 101.

[0035] On this basis, the present invention is described in detail through two specific embodiments.

[0036] Example 1, still for reference Figure 2 The first substrate is a silicon substrate 101, the second substrate is a silicon dioxide substrate 102; the material of the bottom contact electrode 103 is metal palladium; the material of the insulating layer 104 is hafnium oxide; the two-dimensional material 105 is graphene; and the material of the top contact electrode 106 includes titanium nitride.

[0037] A method for preparing a two-dimensional material memristor based on nanoelectrodes comprises the following steps: S101: Substrate hydrophilicity treatment: The silicon substrate 101 / silicon dioxide substrate 102 is treated with oxygen plasma; S102: making alignment marks and bottom test electrodes: spin-coating a layer of negative photoresist on the silicon substrate 101 / silicon dioxide substrate 102 at 700r / 9s and 4000r / 40s, pre-baking at 150°C for 60s, exposing using a chrome mask, mid-baking at 100°C for 120s, developing, evaporating or sputtering 10nm of metal titanium and 30nm of metal palladium, and stripping with acetone to form the designed alignment marks and bottom test electrodes; S103: preparing a PMMA diluent: using anisole as a diluent, diluting PMMA at a ratio of PMMA: anisole of 2:1 to prepare a PMMA diluent; S104: patterning small-size bottom contact electrodes: spin-coating a layer of PMMA diluted solution prepared in step S103 on the silicon substrate 101 / silicon dioxide substrate 102 with alignment marks prepared thereon at 700r / 9s and 3000r / 40s, baking at 170°C for 5min, and electron beam exposure, wherein the mask pattern sizes are 1nm, 5nm, 10nm, 15nm, 20nm, 25nm and 30nm, respectively, followed by low-temperature development; S105: Evaporation of bottom contact electrode: The sample patterned in step S104 is subjected to electron beam evaporation in a low vacuum environment to evaporate 5 nm of metal titanium and 30 nm of metal palladium, and the bottom contact electrode 103 with an actual size of 20 nm is obtained by debonding with acetone; S106: preparing an insulating layer 104: growing a 5-7 nm hafnium oxide insulating layer by atomic layer deposition; S107: Transferring two-dimensional material 105: Prepare a 3% ammonium persulfate solution and let it stand for one day, place the chemical vapor deposited graphene with a copper substrate in the standing ammonium persulfate solution, and wait until the copper substrate is etched clean, transfer the single-layer graphene to deionized water using a hydrophilic silicon wafer and let it stand for more than 5 minutes, repeat the above transfer five times, and transfer the graphene to the small-sized bottom contact electrode of the substrate after the hafnium oxide insulating layer substrate prepared in step S106 is hydrophilic treated; S108: Patterning graphene material: The sample obtained in step S107 is spin-coated with a layer of positive photoresist at 700r / 9s and 3000r / 60s, pre-baked at 100°C for 60s, exposed using a chrome mask, mid-baked at 100°C for 90s, developed, treated with oxygen plasma at a power of 150W and a gas flow of 150sccm for 7min, and debonded using acetone, thereby patterning the graphene material; S109: Preparation of small-sized top contact electrodes: A layer of PMMA diluted solution prepared in step S103 is spin-coated on the patterned graphene material prepared in step S108 at 700r / 9s and 3000r / 40s, baked at 170°C for 5min, and exposed by electron beam, wherein the mask pattern sizes are 1nm, 5nm, 10nm, 15nm, 20nm, 25nm and 30nm, respectively, and are in a cross shape with the small-sized bottom contact electrodes, such as Figure 3 As shown, post-low temperature development; S110: Evaporation of top contact electrode 106: The sample patterned in step S109 is subjected to magnetron sputtering in a low vacuum environment to sputter 36 nm of titanium nitride, and acetone is used for debonding to obtain a top contact electrode with an actual size equal to or less than 20 nm; S111: Prepare the top test electrode: Spin coat a layer of negative photoresist at 700r / 9s and 4000r / 40s on the sample obtained in step S110, pre-bake at 150°C for 60s, expose using a chrome mask, mid-bake at 100°C for 120s, develop, sputter 10nm of metal titanium and 30nm of metal palladium, use acetone to remove the glue and peel off to form the designed top test electrode, and obtain a two-dimensional material resistive resistor with electrode lines equal to or less than 20nm.

[0038] The scanning electron microscope image of the 20 nm line obtained in Example 1 is as follows: Figure 4 As shown in the two-dimensional material memristor prepared in this way, titanium nitride is used as the top contact electrode. When a positive voltage is applied to the top contact electrode, HfO is induced. 2 Oxygen ions migrate in the insulating layer, forming a large number of oxygen vacancy defect states, which accumulate in the entire insulating layer, and the memristor changes from a high resistance state to a low resistance state, which is the SET process; when a negative voltage is applied to the top contact electrode, the oxygen vacancies combine with the oxygen ions, the conductive channel breaks, and the device changes from a low resistance state to a high resistance state, which is the RESET process. The graphene in the memristor and the nanoscale top and bottom contact electrodes can reduce the amount of conductive channels, reduce the on-state current, and realize a low-power neuromorphic device.

[0039] Example 2, continue to refer to Figure 2, the first substrate is a silicon substrate 101; the second substrate is a silicon dioxide substrate 102; the material of the bottom contact electrode 103 is metal palladium; the material of the insulating layer 104 is hafnium oxide; the two-dimensional material 105 is graphene; and the material of the top contact electrode 106 is silver.

[0040] The method for preparing a two-dimensional material memristor based on nanoelectrodes comprises the following steps: S201 to S205 are the same as steps S101 to S105 in the first embodiment; that is: S201: Substrate hydrophilicity treatment: The silicon substrate 101 / silicon dioxide substrate 102 is treated with oxygen plasma; S202: making alignment marks and bottom test electrodes: spin-coating a layer of negative photoresist on a silicon substrate / silicon dioxide substrate at 700r / 9s and 4000r / 40s, pre-baking at 150°C for 60s, exposing using a chrome mask, mid-baking at 100°C for 120s, developing, evaporating or sputtering 10nm of metal titanium and 30nm of metal palladium, and stripping with acetone to form the designed alignment marks and bottom test electrodes; S203: preparing a PMMA diluent: using anisole as a diluent, diluting PMMA at a ratio of PMMA: anisole of 2:1 to prepare a PMMA diluent; S204: patterning small-size bottom contact electrodes: spin-coating a layer of PMMA diluted solution prepared in step S203 on the silicon substrate 101 / silicon dioxide substrate 102 with alignment marks prepared thereon at 700r / 9s and 3000r / 40s, baking at 170°C for 5min, and electron beam exposure, wherein the mask pattern sizes are 1nm, 5nm, 10nm, 15nm, 20nm, 25nm and 30nm, respectively, followed by low-temperature development; S205: Evaporation of bottom contact electrode: The sample patterned in step S204 is subjected to electron beam evaporation in a low vacuum environment to evaporate 5 nm of metal titanium and 30 nm of metal palladium, and the bottom contact electrode 103 with an actual size of 20 nm is obtained by debonding with acetone; S206: preparing the insulating layer 104: growing an 8-10 nm hafnium oxide insulating layer by atomic layer deposition; S207 to S209 are the same as steps S107 to S109 in the first embodiment; that is: S207: Transferring the two-dimensional material 105: Prepare a 3% ammonium persulfate solution and let it stand for one day, place the chemical vapor deposited graphene with a copper substrate in the standing ammonium persulfate solution, wait until the copper substrate is etched clean, use a hydrophilic silicon wafer to transfer the single-layer graphene to deionized water and let it stand for more than 5 minutes, repeat the above transfer five times, and after the substrate prepared in step S206 is hydrophilic, transfer the graphene to the top of the small-sized bottom contact electrode of the substrate; S208: Patterning graphene material: The sample obtained in step S207 is spin-coated with a layer of positive photoresist at 700r / 9s and 3000r / 60s, pre-baked at 100°C for 60s, exposed using a chrome mask, mid-baked at 100°C for 90s, developed, treated with oxygen plasma at a power of 150W and a gas flow of 150sccm for 7min, and debonded using acetone, thereby patterning the graphene material; S209: preparing a small-sized top contact electrode 106: spin coating a layer of PMMA diluted solution prepared in step S203 on the graphene material prepared in step S208 at 700r / 9s and 3000r / 40s, baking at 170°C for 5min, and electron beam exposure, wherein the mask pattern sizes are 1nm, 5nm, 10nm, 15nm, 20nm, 25nm and 30nm, respectively, and are in a cross shape with the small-sized bottom contact electrode, and then developing at low temperature; S210: Evaporation of top contact electrode 106: The sample patterned in step S209 is subjected to thermal evaporation in a low vacuum environment to evaporate 30 nm of metallic silver, and acetone is used to remove the glue to obtain a top contact electrode with an actual size of nanometer level; S211 is the same as step S111 in the first embodiment, that is: S211: Prepare the top test electrode: spin coat a layer of negative photoresist on the sample obtained in step S210 at 700r / 9s and 4000r / 40s, pre-bake at 150°C for 60s, expose using a chrome mask, mid-bake at 100°C for 120s, develop, sputter 10nm of metal titanium and 30nm of metal palladium, use acetone to remove the glue and peel off to form the designed top test electrode, and obtain a two-dimensional material resistive resistor with electrode lines equal to or less than 20nm.

[0041] Thus, a two-dimensional material memristor with electrode lines equal to or less than 20 nm is obtained.

[0042] The two-dimensional material memristor obtained in Example 2 has a top electrode material of silver. Silver atoms are oxidized to anions under the positive voltage of the top contact electrode and drift toward the bottom contact electrode, accumulating on the bottom contact electrode until it contacts the top contact electrode, forming a conductive filament, and converting to a resistance state, which is the SET process of the memristor. When a negative voltage is applied to the top contact electrode, the silver ions drift from the bottom contact electrode to the top contact electrode, which is the RESET process. This is the working process of the memristor described in Example 2. The insulating layer is generally made of HfO deposited by atomic layer deposition at 190°C. 2 The structure is relatively loose, making it easier for conductive filaments to form. The nanoscale top and bottom contact electrodes can reduce the number of conductive filaments, lower the on-state current, and realize low-power neuromorphic devices.

[0043] It is worth noting that the various process steps included in the present invention are prepared layer by layer on the second substrate, and each step of growth or coating is performed on the basis of the previous step.

[0044] The present invention provides a method for preparing nano-electrodes of two-dimensional material memristors, wherein the bottom contact electrode and the top contact electrode of the two-dimensional material memristor are both nano-sized, and the nano-sized memristor electrodes are prepared by electron beam exposure technology, diluting the PMMA solution to reduce the thickness of the photoresist, increasing the electron beam exposure dose, and low-temperature development. The present invention has low technical cost, simple preparation method, and is compatible with traditional semiconductor device preparation and photolithography processes; nano-sized lines are used as electrodes in two-dimensional material memristors, which can, on the one hand, cooperate with two-dimensional materials to reduce the on-state current and realize low-power neuromorphic devices, and on the other hand, can greatly reduce the device size, promote the high-density integration of neuromorphic devices and storage-computing integrated circuits, and in addition, can improve the uniformity of device performance in the array, and have great development prospects in storage-computing integrated circuit and integrated circuit applications.

[0045] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for preparing a nanoelectrode of a two-dimensional material memristor, wherein the structure of the two-dimensional material memristor comprises, from bottom to top: A first substrate, a second substrate, a bottom contact electrode, an insulating layer, a two-dimensional material electrode layer, and a top contact electrode, wherein the second substrate is obtained by growing on the first substrate, characterized in that the method comprises: S1: spin coating a pre-prepared PMMA dilution on the second substrate, performing electron beam exposure of a first mask pattern on the second substrate according to a pre-designed contact electrode layout, and performing low-temperature development to form a patterned bottom contact electrode, wherein the size of the first mask pattern is nanometer-scale; S2: subjecting the patterned bottom contact electrode to a first physical vapor deposition, and then stripping and peeling to obtain a bottom contact electrode of nanometer size; S3: preparing an insulating layer on the second substrate on which the bottom contact electrode is prepared by atomic layer deposition; S4: etching the copper substrate of the two-dimensional material with the copper substrate and transferring the two-dimensional material to above the insulating layer; S5: performing patterning on the transferred two-dimensional material to obtain a patterned two-dimensional material electrode; S6: Spin-coating the PMMA dilution on the surface of the second substrate after the two-dimensional material is patterned, baking the solid glue, performing electron beam exposure of the second mask pattern, and performing low-temperature development to form a top contact electrode pattern; wherein the size of the second mask pattern is nanometer-level, and the second mask pattern and the patterned bottom contact electrode are arranged in a cross shape; S7: subjecting the top contact electrode pattern to a second physical vapor deposition, and then removing the adhesive and peeling off to obtain a top contact electrode.

2. The method for preparing a nanoelectrode of a two-dimensional material memristor according to claim 1, characterized in that: The first substrate is a silicon substrate, and the second substrate is a silicon dioxide substrate; the material of the bottom contact electrode includes metal palladium and gold; the material of the insulating layer includes hafnium oxide, tantalum oxide, and boron nitride; the material of the two-dimensional material electrode is graphene; and the material of the top contact electrode includes titanium nitride and silver.

3. The method for preparing a nanoelectrode of a two-dimensional material memristor according to claim 1, characterized in that: The thickness of the PMMA dilution is less than 100 nm; The preparation method of the PMMA diluent comprises: Select PMMA photoresist from the PMMA300.07.5 series; PMMA photoresist and anisole are mixed in a ratio of 2:1 to obtain a PMMA dilution solution, wherein the thickness of the dilution solution under this ratio is 70-75 nm.

4. The method for preparing a nanoelectrode of a two-dimensional material memristor according to claim 1, characterized in that: The design line sizes of the first mask pattern and the second mask pattern are 1nm, 5nm, 10nm, 15nm, 20nm, 25nm and 30nm respectively.

5. The method for preparing a nanoelectrode of a two-dimensional material memristor according to claim 1, characterized in that: The step of preparing the insulating layer on the second substrate on which the bottom contact electrode is prepared by atomic layer deposition specifically includes: A 5-7nm hafnium oxide insulating layer is grown using atomic layer deposition.

6. The method for preparing a nanoelectrode of a two-dimensional material memristor according to claim 5, characterized in that: The first physical vapor deposition is magnetron sputtering; The vacuum degree of the magnetron sputtering is lower than 1E-6 Torr, and the deposition rate is 1Å / s.

7. The method for preparing a nanoelectrode of a two-dimensional material memristor according to claim 1, characterized in that: The step of preparing the insulating layer on the second substrate on which the bottom contact electrode is prepared by atomic layer deposition specifically includes: Atomic layer deposition is used to grow an 8-10nm hafnium oxide insulating layer.

8. The method for preparing a nanoelectrode of a two-dimensional material memristor according to claim 7, characterized in that: The first physical vapor deposition is electron beam evaporation; The vacuum degree of the electron beam evaporation is lower than 1E-6 Torr, and the deposition rate is 1Å / s.

9. The method for preparing a nanoelectrode of a two-dimensional material memristor according to claim 1, characterized in that: The dose of the electron beam exposure is greater than 1000 mJ / cm 2 .

10. The method for preparing a nanoelectrode of a two-dimensional material memristor according to claim 1, characterized in that: The developer for low temperature development is a PMMA dilution stored in a refrigerated environment below 5°C.

11. The method for preparing a nanoelectrode of a two-dimensional material memristor according to claim 1, characterized in that: Before spin coating the pre-prepared PMMA dilution on the second substrate, the method further comprises: forming alignment marks and bottom test electrodes on the second substrate; The specific process of making the alignment mark and the bottom test electrode includes: A layer of negative photoresist is spin-coated on the second substrate with coating parameters of 700r / 9s and 4000r / 40s, pre-baked at 150°C for 60s, exposed using a chrome mask, mid-baked at 100°C for 120s, developed, evaporated or sputtered 10nm of metal titanium and 30nm of metal palladium, and stripped using acetone to form alignment marks and bottom test electrodes.

12. The method for preparing a nanoelectrode of a two-dimensional material memristor according to claim 11, characterized in that: Spin coating the pre-prepared PMMA dilution on the second substrate, specifically comprising: A layer of the PMMA dilution solution was spin-coated on the second substrate with the alignment mark prepared thereon at the coating parameters of 700r / 9s and 3000r / 40s in sequence, and baked at 170° C. for 5 minutes.

13. The method for preparing nanoelectrodes of two-dimensional material memristors according to claim 1, characterized in that: The step of etching the copper substrate of the two-dimensional material with the copper substrate specifically comprises: A 3% ammonium persulfate solution is prepared and allowed to stand for 24 hours, and a chemical vapor deposited single-layer two-dimensional material electrode with a copper substrate is placed in the ammonium persulfate solution after the standing time; After the copper substrate is etched clean, transfer the single-layer two-dimensional material electrode to deionized water and let it stand for more than 5 minutes, then transfer it to new deionized water and let it stand for more than 5 minutes, and repeat this five times.

14. The method for preparing nanoelectrodes of two-dimensional material memristors according to claim 1, characterized in that: The second physical vapor deposition is magnetron sputtering; the vacuum degree of the magnetron sputtering is lower than 1E-6Torr, and the deposition rate is 1 Å / s.

15. The method for preparing nanoelectrodes of two-dimensional material memristors according to claim 1, characterized in that: After preparing the top contact electrode, the method further comprises: preparing a top test electrode; The specific process of preparing the top test electrode includes: A layer of negative photoresist was spin-coated on the top contact electrode with coating parameters of 700r / 9s and 4000r / 40s, pre-baked at 150°C for 60s, exposed using a chrome mask, mid-baked at 100°C for 120s, developed, sputtered 10nm of metal titanium and 30nm of metal palladium, and peeled off with acetone to form a top test electrode.

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