Processor and method for solving processor data conflict and low-power-consumption execution

Abstract

The invention discloses a processor and a method for solving processor data conflict and low-power-consumption execution. When instructions are dispatched, each long instruction is recorded into an OITF table item, and each long instruction is written back, the instruction is removed from the OITF table item; the long instruction which is dispatched but not written back is stored in the table item in the OITF; when each instruction is dispatched, the target information of the instruction is compared with the target information in each table item in the OITF so as to judge whether the instruction has a data conflict with a long instruction which is dispatched and not written back or not, when the data conflict is generated, an assembly line is blocked at a dispatching point, and after the data conflict is relieved, dispatching is continued, and in addition, the data conflict between the instruction and the long instruction is eliminated. And when the dispatched instruction is executed, data operation of different types of instructions is carried out through the shared data operation sub-module. The method can effectively solve the data conflict generated in the operation of the processor, and reduces the power consumption and area of the processor in the execution stage.

Description

Technical Field

[0001] The present invention belongs to the technical field of processors, and in particular relates to a processor and method for resolving processor data conflicts and low-power execution. Background Art

[0002] In the field of modern processor technology, the performance of the processor plays a vital role in the operating efficiency and function realization of the entire computer system. Among them, the decoding and execution stages are the key links in the processor instruction processing flow.

[0003] With the rapid development of information technology, the tasks handled by computer systems are becoming increasingly complex and diverse, and the requirements for processor performance are also increasing. The traditional processor decoding stage is prone to data risk when facing complex instruction sets and multiple data types and operation modes.

[0004] In traditional processor architectures and instruction execution flows, data hazards frequently occur. Data hazards mainly arise from data dependencies between instructions. When an instruction depends on the data generated by a previous instruction that has not yet been completed, a data conflict will occur. For example, in a pipeline processor, due to overlapping execution of instructions, if subsequent instructions are executed before the data is ready, incorrect data may be read, which will lead to incorrect instruction execution results and seriously affect the accuracy and reliability of the processor. Current methods for resolving data conflicts have certain limitations. Although some solutions can alleviate data hazards to a certain extent, they will introduce additional hardware overhead or time delays, reducing processor performance.

[0005] At the same time, with the widespread use of electronic devices, the demand for low power consumption has become increasingly prominent. Whether it is a mobile device, an IoT node, or other power-sensitive application scenarios, the power consumption of the processor has become a key factor restricting the device's battery life and efficiency. Traditional processor execution methods often ignore power consumption issues while pursuing high performance, resulting in a lot of energy waste. For example, in the execution process of some simple instructions, the same or even more energy may be consumed as complex instructions, which is extremely unfavorable for battery-powered devices. Moreover, when existing low-power technologies are combined with methods to solve data conflict problems, it is often difficult to achieve an ideal balance and cannot meet the needs of high performance and low power consumption at the same time.

[0006] Therefore, there is an urgent need for a new method and processor core that can effectively solve the processor data conflict problem and achieve low-power execution, so as to break through the limitations of existing technologies, improve the performance and energy efficiency of processors in different application scenarios, and meet the growing and complex demands of modern computer systems for processors. Summary of the invention

[0007] In order to solve the above problems existing in the prior art, the present invention provides a processor and method for resolving processor data conflicts and low-power execution.

[0008] The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0009] The present invention provides a processor for resolving processor data conflicts and low-power execution, comprising:

[0010] A decoder module, used for acquiring a current instruction and decoding the current instruction, and determining whether the current instruction is a common instruction or a long instruction;

[0011] The OITF module is used to determine whether the current instruction has a data conflict with the dispatched previous instruction according to the target information in the decoded current instruction and the target information currently stored in its own table entry, and if not, return a determination result indicating no conflict to the decoder module; if yes, continue to determine after a preset time until it is determined that the current instruction has no data conflict with the previous instruction, and return a determination result indicating no conflict to the decoder module; and when the current instruction is a long instruction, store the decoded current instruction in its own table entry, and delete a long instruction written back each time from its own table entry each time a long instruction is written back;

[0012] The decoder module is further configured to dispatch the decoded current instruction to the ALU module upon receiving the judgment result indicating no conflict;

[0013] The ALU module has a shared data operation submodule, which is used to process the decoded current instruction based on the shared data operation submodule to obtain a processing result.

[0014] The present invention provides a method for resolving processor data conflicts and low-power execution, which is applied to the above-mentioned processor, and the method comprises:

[0015] Obtaining a current instruction and decoding the current instruction, and determining whether the current instruction is a common instruction or a long instruction;

[0016] Determining whether the current instruction has data conflicts with the dispatched preceding instruction according to the target information in the decoded current instruction and the currently stored target information;

[0017] If not, and when the current instruction is a common instruction, dispatching the decoded current instruction;

[0018] If not, and when the current instruction is a long instruction, storing the decoded current instruction and dispatching the decoded current instruction;

[0019] If yes, continue to judge after a preset time until it is judged that there is no data conflict between the current instruction and the previous instruction, and when the current instruction is a common instruction, dispatch the decoded current instruction;

[0020] If yes, continue to judge after a preset time until it is judged that there is no data conflict between the current instruction and the previous instruction, and when the current instruction is a long instruction, store the decoded current instruction and dispatch the decoded current instruction;

[0021] Execute the decoded current instruction dispatched;

[0022] Each time a long instruction is written back, the stored long instruction is deleted.

[0023] Compared with the prior art, the present invention has the following beneficial effects:

[0024] When dispatching instructions, the present invention records each long instruction in the table entry of OITF when dispatching it, and removes the instruction from the table entry of OITF when writing back the instruction; therefore, the table entry in OITF stores the long instruction that has been dispatched but not yet written back; when dispatching each instruction, the target information of the instruction is compared with the target information in each table entry in OITF, so as to judge whether the instruction has a data conflict with the long instruction that has been dispatched and not yet written back, and when there is a data conflict in the processor, the processor blocks the pipeline at the dispatch point, and will continue to dispatch only after the data conflict is resolved, so that the data conflict generated during the operation of the processor can be effectively resolved, and the power consumption and area of ​​the processor execution stage can be reduced. In addition, the present invention can greatly reduce the repeated appearance of circuits such as adders, subtractors, and shift registers in different instruction execution modules by designing a shared data operator module, so as to reduce the circuit area of ​​the ALU module and effectively reduce the power consumption of the processor. That is to say, the present invention can not only effectively resolve data conflicts generated during processor operation and reduce power consumption and area during the processor execution phase, but also optimize processor performance. In addition, the processor has low power consumption, small area, and a method for resolving data conflicts has a simple structure and good engineering practicality.

[0025] The present invention will be further described in detail below with reference to the accompanying drawings and specific implementation methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a partial structural diagram of a processor for resolving processor data conflicts and low-power execution provided by an embodiment of the present invention;

[0027] Figure 2is a working principle diagram of the OITF module provided by an embodiment of the present invention;

[0028] Figure 3 These are all the long instructions in the RISC-V 32IM instruction set on which the processor provided by the embodiment of the present invention is based;

[0029] Figure 4 is a structural schematic diagram of an ALU module provided by an embodiment of the present invention;

[0030] Figure 5 It is a structural diagram of a SoC built based on the processor provided by the present invention according to an embodiment of the present invention. DETAILED DESCRIPTION

[0031] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0032] The embodiment of the present invention provides a processor for solving processor data conflicts and low-power execution, and the processor includes: a decoder module, an OITF (Outstanding Instructions Track FIFO) module and an ALU module. The decoder module is used to obtain and decode the current instruction, and to determine whether the current instruction is a common instruction or a long instruction. The OITF module is used to determine whether the current instruction has a data conflict with the dispatched previous instruction according to the target information in the decoded current instruction and the target information currently stored in its own table entry. If not, the judgment result representing no conflict is returned to the decoder module; if so, the judgment is continued after a preset time until it is determined that there is no data conflict between the current instruction and the previous instruction, and the judgment result representing no conflict is returned to the decoder module; and when the current instruction is a long instruction, the decoded current instruction is stored in its own table entry, and each time a long instruction is written back, a long instruction written back is deleted from its own table entry. The decoder module is also used to dispatch the decoded current instruction to the ALU module when receiving the judgment result representing no conflict. The ALU module has a shared data operation submodule, and the ALU module is used to process the decoded current instruction based on the shared data operation submodule to obtain a processing result.

[0033] For example, Figure 1 A schematic diagram of a part of the structure of a processor for resolving processor data conflicts and low-power execution provided by the present invention. Figure 1As shown, the processor includes multiple registers Regfile, a decoder module Decoder, an OITF module and an ALU module, ID represents a decoding stage, and EX represents an execution stage. In the decoding stage, the Decoder will decode each instruction it receives and determine whether the instruction is a normal instruction or a long instruction, and send the decoded instruction and the determination result of whether the instruction is a normal instruction or a long instruction to the OITF module. The OITF module will determine whether the decoded instruction has a data conflict with the dispatched predecessor instruction based on the target information in the decoded current instruction and the target information currently stored in its own table entry. If the decoded instruction does not have a data conflict with the dispatched predecessor instruction, the determination result indicating no conflict is returned to the Decoder, and the Decoder will dispatch the decoded instruction to the ALU module for processing. If the OITF module determines that the decoded instruction does not have a data conflict with the dispatched predecessor instruction and that the instruction is a long instruction, the OITF module will store the decoded instruction in one of its own table entries and return the determination result indicating no conflict to the Decoder, and the Decoder will dispatch the decoded instruction to the ALU module for processing. If the OITF module determines that the decoded instruction has a data conflict with the dispatched previous instruction, it will continue to judge after a preset time until it is determined that there is no data conflict between the decoded instruction and the previous instruction. After that, if the instruction is a long instruction, the OITF module will store the decoded instruction in one of its own table entries and return the judgment result indicating no conflict to the Decoder, and the Decoder will dispatch the decoded instruction to the ALU module for processing; if the instruction is a normal instruction, the OITF module will return the judgment result indicating no conflict to the Decoder, and the Decoder will dispatch the decoded instruction to the ALU module for processing. After that, the ALU module processes the dispatched decoded instruction based on the shared data operation submodule and sends the final execution result to other modules. In addition, each time a long instruction is written back to a Regfile, the OITF module will delete the long instruction written back from its own table entry based on a feedback message.

[0034] Exemplarily, each table entry in the OITF module can store a decoded long instruction, and each table entry is a group of first in first out (FIFO) registers. The depth of the FIFO register can be configured by calculating the maximum number of retained instructions according to the long instruction processing cycle corresponding to the different working main frequencies of the processor, that is, the maximum number of retained instructions can be calculated according to the long instruction processing cycle corresponding to the different working main frequencies of the processor to configure the number of table entries in the OITF module. Exemplarily, Figure 2The working principle diagram of the OITF module is as follows: Figure 2 As shown, the OITF module includes 4 index table entries for storing decoded long instructions. When receiving a decoded instruction, the OITF module compares the target information in the decoded instruction with the target information recorded in the four index table entries in turn to determine whether there is a data conflict between the decoded instruction and the long instructions recorded in the four index table entries. When there is no data conflict, the result is fed back to the decoder module so that the decoder dispatches the decoded instruction, and when the decoded instruction is a long instruction, the decoded instruction is stored. In addition, as Figure 4 As shown, when a long instruction is written back after each WB arbitration, the OITF module deletes the long instruction written back from the index table entry storing the long instruction written back, so that the long instructions that have not been written back are always stored in the OITF module.

[0035] In the present invention, ordinary instructions are single-cycle instructions, and refer to instructions that require one instruction cycle to complete instruction execution and delivery during the execution phase; long instructions are multi-cycle instructions, and refer to instructions that require multiple cycles to complete instruction execution and delivery during the execution phase.

[0036] Exemplarily, the design method proposed in the present invention can be based on the RISC-V instruction set architecture, and the processor structure design can be based on the RISC-V 32IM instruction subset. In some embodiments, the decoder module is also used to determine that the current instruction is a long instruction when it is determined that the current instruction is any one of the four types of instructions, namely, a Load type instruction, a Store type instruction, a multiplication type instruction, and a division type instruction according to partial decoding information in the decoded current instruction, and when it is determined that the current instruction does not belong to any one of the four types of instructions according to partial decoding information, the current instruction is determined to be a normal instruction. The reason why the present invention specially classifies instructions through the decoder is that there will be data correlation between instructions delivered in different cycles. It should be noted that the decoder module in the present invention decodes the current instruction in segments, and identifies whether the current instruction is a Load type instruction or a Store type instruction according to the opcode segment and func3 segment obtained by decoding, and identifies whether the current instruction is a multiplication type instruction or a division type instruction according to the opcode segment and func7 segment obtained by decoding. Exemplarily, Figure 3All long instructions in the RISC-V 32IM instruction set based on the processor of the present invention include Laod / Store type instructions and multiplication / division type instructions. For example, when each instruction is 32 bits, the decoder module decodes the 32-bit instruction in segments, and 0-6 bits in the instruction are decoded as the opcode segment, 7-11 bits are decoded as the rd result register index value, 12-14 bits are decoded as the func3 segment, 15-19 bits are decoded as the rs1 source register 1 index value, 20-24 bits are decoded as the rs2 source register 2 index value, and 25-31 bits are decoded as the func7 segment. The Load / Store instruction type is decoded by the opcode segment and the func3 segment; the multiplication / division instruction type is decoded by the opcode segment and the func7 segment.

[0037] In the present invention, the target information is the source register index value and the result register index value. Based on this, the OITF module is also used to compare the source register index value and the result register index value in the decoded current instruction with the source register index value and the result register index value currently stored in the table entry in the OITF module, and determine whether the current instruction has a data conflict with the previous instruction based on the comparison result. Specifically, when a source register index value in the decoded current instruction is equal to a result register index value currently stored in the table entry in the OITF module, it indicates that there is a data conflict between the current instruction and the previous instruction, and the data conflict type is RAW correlation; when the result register index value in the decoded current instruction is equal to other result register index values ​​currently stored in the table entry in the OITF module, it indicates that there is a data conflict between the current instruction and the previous instruction, and the data conflict type is WAW correlation.

[0038] Here, the occurrence of WAR (Write-After-Read) correlation is: the register group index value to be read when the prologue instruction is dispatched is the same as the register group index value to be written back when the subsequent instruction is delivered, and the subsequent instruction writes back the register group before the prologue instruction. Since the processor provided by the present invention dispatches instructions in sequence, the source operand of the register group has been read when the prologue instruction is dispatched. Therefore, the processor provided by the present invention does not have such data conflicts. The occurrence of RAW (Read-After-Write) correlation is: the register group index value to be written back when the prologue instruction is dispatched is the same as the register group index value to be read when the subsequent instruction is delivered, and the subsequent instruction reads the register group before the prologue instruction. When the prologue dispatched instruction is a long instruction, it takes multiple cycles to write back the register group, and RAW correlation may be generated when dispatching the subsequent instruction. The occurrence of WAW (Write-After-Write) correlation is: the register group index value to be written back when the prologue instruction is dispatched is the same as the register group index value to be written back when the subsequent instruction is delivered, and the subsequent instruction writes back the register group before the prologue instruction. When the preceding dispatched instruction is a long instruction, it takes multiple cycles to write back to the register group. When dispatching subsequent instructions, they may be written back to the same register group before the preceding instruction, resulting in WAW dependency.

[0039] The processor provided by the present invention records the source register index value and the result register index value of the instruction in a table entry of the OITF module each time a long instruction is dispatched, and removes the source register index value and the result register index value of the instruction in the table entry of the OITF each time a long instruction is written back during instruction dispatching. Therefore, the table entry in the OITF stores the register index information of the long instruction that has been dispatched but not yet written back. When dispatching each instruction, the source operand register index and the result register index of the instruction are compared with each table entry in the OITF to determine whether the instruction generates RAW and WAW correlations with the instruction that has been dispatched and not yet written back. If there is a data conflict caused by data correlation in the processor, the processor blocks the pipeline at the dispatch point, and will continue to dispatch only after the data conflict caused by the contact correlation is resolved. In this way, the data conflict generated during the operation of the processor can be effectively resolved, and the power consumption and area of ​​the processor execution stage can be reduced.

[0040] In the present invention, instructions are divided into two types, ordinary instructions and long instructions, in the decoding stage to facilitate the resolution of data conflicts, but in the execution stage of the decoded instructions, each decoded instruction is divided into five types, ordinary ALU instructions, Load / Store type instructions, branch and jump instructions, CSR read and write instructions, and multiplication / division type instructions; wherein ordinary ALU instructions are instructions other than the four types of instructions of Load / Store type instructions, branch and jump instructions, CSR read and write instructions, and multiplication / division type instructions. That is to say, for the ALU module, each decoded instruction belongs to one of the five types of instructions of ordinary ALU instructions, Load / Store type instructions, branch and jump instructions, CSR read and write instructions, and multiplication / division type instructions. Based on this, in some embodiments, the ALU module of the present invention includes: a plurality of submodules for processing different types of instructions, and a shared data calculation submodule, wherein the shared data calculation submodule is used to perform data calculation according to the request of some submodules in the plurality of submodules for processing different types of instructions, and return the calculation result. The shared data calculation submodule is used to perform data calculation types including: addition, subtraction, multiplication and division, etc.

[0041] For example, Figure 4 A structural diagram of the ALU module is shown in Figure 2. Figure 4As shown, the ALU module includes: an ordinary ALU submodule, an address generation submodule, a branch prediction analysis submodule, a CSR read-write control submodule, a multi-cycle multiplier and divider, and a shared data calculation submodule. The ordinary ALU submodule is used to generate a calculation request for the shared data calculation submodule according to the decoded ordinary ALU instruction, and send the calculation request to the shared data calculation submodule, and receive the calculation result returned by the shared data calculation submodule. The address generation submodule is used to generate a calculation request for the shared data calculation submodule according to the decoded Load type instruction or Store type instruction, and send the calculation request to the shared data calculation submodule, and receive the calculation result returned by the shared data calculation submodule. The branch prediction analysis submodule is used to generate a calculation request for the shared data calculation submodule according to the decoded branch and jump instructions, and send the calculation request to the shared data calculation submodule, and receive the calculation result returned by the shared data calculation submodule. The CSR read-write control submodule is used to execute the decoded CSR read-write instruction. The multi-cycle multiplier and divider is used to generate a calculation request for a shared data calculation submodule according to a decoded multiplication type instruction or a division type instruction, and send the calculation request to the shared data calculation submodule, and receive the calculation result returned by the shared data calculation submodule. In this way, the data calculation submodule is used as a data calculation submodule shared by an ordinary ALU submodule, an address generation submodule, a branch prediction analysis submodule, and a multi-cycle multiplier and divider, which can greatly reduce the repetition of circuits such as adders, subtractors, and shift registers in ordinary ALU submodules, address generation submodules, branch prediction analysis submodules, and multi-cycle multipliers and dividers, thereby reducing the circuit area of ​​the ALU module and effectively reducing the power consumption of the processor.

[0042] In the present invention, the main logic of the ordinary ALU submodule is to initiate an operation request to the shared data calculation submodule according to the ordinary ALU instruction, and retrieve the calculation result from the shared data calculation submodule, that is, to inform the shared data calculation submodule which data needs to perform which operation according to the ordinary ALU instruction currently to be executed, and obtain the calculation result from the shared data calculation submodule.

[0043] In the present invention, the address generation submodule is mainly responsible for generating the data required to generate the address of the Load or Store type instruction according to the Load or Store type instruction to be executed currently, and what operations need to be performed on these data to inform the shared data calculation submodule, and obtain the final generated address from the shared data calculation submodule.

[0044] In the present invention, the branch prediction parsing submodule is mainly used to parse the decoded branch and jump instructions to determine whether the branch and jump instructions need to perform an instruction jump, and when an instruction jump is required, generate the data required to generate the PC value of the instruction to be jumped and the type of operation required for these data, so as to inform the shared data calculation submodule and obtain the PC value of the instruction to be jumped from the shared data calculation submodule.

[0045] In the present invention, the CSR read-write control submodule is used to execute the decoded CSR read-write instructions. For example, the CSR read-write instructions may include csrrw, csrrs, csrrc, csrrwi, csrrsi and csrrci instructions.

[0046] In the present invention, the multi-cycle multiplier and divider generates data that need to be added each time according to the decoded multiplication type instruction, and sends these data and the operation type to be performed to the shared data calculation submodule, and obtains the calculation result each time from the shared data calculation submodule. Through the cooperative operation of the multi-cycle multiplier and divider and the shared data calculation submodule, it is possible to use the Booth coding algorithm to calculate the partial product, and then use the iterative method to use the adder to accumulate the partial product in each cycle, and obtain the final product after multiple cycles of iteration. The multi-cycle multiplier and divider generates data that need to be added and / or subtracted each time according to the decoded division type instruction, and sends these data and the operation type to be performed to the shared data calculation submodule, and obtains the calculation result each time from the shared data calculation submodule. Through the cooperative operation of the multi-cycle multiplier and divider and the shared data calculation submodule, it is possible to use the commonly used addition and subtraction alternation method for signed integer division, and use the iterative method to use the adder to obtain the partial remainder in each cycle, and obtain the final quotient value and remainder value after multiple cycles of iteration. Obviously, since both the multi-cycle multiplier and the multi-cycle divider need to use an adder as the main operation path and use a set of registers to save partial products or partial remainders, the two can reuse resources on the shared data calculation submodule to save area.

[0047] In the present invention, the shared data calculation submodule may include a reusable shifter, a reusable XOR logic gate, a reusable adder and a shared register.

[0048] It should be noted that the processor provided by the present invention can be used in any suitable scenario. For example, the processor provided by the present invention can be used to build a SoC. Figure 5 This is a schematic diagram of the structure of a SoC built based on the processor provided by the present invention. Figure 5 As shown, the SoC includes: a processor provided by the present invention ( Figure 5The system memory bus is called the processor core in the system memory bus, bus devices, platform-level interrupt controller (PLIC) with interrupt exception handling function, core local interrupt controller (CLINT), as well as memory devices ROM and FLASH mounted on the system memory bus, and general peripheral interfaces (UART, I2C, GPIO, SPI) connected to the bus devices. In order to alleviate the speed difference between the processor accessing data and instructions from the memory ROM and FLASH through the system memory bus, the processor core uses a tightly coupled architecture cache ITCM (Instruction Tightly Coupled Memory, ITCM) to cache instructions and DTCM (Data Tightly Coupled Memory, DTCM) to cache data. ITCM and DTCM are implemented by static random access memory (SRAM) storage devices.

[0049] The present invention also provides a method for resolving processor data conflicts and low-power execution, which is executed by the above-mentioned processor and includes:

[0050] S101, obtaining and decoding the current instruction, and determining whether the current instruction is a common instruction or a long instruction.

[0051] S102: Determine whether the current instruction has data conflict with the dispatched previous instruction based on the target information in the decoded current instruction and the currently stored target information.

[0052] S1031. If not, and the current instruction is a common instruction, dispatch the decoded current instruction.

[0053] S1032: If not, and when the current instruction is a long instruction, store the decoded current instruction and dispatch the decoded current instruction.

[0054] S1033, if yes, continue to judge after the preset time until it is determined that there is no data conflict between the current instruction and the previous instruction, and when the current instruction is a common instruction, dispatch the decoded current instruction.

[0055] S1034, if yes, continue to judge after the preset time until it is determined that there is no data conflict between the current instruction and the previous instruction, and when the current instruction is a long instruction, store the decoded current instruction and dispatch the decoded current instruction.

[0056] S104, executing the decoded current instruction dispatched.

[0057] S105. Each time a long instruction is written back, the stored long instruction is deleted.

[0058] It should be noted that step S105 is not executed after step S104, but during the execution of other steps, once the situation in step S105 occurs, step S105 can be executed.

[0059] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0060] In the specification, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality of components. Certain measures are recorded in different embodiments, but this does not mean that these measures cannot be combined to produce good effects.

[0061] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A processor for resolving processor data conflicts and low-power execution, characterized in that: include: A decoder module, used for acquiring a current instruction and decoding the current instruction, and determining whether the current instruction is a common instruction or a long instruction; The OITF module is used to determine whether the current instruction has a data conflict with the dispatched previous instruction according to the target information in the decoded current instruction and the target information currently stored in its own table entry, and if not, return a determination result indicating no conflict to the decoder module; if yes, continue to determine after a preset time until it is determined that the current instruction has no data conflict with the previous instruction, and return a determination result indicating no conflict to the decoder module; and when the current instruction is a long instruction, store the decoded current instruction in its own table entry, and delete a long instruction written back each time from its own table entry each time a long instruction is written back; The decoder module is further configured to dispatch the decoded current instruction to the ALU module upon receiving the judgment result indicating no conflict; The ALU module has a shared data operation submodule, which is used to process the decoded current instruction based on the shared data operation submodule to obtain a processing result.

2. The processor for resolving processor data conflicts and executing with low power consumption according to claim 1, characterized in that: The ordinary instruction is a single-cycle instruction, and refers to an instruction that requires one instruction cycle to complete the execution and delivery of the instruction in the execution stage; the long instruction is a multi-cycle instruction, and refers to an instruction that requires multiple cycles to complete the execution and delivery of the instruction in the execution stage.

3. The processor for resolving processor data conflicts and executing with low power consumption according to claim 1, characterized in that: The decoder module is also used to determine that the current instruction is a long instruction when it is determined that the current instruction is any one of the four types of instructions, namely, a Load type instruction, a Store type instruction, a multiplication type instruction and a division type instruction according to part of the decoding information in the decoded current instruction, and to determine that the current instruction is a normal instruction when it is determined that the current instruction does not belong to any one of the four types of instructions according to the part of the decoding information.

4. The processor for resolving processor data conflicts and executing with low power consumption according to claim 3, characterized in that: The decoder module is also used to decode the current instruction in segments, and identify whether the current instruction is a Load type instruction or a Store type instruction based on the opcode segment and func3 segment obtained by decoding, and identify whether the current instruction is a multiplication type instruction or a division type instruction based on the opcode segment and func7 segment obtained by decoding.

5. The processor for resolving processor data conflicts and executing with low power consumption according to claim 1, characterized in that: The target information is a source register index value and a result register index value; The OITF module is also used to compare the source register index value and the result register index value in the decoded current instruction with the source register index value and the result register index value currently stored in the table entry in the OITF module, and determine whether the current instruction has a data conflict with the previous instruction based on the comparison result.

6. The processor for resolving processor data conflicts and executing with low power consumption according to claim 5, characterized in that: The OITF module is also used for, when a source register index value in the decoded current instruction is equal to a result register index value currently stored in the table entry in the OITF module, it indicates that there is a data conflict between the current instruction and the previous instruction, and the data conflict type is RAW correlation; when the result register index value in the decoded current instruction is equal to the result register index value currently stored in the table entry in the OITF module, it indicates that there is a data conflict between the current instruction and the previous instruction, and the data conflict type is WAW correlation.

7. The processor for resolving processor data conflicts and executing with low power consumption according to claim 1, characterized in that: The ALU module includes: multiple sub-modules for processing different types of instructions, and a shared data calculation sub-module, wherein the shared data calculation sub-module is used to perform data calculation according to the requests of some sub-modules among the multiple sub-modules for processing different types of instructions, and return the calculation results.

8. The processor for resolving processor data conflicts and executing with low power consumption according to claim 7, characterized in that: For the ALU module, the decoded current instruction belongs to one of the five types of instructions: ordinary ALU instruction, Load / Store type instruction, branch and jump instruction, CSR read and write instruction, and multiplication / division type instruction. The ordinary ALU instruction is an instruction other than the four types of instructions: Load / Store type instruction, branch and jump instruction, CSR read and write instruction, and multiplication / division type instruction. The shared data calculation submodule is used to perform data calculation types including: addition, subtraction, multiplication and division; The multiple sub-modules for processing different types of instructions include: The common ALU submodule is used to generate a calculation request for the shared data calculation submodule according to the decoded common ALU instruction, send the calculation request to the shared data calculation submodule, and receive the calculation result returned by the shared data calculation submodule; An address generation submodule, used to generate a calculation request for the shared data calculation submodule according to the decoded Load type instruction or Store type instruction, and send the calculation request to the shared data calculation submodule, and receive the calculation result returned by the shared data calculation submodule; A branch prediction parsing submodule, used to generate a calculation request for the shared data calculation submodule according to the decoded branch and jump instructions, send the calculation request to the shared data calculation submodule, and receive the calculation result returned by the shared data calculation submodule; CSR read and write control submodule, used to execute decoded CSR read and write instructions; A multi-cycle multiplier and divider is used to generate a calculation request for the shared data calculation submodule according to the decoded multiplication type instruction or division type instruction, send the calculation request to the shared data calculation submodule, and receive the calculation result returned by the shared data calculation submodule.

9. The processor for resolving processor data conflicts and executing with low power consumption according to claim 1, characterized in that: Each table entry in the OITF module is used to store a decoded long instruction.

10. A method for resolving processor data conflicts and low-power execution, characterized in that: Applied to the processor according to any one of claims 1 to 9, the method comprising: Obtaining a current instruction and decoding the current instruction, and determining whether the current instruction is a common instruction or a long instruction; Determining whether the current instruction has data conflicts with the dispatched preceding instruction according to the target information in the decoded current instruction and the currently stored target information; If not, and when the current instruction is a common instruction, dispatching the decoded current instruction; If not, and when the current instruction is a long instruction, storing the decoded current instruction and dispatching the decoded current instruction; If yes, continue to judge after a preset time until it is judged that there is no data conflict between the current instruction and the previous instruction, and when the current instruction is a common instruction, dispatch the decoded current instruction; If yes, continue to judge after a preset time until it is judged that there is no data conflict between the current instruction and the previous instruction, and when the current instruction is a long instruction, store the decoded current instruction and dispatch the decoded current instruction; Execute the decoded current instruction dispatched; Each time a long instruction is written back, the stored long instruction is deleted.

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