Chip packaging structure, preparation method and electronic equipment

Abstract

The invention discloses a chip packaging structure, a preparation method and electronic equipment, and the chip packaging structure comprises a first substrate which is provided with a plurality of first pins; the electric supporting piece is arranged on the first substrate, and the electric supporting piece is electrically connected with the first pin; the second substrate and the first substrate are arranged in parallel in a spaced mode, the first substrate and the second substrate are connected in a supported mode through an electric supporting piece, a plurality of second pins are arranged on the second substrate, part of the second pins are electrically connected with the electric supporting piece, and the other part of the second pins are used for being led out to be connected with external components; and the plastic package part is used for respectively carrying out plastic package on the two opposite sides of the first substrate so as to form the chip package structure. One-time plastic packaging can be carried out on the two faces of the first substrate, overall plastic packaging of the chip packaging structure is achieved, two-time plastic packaging does not need to be carried out on the two faces of the first substrate, the plastic packaging efficiency is high, two sets of plastic packaging molds do not need to be used, and the cost is reduced.

Description

Technical Field

[0001] The present invention relates to the field of chip packaging technology, and more specifically, to a chip packaging structure, a preparation method and an electronic device. Background Art

[0002] The traditional double-sided plastic sealing process requires that the product be sealed on one side before the other side. The disadvantage of the traditional method is that both sides of the product need to be sealed twice, which is inefficient. In addition, the second side requires a special process to lead out the circuit, and two sets of different molds are required for the two plastic sealings, which is costly. Summary of the invention

[0003] An object of the present invention is to provide a new technical solution for a chip packaging structure, a preparation method and an electronic device, which can at least solve the problems of the prior art that double-sided plastic packaging requires two plastic packaging steps and a special process is required to lead out the circuit.

[0004] According to a first aspect of the present invention, a chip packaging structure is provided, comprising: a first substrate, on which a plurality of first pins are provided; an electric support member, which is provided on the first substrate and is electrically connected to the first pins; a second substrate, which is spaced apart from and arranged in parallel with the first substrate, and the first substrate and the second substrate are supported and connected by the electric support member, and a plurality of second pins are provided on the second substrate, wherein some of the second pins are electrically connected to the electric support member to form an electrical interconnection between the first substrate and the second substrate, and the remaining part of the second pins are used for leading out and connecting external components; and a plastic sealing member, which is used to respectively seal the opposite sides of the first substrate to form the chip packaging structure.

[0005] Optionally, two ends of the electric support are respectively bonded or soldered to the first substrate and the second substrate.

[0006] Optionally, the electrical support is a solder ball.

[0007] Optionally, the electric support is a resistive connecting member.

[0008] Optionally, the first substrate and the second substrate are circuit boards respectively.

[0009] Optionally, a first chip is disposed on a first side of the first substrate, and a second chip is disposed on a second side of the first substrate. The first side and the second side of the first substrate are opposite sides in a thickness direction of the first substrate.

[0010] Optionally, a portion of the plastic encapsulation member is filled between the first substrate and the second substrate, and another portion of the plastic encapsulation member is filled on a side of the first substrate facing away from the second substrate.

[0011] A second aspect of the present invention provides a method for preparing a chip packaging structure, which is used to prepare the chip packaging structure described in the above embodiment, and the preparation method comprises:

[0012] Providing a first substrate having a first pin, mounting an electric support member on a side of the first substrate having the first pin to form a first structural member;

[0013] Stacking the first structural component on a second substrate having a second pin;

[0014] A plastic packaging member is filled on a side of the first substrate facing away from the second substrate and between the first substrate and the second substrate to obtain the chip packaging structure.

[0015] Optionally, the method for preparing the chip packaging structure further includes:

[0016] Mounting a first chip on the first side of the first substrate;

[0017] A second chip is mounted on the second side of the first substrate, wherein the first side and the second side of the first substrate are opposite sides in the thickness direction of the first substrate.

[0018] A third aspect of the present invention provides an electronic device, comprising the chip packaging structure described in the above embodiment.

[0019] In the chip packaging structure of the present invention, the first substrate and the second substrate are respectively provided with the first pin and the second pin, and the first substrate and the second substrate are interconnected by providing the electric support member on the first pin of the first substrate. At the same time, the plastic sealing member can perform plastic sealing on both sides of the first substrate once, thereby achieving overall plastic sealing of the chip packaging structure, without the need to perform plastic sealing on both sides of the first substrate twice, with high plastic sealing efficiency, and without the need to use two sets of plastic sealing molds, thereby reducing costs.

[0020] Further features and advantages of the present invention will become apparent from the following detailed description of exemplary embodiments of the present invention with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0022] Figure 1 is a schematic structural diagram of a chip packaging structure according to an embodiment of the present invention;

[0023] Figure 2 is a flow chart of a method for preparing a chip packaging structure according to an embodiment of the present invention.

[0024] Reference numerals:

[0025] A first substrate 10; a first pin 11;

[0026] Electrical support 20;

[0027] A second substrate 30; a second pin 31;

[0028] Plastic sealing part 40;

[0029] A first chip 51 and a second chip 52 . DETAILED DESCRIPTION

[0030] Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangement of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present invention unless otherwise specifically stated.

[0031] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.

[0032] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.

[0033] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0034] It should be noted that like reference numerals and letters refer to similar items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0035] In the specification and claims of the present invention, if the term "first" or "second" is involved, it may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "plurality" means two or more. In addition, "and / or" in the specification and claims means at least one of the connected objects, and the character " / " generally means that the related objects are in an "or" relationship.

[0036] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, which are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation to the present invention.

[0037] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installation", "connection" and "connection" involved should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0038] The chip packaging structure according to the embodiment of the present invention is described in detail below with reference to the accompanying drawings.

[0039] like Figure 1 and Figure 2 As shown, the chip packaging structure according to the embodiment of the present invention includes a first substrate 10 , an electric support member 20 , a second substrate 30 and a plastic package 40 .

[0040] Specifically, a plurality of first pins 11 are provided on the first substrate 10. An electric support 20 is provided on the first substrate 10, and the electric support 20 is electrically connected to the first pins 11. The second substrate 30 is spaced apart from the first substrate 10 and arranged in parallel, and the first substrate 10 and the second substrate 30 are supported and connected by the electric support 20. A plurality of second pins 31 are provided on the second substrate 30, wherein some of the second pins 31 are electrically connected to the electric support 20, so that the first substrate 10 and the second substrate 30 are electrically interconnected, and the remaining second pins 31 are used to lead out and connect external components. The plastic package 40 is used to plastic package the opposite sides of the first substrate 10 respectively to form a chip packaging structure.

[0041] In other words, if Figure 1 and Figure 2As shown, the chip packaging structure according to the embodiment of the present invention is mainly composed of a first substrate 10, an electric support 20, a second substrate 30 and a plastic package 40. Among them, a plurality of first pins 11 are arranged on the first substrate 10. The electric support 20 is arranged on the first substrate 10, and the electric support 20 is arranged at the position of the first pin 11 and is electrically connected to the first pin 11. The second substrate 30 is spaced apart from the first substrate 10 and arranged in parallel, and the first substrate 10 and the second substrate 30 are supported and connected by the electric support 20 to achieve the interconnection between the first substrate 10 and the second substrate 30. A plurality of second pins 31 are arranged on the second substrate 30, wherein the second pins 31 of the second substrate 30 facing the surface of the first substrate 10 are electrically connected to the electric support 20 to ensure that the first substrate 10 and the second substrate 30 are electrically interconnected. The second pins 31 on the surface of the second substrate 30 facing away from the first substrate 10 are used to lead out and connect external components. The plastic package 40 is used to plastic-seal the opposite sides of the first substrate 10 respectively to form an overall plastic package for the chip packaging structure. The plastic sealing member 40 can perform plastic sealing on both sides of the first substrate 10 once to achieve overall plastic sealing of the chip packaging structure, without the need to perform plastic sealing twice on both sides of the first substrate 10 . The plastic sealing efficiency is high, and there is no need to use two sets of plastic sealing molds, thereby reducing costs.

[0042] The traditional double-sided plastic encapsulation process requires that after the plastic encapsulation of one side of the product is completed, the plastic encapsulation on the other side is continued. The disadvantage of the traditional method is that the traditional method requires two sides to be plastic encapsulated twice, which is inefficient, and the second side requires a special process (such as Selectmold) to lead out the circuit. Two sets of different molds are required for two plastic encapsulations, which is costly. The present invention can mount the product that needs double-sided plastic encapsulation on the second substrate 30, perform overall plastic encapsulation on the chip packaging structure, and the first substrate 10 and the second substrate 30 connected to the electric support 20 are respectively provided with a first pin 11 and a second pin 31, which can lead out the circuit of the package body. The advantage of the present invention is that the first substrate 10 is welded by the electric support 20 and the one-time plastic encapsulation method is adopted, which meets the technical requirements of double-sided plastic encapsulation, is efficient, and saves mold costs.

[0043] Therefore, according to the chip packaging structure of the embodiment of the present invention, the first substrate 10 and the second substrate 30 are respectively provided with the first pin 11 and the second pin 31, and the first substrate 10 and the second substrate 30 are interconnected by providing the electric support 20 on the first pin 11 of the first substrate 10. At the same time, the plastic sealing member 40 can perform plastic sealing on both sides of the first substrate 10 once, so as to realize the overall plastic sealing of the chip packaging structure, without the need to perform plastic sealing on both sides of the first substrate 10 twice, and the plastic sealing efficiency is high, and there is no need to use two sets of plastic sealing molds, thereby reducing costs.

[0044] According to an embodiment of the present invention, two ends of the electric support member 20 are respectively connected to the first substrate 10 and the second substrate 30 by bonding or soldering.

[0045] That is to say, Figure 1 As shown, the two ends of the electric support 20 can be respectively connected to the first substrate 10 and the second substrate 30 by solder paste bonding, and after bonding, they can be further fixed by soldering to achieve stable interconnection between the first substrate 10 and the second substrate 30. At the same time, the second pin 31 on the second substrate 30 is used to facilitate the one-time plastic sealing of both sides of the first substrate 10. After using a set of molds for plastic sealing, the second side does not need to replace a different mold (such as select mold, the purpose is to allow the package body circuit to be led out), which is low in cost and high in efficiency. The present invention pre-mounts the electric support 20 and mounts the plastic sealing structure on the first substrate 10, and the plastic sealing effect on both sides can be achieved by one-time plastic sealing, which is low in cost and high in efficiency.

[0046] According to one embodiment of the present invention, Figure 1 and Figure 2 As shown, the electric support 20 is a solder ball. In other words, the electric support 20 can be a solder ball, and by planting the solder ball, the product that needs double-sided plastic sealing is mounted on the first substrate 10, the chip packaging structure is plastic sealed as a whole, and the second substrate 30 connected to the solder ball is provided with a second pin 31, which can lead out the package body circuit. The present invention meets the technical requirements of double-sided plastic sealing by soldering the substrate with solder balls and adopting a one-time plastic sealing method, which is highly efficient and saves mold costs.

[0047] According to one embodiment of the present invention, the electric support 20 is a resistive connection member.

[0048] That is to say, the electric support 20 can also adopt a resistive connector. The two ends of the resistive connector can be respectively connected to the first substrate 10 and the second substrate 30 by solder paste bonding, and after bonding, they can be further fixed by soldering to achieve stable interconnection between the first substrate 10 and the second substrate 30. By using a resistive connector as a transmission medium between the first substrate 10 and the second substrate 30 for interconnection, the first substrate 10 and the second substrate 30 are interconnected together. The resistive connector does not take up too much space in the horizontal direction, which is conducive to increasing the interconnection density of the chip stacking package, while saving the ball planting process, the process is simple, and the cost is low.

[0049] According to an embodiment of the present invention, the first substrate 10 and the second substrate 30 are circuit boards respectively.

[0050] In other words, the first substrate 10 and the second substrate 30 can be circuit boards, which can be directly used as substrates for the chip packaging structure without the need for additional substrates, thereby reducing the overall size and material of the chip packaging structure, which is conducive to the miniaturization and lightweight design of the chip packaging structure.

[0051] According to an embodiment of the present invention, a first chip 51 is disposed on a first side of the first substrate 10 , and a second chip 52 is disposed on a second side of the first substrate 10 . The first side and the second side of the first substrate 10 are opposite sides in the thickness direction of the first substrate 10 .

[0052] That is to say, Figure 1 and Figure 2 As shown, a first chip 51 may be disposed on the first side of the first substrate 10, and the first chip 51 may be a logic chip. A second chip 52 may be disposed on the second side of the first substrate 10, and the second chip 52 may be a memory chip. The first side and the second side of the first substrate 10 are opposite sides in the thickness direction of the first substrate 10. The types and quantities of the first chip 51 and the second chip 52 may be specifically set according to actual needs, and will not be described in detail in the present invention.

[0053] According to an embodiment of the present invention, a portion of the molding member 40 is filled between the first substrate 10 and the second substrate 30 , and another portion of the molding member 40 is filled on a side of the first substrate facing away from the second substrate 30 .

[0054] That is to say, Figure 1 and Figure 2 As shown, a part of the plastic seal 40 can be filled between the first substrate 10 and the second substrate 30, and another part of the plastic seal 40 can be filled on the side of the first substrate facing away from the second substrate 30. The present invention mounts the product requiring double-sided plastic sealing on the first substrate 10 by adopting the method of solder ball planting, and plastic seals the chip packaging structure as a whole, and the second substrate 30 connected to the solder ball is provided with a second pin 31, which can lead out the package body circuit. The present invention meets the technical requirements of double-sided plastic sealing by solder ball welding the substrate and adopting a one-time plastic sealing method, which is highly efficient and saves mold costs.

[0055] In summary, according to the chip packaging structure of the embodiment of the present invention, the first substrate 10 and the second substrate 30 are respectively provided with the first pin 11 and the second pin 31, and the first substrate 10 and the second substrate 30 are interconnected by providing the electric support 20 on the first pin 11 of the first substrate 10. At the same time, the plastic sealing member 40 can perform plastic sealing on both sides of the first substrate 10 once, so as to achieve the overall plastic sealing of the chip packaging structure, without the need to perform plastic sealing on both sides of the first substrate 10 twice, and the plastic sealing efficiency is high, and there is no need to use two sets of plastic sealing molds, thereby reducing costs.

[0056] Of course, for those skilled in the art, other structures of the chip packaging structure and its working principles are understandable and achievable, and will not be described in detail in the present invention.

[0057] According to a second aspect of the present invention, Figure 2As shown, a method for preparing a chip packaging structure is provided, which is used to prepare the chip packaging structure of the above embodiment, and the preparation method comprises:

[0058] Providing a first substrate 10 having a first pin 11, mounting an electric support member 20 on a side of the first substrate 10 having the first pin 11 to form a first structural member;

[0059] The first structural member is stacked on a second substrate 30 having a second pin 31;

[0060] A plastic package 40 is filled on a side of the first substrate 10 facing away from the second substrate 30 and between the first substrate 10 and the second substrate 30 to obtain a chip packaging structure.

[0061] That is to say, the method for preparing a chip packaging structure according to the present invention is mainly used to prepare the chip packaging structure of the above embodiment. Figure 2 In the method for preparing a chip packaging structure, first, a first substrate 10 having a first pin 11 may be provided, and an electric support member 20 may be mounted on a side of the first substrate 10 having the first pin 11 to form a first structural member. Then, the first structural member may be stacked or welded on a second substrate 30 having a second pin 31. Finally, a plastic sealing member 40 may be filled at one time on a side of the first substrate 10 facing away from the second substrate 30 and between the first substrate 10 and the second substrate 30 to obtain a chip packaging structure.

[0062] The present invention mounts the product requiring double-sided plastic packaging on the first substrate 10 by adopting the solder ball planting method, plastic packaging the chip packaging structure as a whole, and the second substrate 30 connected to the solder ball is provided with a second pin 31, which can lead out the package body circuit. The present invention uses the solder ball to solder the substrate and adopts the one-time plastic packaging method, which meets the technical requirements of double-sided plastic packaging, has high efficiency, and saves mold costs.

[0063] According to one embodiment of the present invention, the method for preparing a chip packaging structure further includes:

[0064] Mounting a first chip 51 on a first side of the first substrate 10;

[0065] The second chip 52 is mounted on the second side of the first substrate 10 , wherein the first side and the second side of the first substrate 10 are two opposite sides in the thickness direction of the first substrate 10 .

[0066] In other words, Figure 2As shown, in the preparation method of the chip packaging structure of the present invention, the first chip 51 can be pre-mounted on the first side of the first substrate 10. Then, the second chip 52 is mounted on the second side of the first substrate 10, wherein the first side and the second side of the first substrate 10 are opposite sides in the thickness direction of the first substrate 10. The plastic sealing member 40 can perform plastic sealing on both sides of the first substrate 10 once, thereby realizing the overall plastic sealing of the chip packaging structure, without the need to perform plastic sealing on both sides of the first substrate 10 twice, with high plastic sealing efficiency, and without the need to use two sets of plastic sealing molds, thereby reducing costs.

[0067] According to the second aspect of the present invention, an electronic device is provided, comprising the chip packaging structure in the above embodiment. Since the chip packaging structure according to the embodiment of the present invention has the above technical effects, the electronic device according to the embodiment of the present invention should also have the corresponding technical effects, that is, the electronic device of the present invention adopts the chip packaging structure in the above embodiment, and interconnects the first substrate 10 and the second substrate 30 by connecting the electric support 20. At the same time, the plastic sealing member 40 can be plastic-sealed once on both sides of the first substrate 10 to achieve overall plastic sealing of the chip packaging structure, without the need to plastic-seale the two sides of the first substrate 10 twice, with high plastic sealing efficiency, and without the need to use two sets of plastic sealing molds, thereby reducing costs.

[0068] Of course, for those skilled in the art, other structures and working principles of the electronic device are understandable and achievable, and will not be described in detail in the present invention.

[0069] Although some specific embodiments of the present invention have been described in detail by way of example, it will be appreciated by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It will be appreciated by those skilled in the art that the above embodiments may be modified without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. A chip packaging structure, characterized in that: include: A first substrate (10), wherein a plurality of first pins (11) are provided on the first substrate (10); An electric support member (20), the electric support member (20) being disposed on the first substrate (10), and the electric support member (20) being electrically connected to the first pin (11); a second substrate (30), the second substrate (30) being spaced apart from and arranged in parallel with the first substrate (10), and the first substrate (10) and the second substrate (30) being supported and connected by the electric support member (20), a plurality of second pins (31) being arranged on the second substrate (30), wherein some of the second pins (31) are electrically connected to the electric support member (20) so as to form an electrical interconnection between the first substrate (10) and the second substrate (30), and the remaining second pins (31) are used for leading out and connecting to external components; A plastic packaging member (40), the plastic packaging member (40) is used to plastic-package the opposite two sides of the first substrate (10) respectively to form the chip packaging structure.

2. The chip packaging structure according to claim 1, characterized in that: Two ends of the electric support (20) are respectively bonded or soldered to the first substrate (10) and the second substrate (30).

3. The chip packaging structure according to claim 1, characterized in that: The electric support (20) is a solder ball.

4. The chip packaging structure according to claim 1, characterized in that: The electric support member (20) is a resistance connecting member.

5. The chip packaging structure according to claim 1, characterized in that: The first substrate (10) and the second substrate (30) are respectively circuit boards.

6. The chip packaging structure according to claim 1, characterized in that: A first chip (51) is provided on the first side of the first substrate (10), and a second chip (52) is provided on the second side of the first substrate (10); the first side and the second side of the first substrate (10) are opposite sides in the thickness direction of the first substrate (10).

7. The chip packaging structure according to claim 1, characterized in that: A portion of the plastic package (40) is filled between the first substrate (10) and the second substrate (30), and another portion of the plastic package (40) is filled on a side of the first substrate facing away from the second substrate (30).

8. A method for preparing a chip packaging structure, used for preparing the chip packaging structure according to any one of claims 1 to 7, characterized in that: The preparation method comprises: Providing a first substrate (10) having a first pin (11), and mounting an electric support member (20) on a side of the first substrate (10) having the first pin (11) to form a first structural member; The first structural component is stacked on a second substrate (30) having a second pin (31); A plastic packaging member (40) is filled on the side of the first substrate (10) facing away from the second substrate (30) and between the first substrate (10) and the second substrate (30) to obtain the chip packaging structure.

9. The method for preparing a chip packaging structure according to claim 8, characterized in that: Also includes: Mounting a first chip (51) on a first side of the first substrate (10); A second chip (52) is mounted on the second side of the first substrate (10), wherein the first side and the second side of the first substrate (10) are opposite sides in the thickness direction of the first substrate (10).

10. An electronic device, characterized in that: A chip packaging structure comprising any one of claims 1-7.

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