Low-power-consumption power-on reset circuit

Abstract

The invention relates to a low-power-consumption power-on reset circuit, which realizes low-power-consumption and high-stability power-on reset and power-on detection functions by utilizing the hysteresis characteristic of a Schmitt trigger and combining the complementary control of a PMOS (P-channel Metal Oxide Semiconductor) transistor and an NMOS (N-channel Metal Oxide Semiconductor) transistor. Not only is necessary reset time delay provided, but also power consumption of the circuit in the starting process is reduced. Meanwhile, in order to further improve the performance, a voltage detection hysteresis function is provided, an additional protection mechanism is provided, and the situation that the voltage is too low due to power supply fluctuation is prevented. Compared with the prior art, the power-on reset circuit has the advantages that the overall power consumption of the power-on reset circuit is remarkably reduced by utilizing the low power consumption characteristic of the CMOS transistor, the reset stability of the circuit is ensured through accurate voltage detection and delay control, the response speed of the circuit to the power supply change is improved through the optimized voltage detection module, the circuit design is simple, and the cost is low. And the method is easily compatible with the existing integrated circuit process.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuit design and relates to a low-power power-on reset circuit. Background Art

[0002] In the context of the rapid development of current electronic devices, the requirements for power management are getting higher and higher. As an important component of electronic systems, the power-on reset (POR) circuit is responsible for providing the circuit with an initial state when the power is turned on or the system is reset. In integrated circuit design, the power-on reset circuit plays a vital role, ensuring that the system can perform initialization safely and stably when the power is turned on or reset. However, the existing POR circuits are generally unable to effectively reduce power consumption in standby mode, resulting in shortened battery life. Some POR circuits do not respond quickly enough when the power changes, affecting the startup speed of the system. Power fluctuations or noise can easily cause false triggering of traditional POR circuits, reducing the reliability of the system; some complex POR circuits are difficult to be compatible with existing integrated circuit processes, limiting their scope of application. With the continuous improvement of energy efficiency requirements for electronic devices, traditional POR circuits can no longer meet the needs of modern low-power design due to their inherent power consumption problems. Summary of the invention

[0003] In view of the problems existing in the above-mentioned traditional methods, the present invention proposes two low-power power-on reset circuits, which can quickly and stably provide a reset signal when the power supply is powered on, while significantly reducing power consumption.

[0004] In order to achieve the above objectives, the embodiments of the present invention adopt the following technical solutions: On the one hand, a low-power power-on reset circuit is provided, comprising a voltage detection module and a quantization delay module, the quantization delay module comprising an intermediate delay unit and a two-stage Schmitt trigger, the two input ends of the two-stage Schmitt trigger are respectively connected to a first power supply voltage and a second power supply voltage, the output end of the first-stage Schmitt trigger is connected to a first control end of the intermediate delay unit, the output end of the intermediate delay unit is connected to a control end of a second-stage Schmitt trigger, and the output end of the second-stage Schmitt trigger is used to provide a stable reset signal; The voltage detection module includes a current mirror, an NMOS tube pair with a proportional aspect ratio, a voltage-dividing resistor unit and a startup load capacitor, wherein the input end of the current mirror is connected to the first power supply voltage, the output end of the current mirror is connected to the input end of the NMOS tube pair, the control end of the current mirror is connected to the second control end of the intermediate delay unit, the output end of the NMOS tube pair is grounded through the voltage-dividing resistor unit, the control end of the voltage-dividing resistor unit is connected to the first control end of the intermediate delay unit, the gate of the startup load capacitor is respectively connected to the output end of the current mirror and the control end of the first-stage Schmitt trigger, the source of the startup load capacitor is connected to the first power supply voltage, and the drain of the startup load capacitor is connected to the input end of the intermediate delay unit; The voltage-dividing resistor unit is used to provide a variable voltage divider for the voltage detection module, the quantized delay module is used to perform digital logic conversion according to the output result of the voltage detection module, and the intermediate delay unit is used to generate a microsecond delay by charging the capacitor.

[0005] On the other hand, another low-power power-on reset circuit is also provided, including a voltage detection module and a quantization delay module, the quantization delay module includes an intermediate delay unit and a two-stage Schmitt trigger, the two input ends of the two-stage Schmitt trigger are respectively connected to a first power supply voltage and a second power supply voltage, the output end of the first-stage Schmitt trigger is connected to a first control end of the intermediate delay unit, the output end of the intermediate delay unit is connected to a control end of a second-stage Schmitt trigger, and the output end of the second-stage Schmitt trigger is used to provide a stable reset signal; The voltage detection module includes a current mirror, an NMOS tube pair with a proportional aspect ratio, a voltage-dividing resistor unit and a startup load capacitor, wherein the input end of the current mirror is connected to the first power supply voltage, the output end of the current mirror is connected to the input end of the NMOS tube pair, the control end of the current mirror is connected to the second control end of the intermediate delay unit, the output end of the NMOS tube pair is grounded through the voltage-dividing resistor unit, the gate of the startup load capacitor is respectively connected to the output end of the current mirror and the control end of the first-stage Schmitt trigger, the source of the startup load capacitor is connected to the first power supply voltage, and the drain of the startup load capacitor is connected to the input end of the intermediate delay unit; The voltage-dividing resistor unit is used to provide voltage division for the voltage detection module, the quantization delay module is used to perform digital logic conversion according to the output result of the voltage detection module, and the intermediate delay unit is used to generate microsecond delay through capacitor charging.

[0006] One of the above technical solutions has the following advantages and beneficial effects: The above-mentioned low-power power-on reset circuit realizes low-power and high-stability power-on reset and power-on detection functions by utilizing the hysteresis characteristics of the Schmitt trigger and combining the complementary control of PMOS and NMOS transistors. It not only provides the necessary reset delay, but also helps to reduce the power consumption of the circuit during the startup process. At the same time, in order to further improve the performance, a voltage detection hysteresis function is provided to provide an additional protection mechanism to prevent low voltage caused by power supply fluctuations. Compared with the prior art, the low-power consumption characteristics of CMOS transistors are utilized to significantly reduce the overall power consumption of the power-on reset circuit. The stability of the circuit reset is ensured through precise voltage detection and delay control. The optimized voltage detection module improves the circuit's response speed to power supply changes. The circuit design is simple and easy to be compatible with existing integrated circuit processes. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0008] Figure 1 It is a structural schematic diagram of a low-power power-on reset circuit in one embodiment; Figure 2 FIG. 4 is a schematic diagram of the structure of another low-power power-on reset circuit in an embodiment. DETAILED DESCRIPTION

[0009] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0010] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0011] It should be noted that the reference to "embodiment" in this article means that the specific features, structures or characteristics described in conjunction with the embodiment may be included in at least one embodiment of the present invention. The presentation of this phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It will be understood by those skilled in the art that the embodiments described herein may be combined with other embodiments. The term "and / or" used in the specification of the present invention and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations. "Connection" can be a direct connection between two devices, or it can be an indirect connection between two devices through other devices.

[0012] The following will describe the implementation of the present invention in detail with reference to the accompanying drawings in the embodiment diagram of the present invention.

[0013] In view of the above limitations of the existing POR circuit, the electronics industry urgently needs a new low-power POR circuit, which should have the following characteristics: Low power consumption: While ensuring fast response and high stability, the power consumption of the circuit is significantly reduced.

[0014] Fast response: The circuit can respond quickly to power supply changes, shortening the system startup time.

[0015] High stability: good anti-interference ability, reducing the possibility of false triggering.

[0016] Easy to integrate: compatible with modern integrated circuit technology, easy to use in various electronic devices.

[0017] Although there are some designs on the market that attempt to reduce power consumption by optimizing circuits, these designs usually sacrifice the accuracy of reset or increase the complexity of the circuit. Aiming at the shortcomings of the existing POR circuit, the present invention proposes a new type of low-power power-on reset circuit, which is designed to reduce energy consumption while maintaining fast response and high reliability to meet the needs of modern electronic systems for high efficiency and fast startup. Through innovative circuit structure and control strategy, it is possible to significantly reduce power consumption while ensuring stable operation of the system, providing electronic equipment with longer battery life and faster startup performance.

[0018] In one embodiment, Figure 1 As shown, a low-power power-on reset circuit 100 is provided, which may include a voltage detection module 11 and a quantization delay module. The quantization delay module includes an intermediate delay unit 13 and a two-stage Schmitt trigger, and the two input terminals of the two-stage Schmitt trigger are respectively connected to a first power supply voltage (VDD) and a second power supply voltage (VSS). The output terminal of the first-stage Schmitt trigger 15 is connected to a first control terminal of the intermediate delay unit 13. The output terminal of the intermediate delay unit 13 is connected to a control terminal of a second-stage Schmitt trigger 17. The output terminal of the second-stage Schmitt trigger 17 is used to provide a stable reset signal (VPOR).

[0019] The voltage detection module 11 includes a current mirror 111, an NMOS transistor pair 113 with a proportional aspect ratio, a voltage-dividing resistor unit 115, and a startup load capacitor PM2. The input end of the current mirror 111 is connected to the first power supply voltage, the output end of the current mirror 111 is connected to the input end of the NMOS transistor pair 113, and the control end of the current mirror 111 is connected to the second control end of the intermediate delay unit 13. The output end of the NMOS transistor pair 113 is grounded through the voltage-dividing resistor unit 115, and the control end of the voltage-dividing resistor unit 115 is connected to the first control end of the intermediate delay unit 13. The gate of the startup load capacitor PM2 is respectively connected to the output end of the current mirror 111 and the control end of the first-stage Schmitt trigger 15, the source of the startup load capacitor PM2 is connected to the first power supply voltage, and the drain of the startup load capacitor PM2 is connected to the input end of the intermediate delay unit 13. The voltage-dividing resistor unit 115 is used to provide a variable voltage division of the voltage detection module 11. The quantization delay module is used to perform digital logic conversion according to the output result of the voltage detection module 11. The intermediate delay unit 13 is used to generate a microsecond delay by charging a capacitor.

[0020] It can be understood that the internal structure of the two-stage Schmitt trigger can be as follows Figure 1 As shown, the main circuit of each stage of Schmitt trigger is the same and adopts the existing Schmitt trigger circuit structure.

[0021] The above-mentioned low-power power-on reset circuit 100 realizes low-power and high-stability power-on reset and power-on detection functions by utilizing the hysteresis characteristics of the Schmitt trigger and combining the complementary control of PMOS and NMOS transistors. It not only provides the necessary reset delay, but also helps to reduce the power consumption of the circuit during the startup process. At the same time, in order to further improve the performance, a voltage detection hysteresis function is provided to provide an additional protection mechanism to prevent low voltage caused by power supply fluctuations. Compared with the prior art, the low-power consumption characteristics of CMOS transistors are utilized to significantly reduce the overall power consumption of the power-on reset circuit. Through precise voltage detection and delay control, the stability of circuit reset is ensured. The optimized voltage detection module 11 improves the circuit's response speed to power supply changes. The circuit design is simple and easy to be compatible with existing integrated circuit processes.

[0022] In one embodiment, Figure 1 As shown, further, the current mirror 111 includes a PM0 tube and a PM1 tube. The NMOS tube pair 113 includes an NM0 tube and an NM1 tube. The voltage-dividing resistor unit 115 includes a resistor R0, a resistor R1, a resistor R2 and an NM2 tube. The sources of the PM0 tube and the PM1 tube are both connected to the first power supply voltage. The gate of the PM0 tube is connected to the gate of the PM1 tube, the drain of the PM1 tube is connected to the gate of the startup load capacitor PM2, and the gate of the PM1 tube is connected to the second control end of the intermediate delay unit 13. The drain of the PM0 tube is connected to one end of the resistor R0, and the other end of the resistor R0 is respectively connected to the drain of the NM0 tube, the gate of the NM0 tube and the gate of the NM1 tube. The source of the NM0 tube is respectively connected to one end of the resistor R2 and the drain of the NM2 tube through the resistor R1. The source of the NM1 tube, the source of the NM2 tube and the other end of the resistor R2 are all grounded. The gate of the NM2 tube is connected to the first control end of the intermediate delay unit 13.

[0023] In one embodiment, Figure 1As shown, further, the intermediate delay unit 13 includes a PM3 tube, a PM4 tube, an NM3 tube, an NM4 tube and a PM5 tube. The gate of the PM3 tube (i.e., the second control terminal of the intermediate delay unit 13) is connected to the gate of the PM1 tube, and the source of the PM3 tube and the source of the PM5 tube are both connected to the drain of the startup load capacitor PM2. The drain of the PM3 tube is connected to the source of the PM4 tube. The gate of the PM4 tube (i.e., the first control terminal of the intermediate delay unit 13) is respectively connected to the gate of the NM3 tube and the output terminal of the first-stage Schmitt trigger 15, the drain of the PM4 tube is connected to the source of the NM3 tube, and the drain of the NM3 tube and the source of the NM4 tube are both grounded. The gate of the PM5 tube is respectively connected to the control terminal of the second-stage Schmitt trigger 17, the drain of the PM4 tube and the gate of the NM4 tube, and the drain of the PM5 tube is connected to the first bias terminal of the second-stage Schmitt trigger 17. The drain of the NM4 tube is connected to the second bias terminal of the second-stage Schmitt trigger 17.

[0024] It should be noted that if Figure 1 As shown, the low power consumption power-on reset circuit 100 mainly includes two key parts: a voltage detection module 11 and a quantization delay module. The voltage detection module 11 includes a current mirror 111, two NMOS transistor pairs 113 with proportional width-to-length ratios (i.e., NM0 and NM1 transistors, , Indicates the width-to-length ratio of the NM0 tube, represents the width-to-length ratio of the NM1 tube, k is a proportional coefficient), resistor R0, resistor R1, resistor R2 and startup load capacitor PM2, resistor R0, resistor R1 and resistor R2 form a voltage divider resistor network for providing variable voltage division. Current mirror 111 is composed of two PMOS tubes (i.e., PM0 tube and PM1 tube). The quantized delay module includes a two-stage Schmitt trigger (ST) and an intermediate delay circuit.

[0025] The circuit working principle of the low power consumption power-on reset circuit 100 may be as follows: In the process of the power supply voltage VDD rising from 0, when the power supply voltage VDD is relatively low, the PMOS tube and the NMOS tube cannot be fully turned on. At this time, the source voltage of the PM1 tube follows the power supply voltage VDD because the charging of the startup load capacitor PM2 is started, ensuring that when the power supply voltage VDD is relatively low, the entire circuit is still in the output reset state.

[0026] As the power supply voltage VDD increases, both PM0 and NM0 are turned on and the current flowing through branch 1 I Also increases and satisfies the following formula: (1) in, , , Indicates the threshold voltage of the PMOS tube, Represents the threshold voltage of the NMOS tube, W represents the transistor width, L represents the transistor length, represents the electron mobility of the NM0 tube, represents the electron mobility of PM0 tube, is the gate oxide capacitance, R 0 represents the resistance value of resistor R0, R 1 represents the resistance value of resistor R1, R 2 represents the resistance value of resistor R2, V DD Indicates the value of the power supply voltage VDD.

[0027] The gate voltage of NM1 tube is: (2) Among them, when the NM2 tube is turned on, the voltage divider resistance value ; When NM2 is turned off, the voltage divider resistance value .

[0028] Because the current mirror 111 formed by PM0 and PM1 makes the current of branch 1 and branch 2 I Keeping them equal, to make NM1 work in the saturation region, the gate voltage required for NM1 is: (3) When the current is small and Sometimes, there is At this time, the voltage at point A is higher than the voltage at point B, and the voltage detection module 11 continues to output a high level.

[0029] when Sometimes, there is At this time, the voltage at point A is equal to the voltage at point B, and branch 1 becomes the input signal source for dividing the power supply voltage VDD, while the NM1 tube and the PM1 tube form a common-source amplifier with a large gain.

[0030] when Sometimes, there is At this time, the voltage at point A is lower than the voltage at point B, and the output of the voltage detection module 11 flips to a low level.

[0031] Therefore, as the power supply voltage VDD increases, the current flowing through branch 1 and branch 2 increases accordingly. When the voltage rises again, the output of the voltage detection module 11 will become a low level.

[0032] The quantized delay module converts the output result of the voltage detection module 11 into digital logic. At the same time, the intermediate delay unit 13 charges the PM5 tube used as a capacitor to generate several tens of (microseconds) delay, and when the power supply voltage VDD is relatively low, Figure 1 Point C in the circuit outputs a high level, and the resistor R2 is short-circuited. At this time, a higher power supply voltage VDD is required to flip the output of the voltage detection module 11. At the same time, when the power supply voltage VDD is relatively high and the point C outputs a low level, the resistor R2 is connected to the branch 1. At this time, a lower power supply voltage is required to flip the output of the voltage detection module 11. Therefore, the output of the voltage detection module 11 achieves the effect of hysteresis voltage.

[0033] In one embodiment, Figure 2 As shown, another low-power power-on reset circuit 200 is also provided, including a voltage detection module 11 and a quantization delay module. The quantization delay module includes an intermediate delay unit 13 and a two-stage Schmitt trigger. The two input ends of the two-stage Schmitt trigger are respectively connected to the first power supply voltage and the second power supply voltage, and the output end of the first-stage Schmitt trigger 15 is connected to the first control end of the intermediate delay unit 13. The output end of the intermediate delay unit 13 is connected to the control end of the second-stage Schmitt trigger 17, and the output end of the second-stage Schmitt trigger 17 is used to provide a stable reset signal.

[0034] The voltage detection module 11 includes a current mirror 111, an NMOS tube pair 113 with a proportional aspect ratio, a voltage-dividing resistor unit 115, and a startup load capacitor PM2. The input end of the current mirror 111 is connected to the first power supply voltage, the output end of the current mirror 111 is connected to the input end of the NMOS tube pair 113, and the control end of the current mirror 111 is connected to the second control end of the intermediate delay unit 13. The output end of the NMOS tube pair 113 is grounded through the voltage-dividing resistor unit 115. The gate of the startup load capacitor PM2 is respectively connected to the output end of the current mirror 111 and the control end of the first-stage Schmitt trigger 15, the source of the startup load capacitor PM2 is connected to the first power supply voltage, and the drain of the startup load capacitor PM2 is connected to the input end of the intermediate delay unit 13. The voltage-dividing resistor unit 115 is used to provide the voltage division of the voltage detection module 11, the quantization delay module is used to perform digital logic conversion according to the output result of the voltage detection module 11, and the intermediate delay unit 13 is used to generate a microsecond delay by capacitor charging.

[0035] It is understandable that Figure 2 As shown, this embodiment provides another Figure 1The circuit shown is a variant design under low power supply voltage, and the resistor R0 is used to provide voltage division. The circuit working principle of the low power consumption power-on reset circuit 200 in this embodiment can be understood by referring to the circuit working principle of the low power consumption power-on reset circuit 100 in the above embodiment, and the only difference is that the variable voltage division is realized by connecting or disconnecting the resistor R0, which will not be repeated here.

[0036] The above-mentioned low-power power-on reset circuit 200 realizes low-power and high-stability power-on reset and power-on detection functions by utilizing the hysteresis characteristics of the Schmitt trigger and combining the complementary control of PMOS and NMOS transistors. It not only provides the necessary reset delay, but also helps to reduce the power consumption of the circuit during the startup process. At the same time, in order to further improve the performance, a voltage detection hysteresis function is provided to provide an additional protection mechanism to prevent the voltage from being too low due to power supply fluctuations. Compared with the prior art, the low-power consumption characteristics of CMOS transistors are utilized to significantly reduce the overall power consumption of the power-on reset circuit. Through precise voltage detection and delay control, the stability of circuit reset is ensured. The optimized voltage detection module 11 improves the circuit's response speed to power supply changes. The circuit design is simple and easy to be compatible with existing integrated circuit processes.

[0037] In one embodiment, Figure 2 As shown, the current mirror 111 includes a PM0 tube and a PM1 tube. The NMOS tube pair 113 includes an NM0 tube and an NM1 tube. The voltage-dividing resistor unit 115 includes a resistor R0. The sources of the PM0 tube and the PM1 tube are both connected to the first power supply voltage, the gate of the PM0 tube is connected to the gate of the PM1 tube, and the drain of the PM0 tube is respectively connected to the drain of the NM0 tube, the gate of the NM0 tube, and the gate of the NM1 tube. The source of the NM0 tube is respectively connected to one end of the resistor R0 and the gate of the PM0 tube. The drain of the NM1 tube is connected to the drain of the PM1 tube, the drain of the PM1 tube is connected to the gate of the startup load capacitor PM2, and the gate of the PM1 tube is connected to the second control end of the intermediate delay unit 13. The source of the NM1 tube and the other end of the resistor R0 are both grounded.

[0038] In one embodiment, Figure 2As shown, the intermediate delay unit 13 includes a PM3 tube, a PM4 tube, an NM3 tube, an NM4 tube and a PM5 tube. The gate of the PM3 tube is connected to the gate of the PM1 tube, the source of the PM3 tube and the source of the PM5 tube are both connected to the drain of the startup load capacitor PM2, and the drain of the PM3 tube is connected to the source of the PM4 tube. The gate of the PM4 tube is respectively connected to the gate of the NM3 tube and the output end of the first-stage Schmitt trigger 15, the drain of the PM4 tube is connected to the source of the NM3 tube, and the drain of the NM3 tube and the source of the NM4 tube are both grounded. The gate of the PM5 tube is respectively connected to the control end of the second-stage Schmitt trigger 17, the drain of the PM4 tube and the gate of the NM4 tube, the drain of the PM5 tube is connected to the first bias end of the second-stage Schmitt trigger 17, and the drain of the NM4 tube is connected to the second bias end of the second-stage Schmitt trigger 17.

[0039] It can be understood that the specific explanation of each component of the low power consumption power-on reset circuit 200 can be understood by referring to the explanation of the low power consumption power-on reset circuit 100 in the above embodiment, and will not be repeated here.

[0040] In actual design applications, PMOS tubes, NMOS tubes, resistors and Schmitt triggers can be selected and arranged to achieve the design goals of low power consumption and fast response. According to the predetermined power supply voltage threshold and system requirements, the resistance ratio of the voltage divider resistor network is adjusted, and the circuit is integrated and tested according to the designed circuit structure to obtain the entire low-power power-on reset circuit to ensure that it correctly performs the power-on reset function within the specified voltage range.

[0041] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0042] The above embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of protection of the invention. It should be pointed out that, for a person of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present application, and all of them belong to the scope of protection of the present application. Therefore, the scope of protection of the present application shall be subject to the attached claims.

Claims

1. A low power consumption power-on reset circuit, characterized in that: It includes a voltage detection module and a quantization delay module, wherein the quantization delay module includes an intermediate delay unit and a two-stage Schmitt trigger, wherein two input ends of the two-stage Schmitt trigger are respectively connected to a first power supply voltage and a second power supply voltage, an output end of the first-stage Schmitt trigger is connected to a first control end of the intermediate delay unit, an output end of the intermediate delay unit is connected to a control end of the second-stage Schmitt trigger, and an output end of the second-stage Schmitt trigger is used to provide a stable reset signal; The voltage detection module includes a current mirror, an NMOS tube pair with a proportional aspect ratio, a voltage-dividing resistor unit and a startup load capacitor, wherein the input end of the current mirror is connected to the first power supply voltage, the output end of the current mirror is connected to the input end of the NMOS tube pair, the control end of the current mirror is connected to the second control end of the intermediate delay unit, the output end of the NMOS tube pair is grounded through the voltage-dividing resistor unit, the control end of the voltage-dividing resistor unit is connected to the first control end of the intermediate delay unit, the gate of the startup load capacitor is respectively connected to the output end of the current mirror and the control end of the first-stage Schmitt trigger, the source of the startup load capacitor is connected to the first power supply voltage, and the drain of the startup load capacitor is connected to the input end of the intermediate delay unit; The voltage-dividing resistor unit is used to provide a variable voltage division for the voltage detection module, the quantization delay module is used to perform digital logic conversion according to the output result of the voltage detection module, and the intermediate delay unit is used to generate a microsecond delay by charging a capacitor.

2. A low power consumption power-on reset circuit according to claim 1, characterized in that: The current mirror includes a PM0 transistor and a PM1 transistor, the NMOS transistor pair includes an NM0 transistor and an NM1 transistor, and the voltage-dividing resistor unit includes a resistor R0, a resistor R1, a resistor R2, and an NM2 transistor; The sources of the PM0 tube and the PM1 tube are both connected to the first power supply voltage, the gate of the PM0 tube is connected to the gate of the PM1 tube, the drain of the PM1 tube is connected to the gate of the startup load capacitor, and the gate of the PM1 tube is connected to the second control terminal of the intermediate delay unit; The drain of the PM0 tube is connected to one end of the resistor R0, the other end of the resistor R0 is respectively connected to the drain of the NM0 tube, the gate of the NM0 tube and the gate of the NM1 tube, the source of the NM0 tube is respectively connected to one end of the resistor R2 and the drain of the NM2 tube through the resistor R1, the source of the NM1 tube, the source of the NM2 tube and the other end of the resistor R2 are all grounded, and the gate of the NM2 tube is connected to the first control end of the intermediate delay unit.

3. A low power consumption power-on reset circuit according to claim 2, characterized in that: The intermediate delay unit includes a PM3 tube, a PM4 tube, an NM3 tube, an NM4 tube and a PM5 tube, the gate of the PM3 tube is connected to the gate of the PM1 tube, the source of the PM3 tube and the source of the PM5 tube are both connected to the drain of the startup load capacitor, the drain of the PM3 tube is connected to the source of the PM4 tube, the gate of the PM4 tube is respectively connected to the gate of the NM3 tube and the output end of the first-stage Schmitt trigger, the drain of the PM4 tube is connected to the source of the NM3 tube, and the drain of the NM3 tube and the source of the NM4 tube are both grounded; The gate of the PM5 tube is respectively connected to the control end of the second-stage Schmitt trigger, the drain of the PM4 tube and the gate of the NM4 tube, the drain of the PM5 tube is connected to the first bias end of the second-stage Schmitt trigger, and the drain of the NM4 tube is connected to the second bias end of the second-stage Schmitt trigger.

4. A low power consumption power-on reset circuit, characterized in that: It includes a voltage detection module and a quantization delay module, wherein the quantization delay module includes an intermediate delay unit and a two-stage Schmitt trigger, wherein two input ends of the two-stage Schmitt trigger are respectively connected to a first power supply voltage and a second power supply voltage, an output end of the first-stage Schmitt trigger is connected to a first control end of the intermediate delay unit, an output end of the intermediate delay unit is connected to a control end of the second-stage Schmitt trigger, and an output end of the second-stage Schmitt trigger is used to provide a stable reset signal; The voltage detection module includes a current mirror, an NMOS tube pair with a proportional aspect ratio, a voltage-dividing resistor unit and a startup load capacitor, wherein the input end of the current mirror is connected to the first power supply voltage, the output end of the current mirror is connected to the input end of the NMOS tube pair, the control end of the current mirror is connected to the second control end of the intermediate delay unit, the output end of the NMOS tube pair is grounded through the voltage-dividing resistor unit, the gate of the startup load capacitor is respectively connected to the output end of the current mirror and the control end of the first-stage Schmitt trigger, the source of the startup load capacitor is connected to the first power supply voltage, and the drain of the startup load capacitor is connected to the input end of the intermediate delay unit; The voltage-dividing resistor unit is used to provide the voltage division of the voltage detection module, the quantization delay module is used to perform digital logic conversion according to the output result of the voltage detection module, and the intermediate delay unit is used to generate a microsecond delay by charging a capacitor.

5. A low power consumption power-on reset circuit according to claim 4, characterized in that: The current mirror includes a PM0 transistor and a PM1 transistor, the NMOS transistor pair includes an NM0 transistor and an NM1 transistor, and the voltage-dividing resistor unit includes a resistor R0; The sources of the PM0 tube and the PM1 tube are both connected to the first power supply voltage, the gate of the PM0 tube is connected to the gate of the PM1 tube, the drain of the PM0 tube is respectively connected to the drain of the NM0 tube, the gate of the NM0 tube and the gate of the NM1 tube, the source of the NM0 tube is respectively connected to one end of the resistor R0 and the gate of the PM0 tube, the drain of the NM1 tube is connected to the drain of the PM1 tube, the drain of the PM1 tube is connected to the gate of the startup load capacitor, the gate of the PM1 tube is connected to the second control end of the intermediate delay unit, and the source of the NM1 tube and the other end of the resistor R0 are both grounded.

6. A low power consumption power-on reset circuit according to claim 5, characterized in that: The intermediate delay unit includes a PM3 tube, a PM4 tube, an NM3 tube, an NM4 tube and a PM5 tube, the gate of the PM3 tube is connected to the gate of the PM1 tube, the source of the PM3 tube and the source of the PM5 tube are both connected to the drain of the startup load capacitor, the drain of the PM3 tube is connected to the source of the PM4 tube, the gate of the PM4 tube is respectively connected to the gate of the NM3 tube and the output end of the first-stage Schmitt trigger, the drain of the PM4 tube is connected to the source of the NM3 tube, and the drain of the NM3 tube and the source of the NM4 tube are both grounded; The gate of the PM5 tube is respectively connected to the control end of the second-stage Schmitt trigger, the drain of the PM4 tube and the gate of the NM4 tube, the drain of the PM5 tube is connected to the first bias end of the second-stage Schmitt trigger, and the drain of the NM4 tube is connected to the second bias end of the second-stage Schmitt trigger.

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