TBC battery and preparation method thereof

Abstract

The embodiment of the invention provides a TBC battery and a preparation method thereof, in the embodiment of the invention, not only is a tunneling oxide layer added in an N region for passivation contact and phosphorus doping performed, but also a tunneling oxide layer added in a P region for passivation contact and boron diffusion and laser doping treatment are performed, so that the passivation of the P region is increased, the doping effect of the P region is improved, and the service life of the TBC battery is prolonged. Therefore, the photoelectric conversion efficiency of the cell can be improved, and the open-circuit voltage value of the cell is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of crystalline silicon solar cell manufacturing, and in particular to a TBC cell and a preparation method thereof. Background Art

[0002] The interdigitated back contact (IBC) battery is a new type of battery in which the contact electrodes of the P / N junction, substrate and emitter region are made in an interdigitated shape on the back of the battery. Its core technology is to prepare high-quality p-regions and n-regions arranged in an interdigitated shape on the back of the battery.

[0003] At present, P-type IBC cells use P-type silicon wafers as raw materials and retain the tunneling oxide layer passivation contact structure in the N+ region. The laser grooving method used in the P region retains the doping of the original silicon wafer, and laser film opening and aluminum paste printing are performed in the P region, which can easily lead to a decrease in the open circuit voltage value and photoelectric conversion efficiency of the battery. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a TBC battery and a preparation method thereof, so as to solve the problem of low open circuit voltage value and photoelectric conversion efficiency of existing P-type IBC batteries.

[0005] In order to solve the above problems, the present invention is achieved through the following technical solutions:

[0006] The present invention provides a method for preparing a TBC battery, which comprises:

[0007] After sequentially forming a first silicon oxide layer and a first polysilicon layer on the back side of the P-type silicon wafer, phosphorus-doping the first polysilicon layer;

[0008] Laser grooves are formed on the back of a phosphorus-doped P-type silicon wafer to form interdigitated n+ doped regions and p-type doped regions;

[0009] After laser grooving, a second silicon oxide layer and a second polysilicon layer are sequentially formed on the back of the silicon wafer, and the second polysilicon layer is subjected to boron diffusion treatment;

[0010] Performing laser doping treatment on the back side of the silicon wafer after the boron diffusion treatment;

[0011] The back side of the silicon wafer after the laser doping treatment is subjected to acid washing and alkali polishing to form an n+ doped region and a p+ doped region arranged in an interdigitated manner;

[0012] After acid washing and alkaline polishing, a passivation film layer and an anti-reflection film layer are formed on both sides of the silicon wafer, and a positive gate line connected to the p+ doped area and a negative gate line connected to the n+ doped area are formed on the back to produce a TBC battery.

[0013] Furthermore, before performing acid cleaning and alkali polishing on the back side of the silicon wafer after the laser doping treatment, the method further comprises:

[0014] The silicon wafer after the laser doping treatment is subjected to an oxidation treatment, wherein the oxidation treatment temperature is 800° C. to 81000° C., the oxygen flow rate is 200 to 8500 sccm, and the time is 58 to 15 minutes.

[0015] Furthermore, before laser grooving the back side of the phosphorus-doped P-type silicon wafer, the method further comprises:

[0016] Performing chain pickling on the phosphorus-doped silicon wafer, and sequentially forming a third silicon oxide layer, a first silicon nitride layer, and a fourth silicon oxide layer on the back side of the P-type silicon wafer;

[0017] Before sequentially forming a second silicon oxide layer and a second polysilicon layer on the back side of the P-type silicon wafer, the method further comprises:

[0018] The silicon wafer after laser grooving is subjected to chain pickling and texturing treatment.

[0019] Furthermore, after the laser-grooved silicon wafer is subjected to chain pickling and texturing treatment, and before a second silicon oxide layer and a second polysilicon layer are sequentially formed on the back of the silicon wafer, the method further comprises:

[0020] A fifth silicon oxide layer is formed on the front side of the silicon wafer.

[0021] Furthermore, in the method, the third silicon oxide layer, the fourth silicon oxide layer and the fifth silicon oxide layer are formed by respectively adopting a thermal oxidation process.

[0022] Furthermore, the temperature of the thermal oxidation process is 3008500° C., and the oxygen flow rate is 5000810000 sccm / min.

[0023] Furthermore, before sequentially forming a first silicon oxide layer and a first polysilicon layer on the back side of the P-type silicon wafer, the method further comprises:

[0024] The silicon wafer is subjected to alkali polishing treatment.

[0025] Furthermore, the width of the laser groove is 2808320 microns and the depth is 183 microns.

[0026] Furthermore, in the preparation method, the phosphorus-doped silicon wafer is subjected to chain pickling, comprising:

[0027] Using 285% by mass hydrochloric acid and 285% by mass hydrofluoric acid to clean the phosphorus-doped silicon wafer; and / or

[0028] The silicon wafer after laser grooving is subjected to chain pickling and texturing treatment, including:

[0029] The laser grooved silicon wafer is cleaned with 285% hydrochloric acid, and then KOH and a texturing additive are used to perform a groove texturing treatment; and / or

[0030] The back side of the laser doped silicon wafer is subjected to acid washing and alkali polishing, including:

[0031] The silicon wafer after laser grooving is cleaned with hydrochloric acid with a mass percentage of 183% and hydrofluoric acid with a mass percentage of 183%, and then alkaline polishing treatment is performed with KOH and alkaline polishing additives.

[0032] Furthermore, in the preparation method, forming a positive gate line conductive to the p+ doped region and a negative gate line conductive to the n+ doped region on the back side includes:

[0033] Printing silver-aluminum paste on a first area of ​​the anti-reflection film layer on the back of the silicon wafer, and printing silver paste on a second area of ​​the anti-reflection film layer on the back of the silicon wafer; the projection of the first area is within the range of the p+ doped area, and the projection of the second area is within the range of the n+ doped area;

[0034] The P-type silicon wafer with silver-aluminum paste printed on the first area and silver paste printed on the second area is sintered at high temperature.

[0035] The present invention also provides a TBC battery, which is prepared by the above method.

[0036] Compared with the prior art, the embodiments of the present invention have the following advantages:

[0037] In an embodiment of the present invention, after a first silicon oxide layer and a first polysilicon layer are sequentially formed on the back side of a P-type silicon wafer, the first polysilicon layer is doped with phosphorus; laser grooves are formed on the back side of the phosphorus-doped silicon wafer to form an n+ doped region and a p-type doped region arranged in a finger-like manner; after laser grooves, a second silicon oxide layer and a second polysilicon layer are sequentially formed on the back side of the silicon wafer, and the second polysilicon layer is subjected to boron diffusion treatment; laser doping treatment is performed on the back side of the silicon wafer after the boron diffusion treatment; acid pickling and alkali polishing are performed on the back side of the silicon wafer after the laser doping treatment to form an n+ doped region and a p+ doped region arranged in a finger-like manner; after acid pickling and alkali polishing, a passivation film layer and an anti-reflection film layer are formed on both sides of the silicon wafer, and a positive gate line conductive to the p+ doped region and a negative gate line conductive to the n+ doped region are formed on the back side to obtain a TBC battery. Not only is a tunneling oxide passivation contact added to the N region and phosphorus doping is performed, but a tunneling oxide passivation contact is also added to the P region and boron diffusion and laser doping are performed, which increases the passivation of the P region and increases the doping effect of the P region, thereby improving the photoelectric conversion efficiency of the battery and increasing the open circuit voltage value of the battery.

[0038] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 It is a flow chart of the method for preparing a TBC battery provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0040] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0041] The applicant of the present invention has discovered that the current P-type IBC battery uses P-type silicon wafers as raw materials and retains a tunneling oxide layer passivation contact structure in the N+ region, while the laser grooving method used in the P region retains the doping of the original silicon wafer, and laser film opening and aluminum paste printing are performed in the P region, which easily leads to a decrease in the open circuit voltage value and photoelectric conversion efficiency of the battery.

[0042] In order to solve the above problems, the embodiment of the present invention provides a method for preparing a TBC battery, which includes step 1018 and step 105:

[0043] Step 101, after sequentially forming a first silicon oxide layer and a first polysilicon layer on the back side of a P-type silicon wafer, phosphorus-doping the first polysilicon layer;

[0044] Step 102, laser grooving the back side of the phosphorus-doped silicon wafer to form interdigitated n+ doped regions and p-type doped regions;

[0045] Step 103, after laser grooving, sequentially forming a second silicon oxide layer and a second polysilicon layer on the back side of the silicon wafer, and performing boron diffusion treatment on the second polysilicon layer;

[0046] Step 104, performing laser doping treatment on the back side of the silicon wafer after the boron diffusion treatment;

[0047] Step 105, performing acid washing and alkali polishing on the back side of the silicon wafer after the laser doping treatment to form n+ doped regions and p+ doped regions arranged in an interdigitated manner;

[0048] Step 106, after pickling and alkaline polishing, a passivation film layer and an anti-reflection film layer are formed on both sides of the silicon wafer, and a positive gate line connected to the p+ doped area and a negative gate line connected to the n+ doped area are formed on the back side to obtain a TBC battery.

[0049] In the embodiment of the present invention, not only is a tunneling oxide layer passivation contact added to the N region and phosphorus doping is performed, but a tunneling oxide layer passivation contact is also added to the P region and boron diffusion treatment and laser doping treatment are performed, which not only increases the passivation of the P region, but also increases the doping effect of the P region, thereby improving the photoelectric conversion efficiency of the battery and increasing the open circuit voltage value of the battery.

[0050] In the above step 101, take the original P-type silicon wafer, and use low pressure chemical vapor deposition (LPCVD) to form an ultra-thin silicon oxide layer on the back of the P-type silicon wafer, that is, the above-mentioned first silicon oxide layer, as an ultra-thin tunneling oxide layer, and then use double-sided preparation or single-sided preparation to prepare the first polysilicon layer on the back to meet the thickness of the passivation effect; the thickness can be 1008200nm, for example, 150nm. Among them, because the double-sided preparation of the polysilicon layer is conducive to the subsequent removal of the front polysilicon layer, it is not easy to have the two extreme situations of excessive removal or insufficient removal, and the yield is better controlled.

[0051] In the above step 101, after preparing the first polysilicon layer, the silicon wafer is sent into a furnace tube to phosphorus-dope the first polysilicon layer to form an n+ doped region, thereby forming a passivation contact structure composed of a first silicon oxide layer and a phosphorus polysilicon layer, effectively reducing surface recombination and metal contact recombination.

[0052] The first polysilicon layer is doped with phosphorus by phosphorus diffusion. In the phosphorus diffusion process, the temperature is 8708920℃, POCl 3The deposition was carried out for 8812 min at a flow rate of 808150 sccm / min, an oxygen flow rate of 5008800 sccm / min, a nitrogen flow rate of 120082000 sccm / min, and a pressure of 1508200 mbar. The silicon wafer was then heated to 92081000°C and treated for 40880 min at a pressure of 800 mbar and an oxygen flow rate of 8000815000 sccm / min to obtain a surface doping concentration of 2E1885E18 / cm 3 n+ doped region.

[0053] The square resistance after phosphorus doping is 30840Ω / sq, and the junction depth of ECV is 0.581.5μm. For example, the square resistance after phosphorus doping is 32Ω / sq, and the junction depth of ECV is 0.95μm.

[0054] In the above step 102, the back side of the silicon wafer is laser grooved to expose the p-type doped region, forming an interdigitated n+ doped region and a p-type doped region, and then the front polysilicon layer is removed by a wet method. In this step, the phosphosilicate glass coated on the front side can be removed by using a chain machine in a single-sided film removal method using an alkali solution to react with the phosphosilicate glass.

[0055] Optionally, when laser grooving the back side of the silicon wafer, a laser is used to perform grooving using picosecond green light and laser marking, with a pulse width of 0.8 picoseconds and a pulse number of 2; the laser marking speed is 38000842000mm / second, the laser power is 50860w, the frequency is 100081500Hz, and the width of the laser back groove is 2808320 microns and the depth is 183 microns.

[0056] For example, the rated power of the laser is 100W, and laser marking is performed at 550‰ of the rated power, i.e., 55W. The laser marking speed is 25000mm / s and the frequency is 1200Hz, and a laser groove with a width of 320 microns and a depth of 1.5 microns is formed.

[0057] In the above step 103, the silicon wafer in the laser groove is taken, and a layer of ultra-thin silicon oxide, that is, the above-mentioned second silicon oxide layer, is formed on the back of the silicon wafer by low pressure chemical vapor deposition (LPCVD), which serves as an ultra-thin tunneling oxide layer, and then a second polysilicon layer having a thickness that can meet the passivation effect is prepared on the back by double-sided preparation or single-sided preparation; the thickness can specifically be 1008200nm, for example, 150nm.

[0058] In the above step 103, after preparing the second polysilicon layer, the silicon wafer is sent into the furnace tube to perform boron diffusion treatment on the second polysilicon layer to form a p+ doped region, thereby forming a passivation contact structure composed of a second silicon oxide layer and a boron polysilicon layer, effectively reducing surface recombination and metal contact recombination.

[0059] The second polysilicon layer is doped with boron by boron diffusion. In the boron diffusion process, the temperature is 8508890℃, BCl 3 The deposition was carried out for 8812 min at a flow rate of 808150 sccm / min, an oxygen flow rate of 5008800 sccm / min, a nitrogen flow rate of 120082000 sccm / min, and a pressure of 1508200 mbar. The silicon wafer was then heated to 102081060°C and treated for 40890 min at a pressure of 800 mbar and an oxygen flow rate of 8000817000 sccm / min to obtain a surface doping concentration of 2E1884E18 / cm 3 p+ doped region.

[0060] In the above step 104, the silicon wafer after the boron diffusion treatment is taken for laser SE, wherein, because after the boron diffusion treatment, a boron-rich borosilicate glass layer (BSG) is formed on the surface of the silicon wafer, the SE laser emitter uses this boron-rich BSG layer as a doping source, and emits laser pulses at high frequency to melt the surface of the silicon wafer, so that the boron atoms in the BSG layer are pushed to the surface of the silicon wafer, and the doped boron atoms will quickly replace the position of the silicon atoms after solidification, thereby achieving the purpose of diffusion and advancement of the doped atoms. The square resistance of the silicon wafer after the laser doping treatment is 40850 ohms, for example, 45 ohms.

[0061] Optionally, when laser doping is performed on the back side of the silicon wafer, a laser is used to perform laser doping by laser marking using picosecond green light, with a laser marking speed of 28000832000mm / s, a laser power of 50w, a frequency of 100081500Hz, and a processing time of 0.380.5s.

[0062] For example, the laser is used for laser marking at a power of 50 W, a speed of 30,000 mm / s, a frequency of 1,200 Hz, and a processing time of 0.45 s.

[0063] In the above step 105, the back side of the silicon wafer after laser doping is pickled and alkaline polished to remove the second silicon oxide layer, the boron-doped polysilicon layer and the borosilicate glass layer covering the n+ doped area, thereby exposing the n+ doped area, thereby forming n+ doped areas and p+ doped areas arranged in a finger-like manner.

[0064] Optionally, the silicon wafer after laser grooving is cleaned with hydrochloric acid having a mass percentage of 183% and hydrofluoric acid having a mass percentage of 183%, and then alkaline polishing is performed with KOH and a texturing additive.

[0065] For example, the boron-doped silicon wafer is chain pickled with 2% by mass hydrochloric acid and 2% by mass hydrofluoric acid, and then the silicon wafer is wet-alkali polished with KOH+alkali polishing additive, wherein, by volume, the alkali polishing solution includes 20 parts of concentrated KOH, 4 parts of alkali polishing additive BP65 and 450 parts of pure water, the processing time is 240s, and the processing temperature is 70°C.

[0066] In the above step 106, an atomic layer deposition (ALD) process is used to plate a passivation layer on the entire front and back of the product to form field passivation; after the aluminum oxide film layer is formed, an anti-reflection film layer is first plated on the front of the battery, and then on the back, to further enhance the passivation effect of the battery cell.

[0067] Optionally, the passivation layer is an aluminum oxide film layer, that is, the aluminum oxide film layer is plated on the entire front surface and the entire back surface as the passivation layer.

[0068] Optionally, the anti-reflection film layer is a silicon nitride layer, that is, the anti-reflection film is formed by coating the entire front surface and the entire back surface with a silicon nitride layer; wherein the anti-reflection film includes multiple layers of silicon nitride layers, which can further enhance the anti-reflection effect.

[0069] In the above step 106, the silicon wafer after the anti-reflection film is formed is screen-printed to form a positive grid line connected to the p+ doped region and a negative grid line connected to the n+ doped region on the back. Specifically, silver-aluminum paste is printed on the first area of ​​the anti-reflection film layer on the back of the silicon wafer, and the projection of the first area is within the range of the p+ doped region to form a positive grid line connected to the p+ doped region; at the same time, silver paste needs to be printed on the second area of ​​the anti-reflection film layer on the back, and the projection of the second area is within the range of the n+ doped region to form a negative grid line spaced from the positive grid line.

[0070] Optionally, in one embodiment, the silver-aluminum paste is the silver-aluminum paste in the prior art, and the silver paste is the silver paste in the prior art.

[0071] Optionally, in one embodiment, the components constituting the above-mentioned silver-aluminum paste include organic additives, silver powder, aluminum powder, boron-aluminum alloy powder, organic binder and glass powder.

[0072] Among them, silver powder and aluminum powder are the main components, aluminum powder is mainly used to replace the P+ emitter of the battery, and silver paste has good thermal conductivity, electrical conductivity and burn-through performance; glass powder is an inorganic adhesive, which will melt into liquid under high temperature conditions and condense when cooled to play a bonding role; organic binder can ensure the overall bonding effect; organic additives can reduce the overall viscosity of the silver paste; because boron aluminum alloy powder can be mixed with metallic aluminum liquid, boron can be introduced into the silicon surface and diffused into the silicon for heavy doping, which is beneficial to improve the contact performance of the slurry and reduce the reaction contact area between aluminum and silicon; the above-mentioned silver aluminum paste can quickly form a good alloy with silicon under lower sintering temperature conditions, reduce the contact resistivity between the front silver aluminum grid and the battery, thereby improving the battery filling and battery efficiency.

[0073] Optionally, in one embodiment, in the above-mentioned silver-aluminum paste, the mass percentage of organic additives is 0.480.6%; the mass percentage of silver powder is 65875%; the mass percentage of aluminum powder is 385%; the mass percentage of boron-aluminum alloy powder is 0.0580.1%; the mass percentage of organic binder is 17.5830.55%; and the mass percentage of glass powder is 181.8%.

[0074] Optionally, in one embodiment, the aluminum powder includes a micron-grade aluminum powder with a mass fraction of 75880% and a D50 of 586μm, and a micron-grade aluminum powder with a mass fraction of 20825% and a D50 of 9810μm; the silver powder includes a micron-grade silver powder with a mass fraction of 88894% and a nano-grade silver powder with a mass fraction of 6812%. Specifically, the aluminum powder includes a spherical aluminum powder with a purity of 3 nines and a mass fraction of 75880% and a D50 of 586μm, and a spherical aluminum powder with a purity of 3 nines and a mass fraction of 20825% and a D50 of 9810μm. The silver powder is a micron-grade spherical silver powder with a purity of 3 nines and a mass fraction of 88894% and a nano-grade spherical silver powder with a purity of 3 nines and a mass fraction of 6812%. In the embodiment of the present invention, the above-mentioned silver powder is a micron-grade spherical silver powder with a purity of 3 nines. Among them, because there are gaps between micron-sized silver powders and gaps between micron-sized aluminum powders, the above-mentioned nano-sized spherical silver powder can just fill and penetrate into the gaps between the micron-sized ones.

[0075] The above-mentioned boron aluminum alloy powder is a micron-level boron aluminum alloy powder, which has the characteristics of high tap density, low oxygen content and high activity. By adding the micron-level boron aluminum alloy powder, the silver aluminum paste can quickly form a good alloy with silicon under lower sintering temperature conditions, thereby reducing the contact resistivity between the front silver aluminum fine grid and the battery.

[0076] Optionally, in one embodiment, the organic additive includes at least one of a silane coupling agent, lauryl phosphate, silicone oil, and a dibasic acid ester.

[0077] In the IBC battery aluminum paste provided in the embodiment of the present invention, the above-mentioned organic binder includes a polymer resin and an organic solvent; wherein the polymer resin is dissolved in the organic solvent, so that the organic solvent can be used as an organic binder, that is, the paste plays a role of bonding powder after drying.

[0078] Optionally, in one implementation, the mass fraction of the high molecular polymer in the organic binder is 98.15%; the mass fraction of the organic solvent in the organic binder is 858.91%.

[0079] Optionally, in one embodiment, the high molecular weight polymer is one or more of ethyl cellulose-N20, ethyl cellulose N-50, and ethyl cellulose-N100;

[0080] The organic solvent comprises at least four of benzyl alcohol, diethyl phthalate, terpineol, butyl carbitol, butyl carbitol acetate, tributyl citrate, Span 85 and alcohol ester twelve.

[0081] In the above step 106, the silver-aluminum paste is solidified by high-temperature sintering, and the silver-aluminum paste is used to burn through the anti-reflection film layer and the passivation layer in the above-mentioned first area to form a positive electrode grid line in contact with the p+ doped area. At the same time, the silver paste is solidified by high-temperature sintering, and the silver paste is used to burn through the anti-reflection film layer and the passivation layer in the above-mentioned second area to form a negative electrode grid line in contact with the n+ doped area, thereby producing an IBC battery.

[0082] Optionally, the high temperature sintering temperature is 750-8800°C, for example, 750°C, 772°C or 800°C.

[0083] Optionally, the preparation method provided in the embodiment of the present invention further includes step 1021 before the above step 102, and further includes step 1031 before the above step 103.

[0084] Step 1021 , chain pickling is performed on the phosphorus-doped silicon wafer, and a third silicon oxide layer, a first silicon nitride layer and a fourth silicon oxide layer are sequentially formed on the back side of the silicon wafer.

[0085] In the above step 1021, the phosphosilicate glass layer formed by the phosphorus diffusion treatment is first removed by chain pickling, and then a third oxide layer is formed on the back of the silicon wafer by a thermal oxidation process, and then a first silicon nitride layer is formed on the third silicon oxide layer by back coating, and then a fourth silicon oxide layer is formed on the first silicon nitride layer by a thermal oxidation process.

[0086] Among them, because the back side of the silicon wafer needs to be pickled and alkaline polished after boron doping, the above-mentioned first silicon nitride layer and the third silicon oxide layer can effectively alleviate the effects of the pickling and alkaline polishing treatments, thereby protecting the existing n+ doped area.

[0087] Optionally, in one embodiment, 285% by mass hydrochloric acid and 285% by mass hydrofluoric acid are used to clean the phosphorus-doped silicon wafer, which can effectively remove the formed phosphorus-silicate glass layer and avoid excessive cleaning to damage the boron-doped polysilicon layer. For example, 3% by mass hydrochloric acid and 4% by mass hydrofluoric acid are used to clean the phosphorus-doped silicon wafer.

[0088] Optionally, in one embodiment, the third silicon oxide layer and the fourth silicon oxide layer are formed by a thermal oxidation process, wherein the temperature of the thermal oxidation process is 3008500° C. and the oxygen flow rate is 5000810000 sccm / min. For example, the back side of the silicon wafer is thermally oxidized at a temperature of 400° C. and an oxygen flow rate of 8000 sccm / min to form the third silicon oxide layer and the fourth silicon oxide layer.

[0089] Step 1031, performing chain pickling and texturing treatment on the silicon wafer after laser grooving.

[0090] In the above step 1031, chain pickling is used to remove metal impurities such as Al, Fe, Zn, Ni on the surface of the silicon wafer, and to remove metal hydroxides attached to the natural oxide film; and the texturing process can form a velvet surface on the front side of the silicon wafer, which can greatly reduce the surface reflectivity of the cell. Among them, because the laser grooved area on the back side of the silicon wafer retains the fourth silicon oxide layer, it can be used to offset the effects of chain pickling and alkali washing, and protect the existing n+ doped area, so that the front side of the silicon wafer has a velvet surface and the back side is polished without velvet.

[0091] Optionally, in one embodiment, the laser grooved silicon wafer is cleaned with 285% hydrochloric acid by mass, and then KOH and texturing additives are used for groove texturing treatment, which can effectively remove the impurity cost formed by the laser groove and effectively form a velvet surface on the front side.

[0092] For example, the silicon wafer after laser grooving is chain pickled with 3% by mass hydrochloric acid and 4% by mass hydrofluoric acid, and then the silicon wafer is wet-textured with KOH+texturing additive, wherein, by volume, the texturizing solution includes 10 parts by mass of 45% concentrated KOH, 3 parts of texturizing additive EP12V78 and 400 parts of pure water, the processing time is 550s, and the processing temperature is 78°C.

[0093] Optionally, in one embodiment, the preparation method provided in the embodiment of the present invention further includes step 1032 after step 1031 and before step 103:

[0094] A fifth silicon oxide layer is formed on the front side of the silicon wafer.

[0095] In step 1032, after the texturing treatment, a fifth silicon oxide layer is formed on the front side of the silicon wafer through a thermal oxidation process, which can avoid damage to the front side texture surface by subsequent acid washing and alkali polishing treatments and protect the front side texture surface.

[0096] Optionally, in one embodiment, the fifth silicon oxide layer and the fourth silicon oxide layer are formed by a thermal oxidation process, wherein the temperature of the thermal oxidation process is 3008500° C. and the oxygen flow rate is 5000810000 sccm / min. For example, the back side of the silicon wafer is thermally oxidized at a temperature of 400° C. and an oxygen flow rate of 8000 sccm / min to form the fifth silicon oxide layer.

[0097] Optionally, in one implementation, step 1001 is further included before the above step 101.

[0098] Step 1001: performing alkali polishing on the silicon wafer.

[0099] In the above step 1001, the purpose of the alkali polishing treatment is to remove the surface damage from the original wafer cutting process; at the same time, the alkali polishing treatment also increases the surface area of ​​the battery cell to prepare for increasing the junction area for diffusion.

[0100] According to the method for preparing a TBC battery provided in an embodiment of the present invention, the block size after alkali polishing is 688 microns, for example, 6 microns, 7 microns or 8 microns.

[0101] Optionally, the alkali polishing treatment is to perform wet alkali polishing on the original silicon wafer in the form of KOH + alkali polishing additive, wherein, by volume, the texturing solution includes 30 parts of 45% concentrated KOH, 6 parts of alkali polishing additive BP56 and 450 parts of pure water, the processing time is 3008350s, and the processing temperature is 75880℃.

[0102] Optionally, in one embodiment, the preparation method provided in the embodiment of the present invention further includes step 1051 before the above step 105:

[0103] The silicon wafer after the laser doping treatment is subjected to an oxidation treatment, wherein the oxidation treatment temperature is 800° C. to 81000° C., the oxygen flow rate is 200 to 8500 sccm, and the time is 58 to 15 minutes.

[0104] In this embodiment, by performing oxidation treatment on the laser doped silicon wafer at a temperature of 800°C to 81000°C and an oxygen flow rate of 200 to 8500 sccm, not only can high temperature advancement be achieved to redistribute the diffused boron, but also an oxide layer can be formed, which can protect the boron-doped polysilicon layer when the silicon wafer is alkaline polished. The sheet resistance of the silicon wafer after oxidation treatment is 80 to 890 ohms, for example, 80 ohms, 85 ohms or 90 ohms.

[0105] The present invention also provides a TBC battery, wherein the battery is prepared by the above-mentioned TBC battery preparation method.

[0106] The present invention is described in detail below by way of examples.

[0107] Example 1

[0108] (1) A 182*182 P-type silicon wafer was subjected to alkali polishing to form a 688 μm square on the surface; wherein the mass percentage concentration of KOH in the alkali polishing was 1.5%, the alkali polishing additive was Tobang EP12V88, the treatment time was 340 s, and the treatment temperature was 70°C;

[0109] (2) After forming a first silicon oxide layer and a first polysilicon layer on the back of the P-type silicon wafer, the first polysilicon layer is doped with phosphorus by phosphorus diffusion. In the phosphorus diffusion process, the first polysilicon layer is doped with phosphorus at a temperature of 880°C and POCl 3 The deposition was carried out for 10 min at a flow rate of 120 sccm / min, an oxygen flow rate of 700 sccm / min, a nitrogen flow rate of 1800 sccm / min, and a pressure of 160 mbar. The silicon wafer was then heated to 980°C and treated for 70 min at a pressure of 800 mbar and an oxygen flow rate of 12000 sccm / min to obtain a surface doping concentration of 2E1885E18 / cm 3 n+ doped region;

[0110] (3) taking the silicon wafer after phosphorus expansion, and performing chain pickling with 2% by mass hydrochloric acid and 2% by mass hydrofluoric acid;

[0111] (4) thermally oxidizing the back side of the silicon wafer for 240 seconds at a temperature of 400° C. and an oxygen flow rate of 8000 sccm / min to form a third oxide layer;

[0112] (5) forming a first silicon nitride layer on the third silicon oxide layer by back side coating;

[0113] (6) thermally oxidizing the back side of the silicon wafer for 240 seconds at a temperature of 400° C. and an oxygen flow rate of 8000 sccm / min to form a fourth silicon oxide layer on the first silicon nitride layer;

[0114] (7) using a laser with a rated power of 100 W, laser grooving is performed on the back side of the silicon wafer by laser marking at 550‰ of the rated power, the laser marking speed is 40000 mm / s, the frequency is 1200 Hz, and a laser groove with a width of 300 μm and a depth of 1.5 μm is formed, thereby exposing the p-type doped region and forming an n+ doped region and a p-type doped region arranged in an interdigitated manner;

[0115] (8) Take the silicon wafer after laser grooving, use 3% hydrochloric acid for chain pickling for 30 seconds, and then perform wet texturing treatment; wherein, by volume, the texturing solution includes 10 parts of concentrated KOH, 3 parts of texturing additive EP12V58 and 400 parts of pure water, the treatment time is 550 seconds, and the treatment temperature is 78°C;

[0116] (9) taking the silicon wafer after the texturing treatment, performing thermal oxidation on the back side of the silicon wafer for 240 seconds at a temperature of 400° C. and an oxygen flow rate of 8000 sccm / min, so as to form a fifth silicon oxide layer on the front side of the silicon wafer;

[0117] (10) After the second silicon oxide layer and the second polysilicon layer are formed on the back of the silicon wafer after the front thermal oxidation treatment, the second polysilicon layer is doped with boron by boron diffusion. In the boron diffusion treatment, the temperature is firstly 880°C, BCl 3 The deposition was carried out for 10 min at a flow rate of 120 sccm / min, an oxygen flow rate of 600 sccm / min, a nitrogen flow rate of 16000 sccm / min, and a pressure of 180 mbar. The silicon wafer was then heated to 1030°C and treated for 80 min at a pressure of 800 mbar and an oxygen flow rate of 15000 sccm / min. The surface doping concentration was 2E1884E18 / cm 3 p+ doped region;

[0118] (11) The silicon wafer after boron diffusion treatment was taken and laser doped by laser marking using picosecond green light. The laser marking speed was 30000 mm / s, the laser power was 50 W, the frequency was 1200 Hz, and the processing time was 0.45 s.

[0119] (12) performing oxidation treatment on the laser doped silicon wafer at a temperature of 900° C. and an oxygen flow rate of 300 sccm for 10 minutes;

[0120] (13) The silicon wafer after oxidation treatment was chain pickled with 2% by mass hydrochloric acid and 2% by mass hydrofluoric acid, and then wet alkali polished with KOH + alkali polishing additive, wherein the alkali polishing solution included 20 parts of concentrated KOH, 4 parts of alkali polishing additive BP65 and 450 parts of pure water, the treatment time was 240 seconds, and the treatment temperature was 70°C;

[0121] (14) taking the silicon wafer after alkali polishing, and performing chain pickling with 2% hydrochloric acid;

[0122] (15) Take the silicon wafer after chain pickling, and use the atomic layer deposition process to plate an aluminum oxide film on the entire front and back of the product to form field passivation;

[0123] (16) After the aluminum oxide film is formed, a second silicon nitride layer is firstly plated on the front side of the battery as a front anti-reflection film layer, and then a third silicon nitride layer is plated on the back side as a back anti-reflection film layer.

[0124] (17) printing silver-aluminum paste on a first region of the anti-reflection film layer on the back side of the silicon wafer, wherein the projection of the first region is within the range of the p+ doped region; and printing silver paste on a second region of the anti-reflection film layer on the back side, wherein the projection of the second region is within the range of the n+ doped region;

[0125] (18) The silicon wafer is subjected to high temperature sintering to obtain a TBC battery, and the peak sintering temperature is 778°C.

[0126] After sintering, the electrical properties tested were: open circuit voltage 727.2mV, photoelectric conversion efficiency 25.42%, which is 0.35% higher than that of conventional processes.

[0127] To sum up, in this embodiment, by adopting multiple mask technology, not only a tunneling oxide passivation contact is added to the N region and phosphorus doping is performed, but also a tunneling oxide passivation contact is added to the P region and boron diffusion and laser doping are performed, which not only increases the passivation of the P region, but also increases the doping effect of the P region, thereby improving the photoelectric conversion efficiency of the battery and increasing the open circuit voltage value of the battery, thereby solving the problem of low open circuit voltage value and photoelectric conversion efficiency of existing P-type IBC batteries.

[0128] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they are aware of the basic creative concept. Therefore, the claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0129] The TBC battery and its preparation method provided by the present invention are introduced in detail above. The principle and implementation mode of the present invention are explained by using specific examples in this article. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation mode and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A method for preparing a TBC battery, characterized in that: include: After sequentially forming a first silicon oxide layer and a first polysilicon layer on the back side of the P-type silicon wafer, phosphorus-doping the first polysilicon layer; Laser grooving the back side of the phosphorus-doped silicon wafer to form interdigitated n+ doped regions and p-type doped regions; After laser grooving, a second silicon oxide layer and a second polysilicon layer are sequentially formed on the back of the silicon wafer, and the second polysilicon layer is subjected to boron diffusion treatment; Performing laser doping treatment on the back side of the silicon wafer after the boron diffusion treatment; The back side of the silicon wafer after the laser doping treatment is subjected to acid washing and alkali polishing to form an n+ doped region and a p+ doped region arranged in an interdigitated manner; After acid washing and alkaline polishing, a passivation film layer and an anti-reflection film layer are formed on both sides of the silicon wafer, and a positive gate line connected to the p+ doped area and a negative gate line connected to the n+ doped area are formed on the back to produce a TBC battery.

2. The preparation method according to claim 1, characterized in that: Before performing acid cleaning and alkali polishing on the back side of the silicon wafer after the laser doping treatment, the method further comprises: The silicon wafer after the laser doping treatment is subjected to oxidation treatment, wherein the oxidation treatment temperature is 800° C. to 1000° C., the oxygen flow rate is 200 to 500 sccm, and the time is 5 to 15 minutes.

3. The preparation method according to claim 1, characterized in that: Before laser grooving the back side of the phosphorus-doped silicon wafer, the method further comprises: Performing chain pickling on the phosphorus-doped silicon wafer, and sequentially forming a third silicon oxide layer, a first silicon nitride layer, and a fourth silicon oxide layer on the back side of the silicon wafer; Before sequentially forming a second silicon oxide layer and a second polysilicon layer on the back side of the silicon wafer, the method further comprises: The silicon wafer after laser grooving is subjected to chain pickling and texturing treatment.

4. The preparation method according to claim 3, characterized in that: After the laser-grooved silicon wafer is subjected to chain pickling and texturing treatment, and before a second silicon oxide layer and a second polysilicon layer are sequentially formed on the back of the silicon wafer, the method further comprises: A fifth silicon oxide layer is formed on the front side of the silicon wafer.

5. The preparation method according to claim 4, characterized in that: In the method, the third silicon oxide layer, the fourth silicon oxide layer and the fifth silicon oxide layer are formed respectively by thermal oxidation processes.

6. The preparation method according to claim 4, characterized in that: The temperature of the thermal oxidation process is 300-500° C., and the oxygen flow rate is 5000-10000 sccm / min.

7. The preparation method according to claim 1, characterized in that: Before sequentially forming a first silicon oxide layer and a first polysilicon layer on the back side of the P-type silicon wafer, the method further comprises: The silicon wafer is subjected to alkali polishing treatment.

8. The preparation method according to claim 1, characterized in that: The width of the laser groove is 280 to 320 microns and the depth is 1 to 3 microns.

9. The preparation method according to claim 3, characterized in that: The phosphorus-doped silicon wafer is subjected to chain pickling, comprising: Using 2-5% by mass hydrochloric acid and 2-5% by mass hydrofluoric acid to clean the phosphorus-doped silicon wafer; and / or The silicon wafer after laser grooving is subjected to chain pickling and texturing treatment, including: The laser grooved silicon wafer is cleaned with 2-5% hydrochloric acid by mass, and then KOH and a texturing additive are used for groove texturing treatment; and / or The back side of the laser doped silicon wafer is subjected to acid washing and alkali polishing, including: The silicon wafer after laser grooving is cleaned with hydrochloric acid with a mass percentage of 1 to 3% and hydrofluoric acid with a mass percentage of 1 to 3%, and then alkaline polishing treatment is performed with KOH and alkaline polishing additives.

10. A TBC battery, characterized in that: The invention is prepared by the method described in claims 1 to 9.

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