Voltage and clock frequency management

Abstract

The invention relates to voltage and clock frequency management. Voltage sensing circuitry and management circuitry provide voltage and clock frequency management. The voltage sensing circuitry may be configured to detect a voltage associated with a system on chip (SoC) and determine when the voltage transitions from a first voltage to a second voltage. The management circuitry may be configured to generate a timing signal for the SoC and alter a frequency of the generated timing signal in response to the detected voltage transition.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to digital logic circuits, and more specifically, to voltage and clock frequency management. Background Art

[0002] The memory system may include one or more digital circuits, which may include various circuit systems. Generally speaking, a portion of the circuit system may provide voltage signals to power the digital circuits and / or power components of the memory system. Summary of the invention

[0003] In one aspect, the present disclosure provides an apparatus for clock frequency management, comprising: a voltage sensing circuit system configured to: detect a voltage associated with a system on a chip (SoC); and determine when the voltage transitions from a first voltage to a second voltage; and a management circuit system configured to: generate a timing signal for the SoC; and change the frequency of the generated timing signal in response to the detected voltage transition.

[0004] In another aspect, the present disclosure further provides a method for clock frequency management, comprising: detecting a voltage associated with a system on a chip (SoC) by a voltage sensing circuit system; determining by the voltage sensing circuit system when the detected voltage transitions from a first voltage to a second voltage; generating a timing signal for the SoC by a management circuit system coupled to the voltage sensing circuit system; and changing by the management circuit system a frequency of the generated timing signal in response to the transition from the first voltage to the second voltage so that the frequency corresponds to the detected voltage during the transition.

[0005] In another aspect, the present disclosure further provides a system for clock frequency management, comprising: a plurality of computing components coupled to a system on a chip (SoC), wherein the SoC comprises: a voltage regulator; a voltage sensing circuit configured to: determine a voltage received from the voltage regulator; and determine when a voltage transition corresponds to an increase in voltage or a decrease in voltage; and a management circuit system configured to: generate a timing signal for the SoC; change a frequency of the generated timing signal in response to the increase in voltage or the decrease in voltage; and apply the timing signal having the changed frequency to one or more of the plurality of computing components or one or more components of the SoC. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments of the present disclosure.

[0007] Figure 1An example system including a voltage sensing circuit for voltage and clock frequency management according to some embodiments of the present disclosure is described.

[0008] Figures 2A to 2C Example timing signals for voltage and clock frequency management are described according to some embodiments of the present disclosure.

[0009] Figure 3 An example system including a voltage sensing circuit for voltage and clock frequency management according to some embodiments of the present disclosure is described.

[0010] Figure 4 is a flow chart corresponding to a method for voltage and clock frequency management according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0011] Aspects of the present disclosure relate to voltage and clock frequency management. Voltage and clock frequency management can be achieved by using a voltage sensing circuit that can determine the instantaneous voltage associated with a system (e.g., a system on a chip (SoC), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other hardware circuit system) and a management circuit system (e.g., a clock management circuit system, etc.) to reduce power consumption and / or improve the performance of the system compared to methods that do not employ such management. The voltage sensing circuit combined with the clock management circuit system described herein can provide benefits in systems that rely on instantaneous (or near-instantaneous) voltage sensing to dynamically track, limit, adjust and / or manipulate power consumption and / or noise. The following is combined with Figure 1 etc. describe examples of devices and systems that employ voltage and clock frequency management according to embodiments of the present disclosure.

[0012] The voltage and clock frequency management systems and devices described herein can dynamically and automatically adjust the timing signals generated during power mode transitions based on the detected voltage. Voltage sensing circuits can be used to detect instantaneous or near-instantaneous voltage readings associated with the system and provide the detected voltage to the clock management circuit system. The clock management circuit system can generate timing signals for the system in response to the detected voltage. In this way, the present disclosure provides a shorter power mode transition delay compared to previous systems. In addition, the present disclosure allows the power mode transition to be terminated without performance interruption. In addition, the present disclosure is able to dynamically and automatically adjust IR drops and / or other types of voltage irregularities while compensating for temperature and current fluctuations. These and other aspects of the present disclosure can also provide a reduction in power consumption in various types of systems, computing devices and / or circuits; thereby providing improvements to computing devices in which aspects of the present disclosure are deployed.

[0013] By utilizing the voltage sensing circuitry and / or clock management circuitry described herein, voltage and clock frequency management may be provided to a system and / or components coupled to the system. For example, the voltage sensing circuitry may be deployed in a system (e.g., an SoC, an ASIC, an FPGA, etc.) to detect voltage characteristics (e.g., voltage drops or "IR drops") at locations within the system that may be prone to exhibiting IR drop phenomena. As described in greater detail herein, in response to the voltage characteristics determined by the voltage sensing circuitry, the clock management circuitry may alter the frequency of a generated timing signal of the system. In this manner, the frequency of the timing signal may be locked to correspond to an actual voltage value determined by the voltage sensing circuitry.

[0014] Figure 1 An example system 100 including a voltage sensing circuit (e.g., a voltage sensor 103, etc.) according to some embodiments of the present disclosure is described. The example system 100 (which may be referred to as an "apparatus" in an alternative example) includes a voltage regulator 101, which is configured to generate a power supply signal (e.g., a supply voltage signal) and apply it to a voltage sensor 103 (e.g., a voltage sensing circuit, etc.) and / or other components of the system 100. As used herein, a voltage regulator 101 may be a device or system of devices that can manipulate or change an output voltage. For example, the voltage regulator 101 may include one or more of the following: a power supply, one or more converters, one or more inverters, one or more generators, and other electrical components that can change voltage or current. In another example, the voltage regulator 101 may include a battery or solar element having a switch that connects different battery elements to manipulate voltage.

[0015] System 100 may be coupled to one or more computing components. The computing component may be external to system 100 (i.e., the computing component is physically distinct from a chip, such as a SoC on which system 100 is deployed), but may be communicatively coupled to system 100 such that signaling may be exchanged between system 100 and the computing component. In some embodiments, the computing component may be internal to system 100 (i.e., physically located on a chip). Non-limiting examples of computing components may include controllers, memory devices, graphics processing units, processors / coprocessors, and / or logic blocks, as well as other computing components connected to a computer in which system 100 operates.

[0016] Voltage sensor 103 may include a voltage sensing circuit, which may be any type of circuit configured to instantaneously (or nearly instantaneously) sense a voltage or voltage change (e.g., an IR drop) in a power supply signal. Additionally, or in the alternative, the voltage sensor may include an analog comparator, an oscillator circuit, a phase detection circuit, a digital-to-analog converter, and / or an analog-to-digital converter. In some embodiments, system 100 is a system on a chip (SoC), an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA), among other possibilities.

[0017] like Figure 1 , the voltage sensor 103 may signal a voltage error to a clock controller 104 (e.g., a clock management circuit system, etc.). System 100 may include a clock controller 104 that includes a clock management circuit system. The clock controller 104 or the clock management circuit system may be configured to generate and apply timing signals to various components of the system 100, such as partition A 105-1, partition B 105-N, and / or additional partitions not illustrated. In some embodiments, partition A 105-1 may be a first logic block and partition B 105-2 may be a second logic block separate from the first logic block. However, embodiments are not limited thereto, and the clock controller 104 or the clock management circuit system may generate and apply timing signals to components external to the system 100, as described in more detail herein. Advantageously, the clock controller 104 may be configured to alter the frequency of a clock signal generated thereby, as will be described in more detail below.

[0018] Partition A 105-1 and / or Partition B 105-N may include various hardware forming one or more cores (e.g., "intellectual property (IP) cores"). As used herein, a "core" or "IP core" generally refers to one or more blocks of data and / or logic forming a constituent component of an application specific integrated circuit or a field programmable gate array. Partition A 105-1 and / or Partition B 105-N may be designed, constructed, and / or otherwise configured to perform specific tasks and / or functions within the systems described herein. In some embodiments, the voltage sensor 103 may take action (or cause action to be taken) to track, limit, adjust, or manipulate the dynamic power available to Partition A 105-1 and / or Partition B 105-N.

[0019] The clock controller 104 may include hardware circuitry configured to perform the operations described herein. For example, the clock controller 104 may include one or more chips or other hardware circuitry configured to generate a periodic oscillating signal (e.g., a square wave) that is applied to the components of the system 100. In some embodiments, the clock controller 104 includes throttling circuitry, clock division circuitry, and / or a voltage controlled oscillator to facilitate embodiments of the present disclosure.

[0020] In some embodiments, at least one of the clock controller 104 and / or the voltage sensor 103 may reside on one of the partitions (partition A 105-1, partition B 105-N, etc.). As used herein, the term "resides on" refers to something that is physically located on a particular component. For example, the voltage sensor 103 and / or the clock controller 104 "resides on partition A 105-1" refers to a situation where the hardware circuitry including the voltage sensor 103 and / or the clock controller 104 is physically located on partition A 105-1. Herein, the term "resides on" may be used interchangeably with other terms such as "deployed on" or "located on".

[0021] In a non-limiting example, the system 100 may include a voltage sensor 103 configured to detect a voltage associated with a system on a chip (SoC) and determine when the voltage changes from a first voltage to a second voltage. The voltage may be generated by a voltage regulator 101. In some embodiments, the voltage transition may correspond to a specific voltage change (e.g., a voltage drop or an IR drop) that the SoC is consuming. In some embodiments, the voltage change may correspond to a change from a nominal voltage to a hold voltage or from a hold voltage to a nominal voltage. As used herein, a nominal voltage refers to a specified or specified voltage level at which an electrical component, device, or system is designed to operate. It can be used as a standard reference point for manufacturers and engineers to design, build, and operate various electrical and electronic devices. In this way, when the nominal voltage is detected by the voltage sensor 103, the system 100 can operate in a normal mode or an operating mode. As used herein, a hold voltage may refer to a minimum voltage for holding data associated with the system 100. In this way, a hold voltage may refer to a voltage provided by the voltage regulator 101 during a sleep mode or a low power mode of the system 100. In these embodiments, the nominal voltage may be a greater voltage than the holding voltage.

[0022] As described herein, the system 100 further includes a clock controller 104 configured to generate a timing signal for the SoC. The clock controller 104 may be further configured to change the frequency of the generated timing signal in response to the detected voltage transition. In some embodiments, the frequency of the generated timing signal is changed to correspond to the value of the detected voltage. In this way, the clock controller 104 may receive a specific voltage value from the voltage sensor 103 and generate a frequency of the timing signal corresponding to the specific voltage value. In some embodiments, the clock controller 104 may lock the frequency of the timing signal to the detected voltage, such that an increase in the detected voltage results in an increase in the frequency of the timing signal and a decrease in the detected voltage results in a decrease in the frequency of the timing signal.

[0023] In some embodiments, the clock controller 104 may be configured to change the frequency of the timing signal by increasing the frequency of the timing signal when the first voltage is less than the second voltage. The frequency of the timing signal may be referred to as the clock frequency or clock speed. The frequency of the timing signal is a parameter in digital systems and electronic devices. The frequency of the timing signal may represent the rate at which the clock signal alternates between its high state and low state (or transitions between 1 and 0) within a specific time interval. The timing signal may be used to synchronize various components and operations within digital and / or analog circuits, thereby ensuring that actions occur at precise and coordinated times. The clock frequency may be measured in Hertz (Hz) and represents the number of clock cycles that occur per second. Higher clock frequencies generally indicate faster processing capabilities and faster data transfer within the system.

[0024] In some embodiments, clock controller 104 may be configured to change the frequency of the generated timing signal in the absence of a guard band. As described herein, the frequency of the timing signal may be locked to the detected voltage and the frequency may be gradually reduced when the detected voltage reaches the holding voltage. By changing the frequency of the timing signal in response to the detected voltage, guard bands (e.g., overshoot / undershoot guard bands, etc.) are unnecessary to avoid overshoot and undershoot. Figure 3 This process without utilizing a guard band is further described in . In some embodiments, the clock controller 104 may be configured to change the frequency of the generated timing signal in the absence of clock management timing. As described herein, by locking the frequency of the timing signal to the detected voltage, utilizing clock management timing is unnecessary for transitioning between different power modes. In some embodiments, the clock management timing will force the timing signal to stop during the hold mode of the system 100 and restart when the hold mode transitions to the nominal mode. However, because the frequency of the timing signal is locked to the detected voltage, the additional clock management timing circuitry may be removed from the system 100.

[0025] In some embodiments, the clock controller 104 may be configured to apply a power mode transition termination during a power mode transition. Figure 2B As described, the power mode transition termination may include a termination signal that stops the transition from the first power mode to the second power mode during the transition period. For example, early termination of the retention mode may prevent the system 100 from transitioning from the nominal mode to the retention mode, so that the system 100 returns to the nominal mode before reaching the retention mode. Since the detected voltage does not reach the retention voltage associated with the retention mode, the timing signal is not completely stopped. In this way, the frequency of the timing signal may decrease between the nominal voltage and the termination signal. When the termination signal is received, the detected voltage and frequency of the timing signal may increase back to the voltage and frequency of the timing signal associated with the nominal mode.

[0026] In some embodiments, clock controller 104 may include clock management circuitry including throttling circuitry, clock division circuitry, a voltage controlled oscillator (VCO), or any combination thereof. Throttling circuitry may refer to circuitry for adjusting the frequency and / or clock speed of a timing signal. Clock division circuitry may refer to an electronic circuit that produces an output clock signal having a frequency that is a fraction of the frequency of its input clock signal. This may be accomplished by dividing the number of clock cycles of the input signal to produce an output signal with a reduced frequency. A voltage controlled oscillator may refer to an oscillator circuit that produces an output signal whose frequency can be controlled by an input voltage.

[0027] In some embodiments, the voltage sensing circuit of the voltage sensor 103 may be deployed on a memory system (e.g., a storage device, a memory module, or a hybrid of a storage device and a memory module), or otherwise included in a memory system. Examples of storage devices include solid state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controllers (eMMC) drives, universal flash storage devices (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0028] In other embodiments, the voltage sensing circuit of the voltage sensor 103 may be deployed on or otherwise included in a computing device, such as a desktop computer, a laptop computer, a server, a network server, a mobile computing device, a vehicle (e.g., an airplane, a drone, a train, a car, or other transportation vehicle), a device with Internet of Things (IoT) capabilities, an embedded computer (e.g., an embedded computer included in a vehicle, an industrial device, or a networked commercial device), or such a computing device including a memory and a processing device. As used herein, the term "mobile computing device" generally refers to a handheld computing device having a tablet or tablet form factor. In general, a tablet form factor may include a display screen of approximately between 3 inches and 5.2 inches (measured diagonally), while a tablet form factor may include a display screen of approximately between 5.2 inches and 7 inches (measured diagonally). However, examples of "mobile computing devices" are not limited thereto, and in some embodiments, "mobile computing devices" may refer to IoT devices as well as other types of edge computing devices.

[0029] Such a computing device may include a host system coupled to a memory system (e.g., one or more storage devices, memory modules, or a mix of storage devices and memory modules). The host system may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an SSD controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). For example, the host system uses the storage devices, memory modules, or a mix of storage devices and memory modules to write data to the storage devices, memory modules, or a mix of storage devices and memory modules, and read data from the storage devices, memory modules, or a mix of storage devices and memory modules.

[0030] In these examples, the host system may include a processing unit, such as a central processing unit (CPU), configured to execute an operating system. In some embodiments, the processing unit may execute a complex instruction set computer architecture, such as x86 or other architecture suitable for use as a CPU for the host system.

[0031] The host system may be coupled to the memory system via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), a Small Computer System Interface (SCSI), a Double Data Rate (DDR) memory bus, a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM slot interface supporting Double Data Rate (DDR)), an Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), or any other interface. The physical host interface may be used to transfer data between the host system and the memory system. When the memory system is coupled to the host system via a PCIe interface, the host system may further utilize an NVM Express (NVMe) interface to access the component. The physical host interface may provide an interface for transferring control, address, data, and other signals between the memory system and the host system. In general, the host system may access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0032] The memory system may include any combination of different types of non-volatile memory devices and / or volatile memory devices. The volatile memory devices may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0033] Some examples of non-volatile memory devices include non-and (NAND) type flash memory and write-in-place memory, such as a three-dimensional cross-point ("3D cross-point") memory device, which is a cross-point array of memory cells. The cross-point array of non-volatile memory can perform bit storage based on bulk resistance changes in combination with a stackable cross-gate data access array. In addition, in contrast to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without previously erasing the non-volatile memory cells. NAND type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0034] Although nonvolatile memory components such as three-dimensional cross-point arrays of nonvolatile memory cells and NAND-type memories (e.g., 2D NAND, 3D NAND) are described, the memory device may be based on any other type of nonvolatile memory or storage device, such as read-only memory (ROM), phase-change memory (PCM), self-select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), non-OR (NOR) flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0035] The memory system may also include additional circuitry or components. In some embodiments, the memory system may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that may receive addresses from a memory system controller and decode the addresses to access memory devices.

[0036] In some embodiments, a memory device may include a local media controller that operates in conjunction with a memory system controller to perform operations on one or more memory cells of the memory device. For example, an external controller may manage the memory device externally (e.g., perform media management operations on the memory device). In some embodiments, the memory device is a managed memory device, which is a raw memory device combined with a local controller for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0037] Figures 2A to 2C Example timing signals for voltage and clock frequency management are described in accordance with some embodiments of the present disclosure. Figures 2A to 2C261, 262, 263, 264 and / or 265 may be any periodic signal (e.g., sawtooth wave, sine wave, etc.). Figure 1 The clock management circuit system of the clock controller 104 described in the figure) generates the timing control signals 221, 262, 263, 264 and / or 265.

[0038] Figure 2A A timing signal 221 is illustrated that may be generated by the clock management circuitry in response to a detected voltage 222. In this manner, the frequency of the timing signal 221 may correspond to the level or value of the detected voltage 222. For example, the frequency of the timing signal 221 may increase when the detected voltage 222 increases, and the frequency of the timing signal 221 may decrease when the detected voltage 222 decreases.

[0039] The timing signal 221 and the detected voltage 222 may include a timing start position 223-1 and a voltage start position 223-2. Although these are visual start positions, the timing signal 221 and / or the detected voltage 222 have been valid before the start positions 223-1, 223-2. The detected voltage at the voltage start position 223-2 may be at a nominal voltage level. As described herein, the nominal voltage level may refer to a voltage utilized during a normal operating level of the system. As described herein, the timing signal 221 may be locked to the voltage level of the detected voltage 222. In this way, the frequency of the timing signal 221 at the position 230 may be the frequency of the timing signal 221 during the nominal voltage of the detected voltage 222.

[0040] In some embodiments, the detected voltage 222 may decrease at locations 224, 225. In some embodiments, the detected voltage 222 may decrease at locations 224, 225 during the transition from the nominal voltage to the hold voltage. In these embodiments, Figure 1 The clock controller 104 or similar timing circuit system referenced in can receive the detected voltage at locations 224, 225 and reduce the frequency of the timing signal 221, as illustrated at location 231. In previous systems and devices, the clock controller 104 can completely stop generating the timing signal 221 when there is an indication that the voltage is transitioning from the nominal voltage to the detected voltage or the system is transitioning from the awake state to the sleep state. Figure 2A As illustrated in FIG. 2 , the frequency of the clock signal 221 is reduced during the transition at positions 224, 225, rather than completely stopping the clock signal 221. In some embodiments, changing the frequency of the clock signal 221 during the voltage transition may allow the clock to continue during the voltage transition, as compared to previous embodiments where the clock is stopped during the voltage transition. Figure 2B As further described, continuing the clocking signal 221 may allow early termination signals to be executed without missing termination and / or stalling the clock.

[0041] In some embodiments, when the detected voltage 222 reaches the holding voltage at position 226, the timing signal 221 may stop during position 232. In some embodiments, the detected voltage 222 may transition from the holding voltage at position 226 to a reduced voltage at position 228. The voltage transition at position 227 may be illustrated by the corresponding frequency of the timing signal 221 at position 233. The detected voltage 222 may transition from the reduced voltage at position 228 to the nominal voltage at position 229. As the transition of the detected voltage 222 between position 227 and position 228 increases, the frequency of the timing signal 221 may increase at position 233. In a similar manner, as the transition of the detected voltage 222 between position 228 and position 229 increases, the frequency of the timing signal may increase at position 234.

[0042] like Figure 2A As described in , the timing signal 221 continues to operate during the transition from the nominal voltage to the holding voltage, from the nominal voltage to the reduced voltage, from the holding voltage to the nominal voltage, and / or from the holding voltage to the reduced voltage. In some embodiments, the voltage increase and reduction are gradually performed to avoid transient current events. As used herein, transient current refers to the temporary or short-lived flow of current in a circuit. Transient current may occur when the voltage changes suddenly or when a circuit element such as a switch is suddenly opened or closed. Transient current can appear as a rapid fluctuation of charge flow and can cause changes in voltage levels and other electrical parameters. These types of transient current events can damage electrical components of the circuit and / or interrupt the operation of the electrical components. In these embodiments, the voltage can be transformed to avoid transient current events and continue to operate the timing signal 221.

[0043] Figure 2B Example timing signals for voltage and clock frequency management are described according to some embodiments of the present disclosure. Figure 2B The difference between the timing signal 221-1 and the detected voltage 222-1 of the present disclosure compared to the timing signal 221-2 and the detected voltage 222-2 of the previous system and device is described. In addition, Figure 2B Describe when there is early termination of a power mode transition (eg, power up, power down, hold mode transition, nominal mode transition, etc.).

[0044] As used herein, early termination of a power mode transition refers to stopping the power mode transition and / or changing from a first power mode transition to a second power mode transition. For example, a device or system may receive a command to transition from a nominal mode to a hold mode. In this example, during the transition, the device may receive a termination command. This termination command may be an instruction to transition back to the nominal mode before reaching the hold mode. In this way, early termination allows the device to change back to the original mode during the transition to a different mode. In another example, a device or system may receive a command to transition from a hold mode to a nominal mode. In this example, during the transition, the device may receive a termination command. This termination command may be an instruction to transition to a reduced voltage mode. In this way, early termination allows the device to transition to a different mode during the initial transition without having to complete the initial transition.

[0045] In some embodiments, the starting positions 223-1, 223-2, 223-3, 223-4 may be at a nominal voltage of a device having a corresponding clock frequency. In some embodiments, the nominal voltage may correspond to a nominal mode of the device (e.g., a normal operating mode, etc.). In this way, the timing signal 221-1 of the present disclosure and the timing signal 221-2 of the previous system may be described on the same timeline. That is, the timing signal 221-1 and the timing signal 221-2 may be the same or similar between the starting positions 223-2, 223-4 and the position 240. In addition, the detected voltage 222-1 of the present disclosure and the detected voltage 222-2 of the previous system may be the same nominal voltage between the starting positions 223-1, 223-3 and the position 240.

[0046] At position 240, the device may receive an instruction to enter a hold mode or recognize an indication that the device is entering a hold mode. Figure 2B As illustrated in FIG. 1 , the timing signal 221-1 of the present disclosure changes the generated timing signal to a lower frequency in response to the voltage level decreasing between position 240 and position 241. The timing signal 221-2 of the previous device stops or deactivates the timing circuitry so that no timing signal is generated between position 240 and position 241.

[0047] At position 241, a termination command is issued to the device to terminate the initiation of the hold mode and return to the nominal mode. At position 241, the timing signal 221-1 of the present disclosure continues to generate a timing signal at a frequency corresponding to the voltage level at position 241. In this way, the timing signal 221-1 continues to pass through position 241, while the timing signal 221-2 remains invalid, even if the hold mode is terminated early.

[0048] There is a voltage transition between position 241 and position 242 to increase the voltage back to the nominal voltage. In these embodiments, as the voltage increases back to the nominal voltage, the frequency of the timing signal 221-1 may increase. When the detected voltage 222-1 reaches the nominal voltage, the timing signal 221-1 may return to the frequency associated with the nominal voltage. Figure 2B As illustrated in , the timing signal 221-2 misses the hold termination at 241 and stagnates without the timing signal. In some previous systems, a counter is used to determine a timeout during a transition period or during a transition from a first mode to a second mode.

[0049] It may be difficult to determine the amount of time to transition from the first mode to the second mode. For example, the amount of time for the transition period may vary depending on the current, capacitance, or other characteristics of the system. Therefore, the counter is set to have a large error margin that can cover the worst-case amount of time for this voltage transition. In addition, in the case where a termination signal occurs during the transition between the first mode and the second mode, it may be difficult to determine when the voltage is stable. Therefore, a counter timeout with a large error margin can be utilized in the case where termination occurs during the transition. In some embodiments, the timing signal 221-2 may be slowed down or stopped before the voltage 222-2 decreases. In this way, the error margin may be at the beginning and / or end of the transition from the first mode to the second mode. Similar error margins are provided for the transition from the nominal voltage to the hold voltage and the transition from the hold voltage to the nominal voltage.

[0050] Between the position 242 and the position 243, another signal (e.g., a second signal, etc.) is received to enter the hold mode. Therefore, the detected voltage 222-1 decreases from the nominal voltage to the hold voltage between the position 242 and the position 243. In these embodiments, as the detected voltage 222-1 decreases, the timing signal 221-1 may decrease at the same or similar rate. At the position 243, the detected voltage 222-1 reaches the hold voltage value. In these embodiments, when the detected voltage 222-1 reaches the hold voltage, the timing signal 221-1 may stop or delay.

[0051] like Figure 2BAs illustrated in , the timing signal 221-2 of the previous device misses the second signal indicating that the device is to be converted to the holding mode. Since the timing signal 221-2 misses the second signal indicating that the device is to be converted to the holding mode, the frequency of the timing signal 221-2 at the position 244 is at the nominal frequency, which may waste power at the voltage level of the detected voltage 222-2. Utilizing a clock frequency at the nominal frequency when the voltage is higher than the nominal voltage may result in power waste. In contrast, the timing signal 221-1 is at a frequency synchronized with the detected voltage 222-1 and is therefore not too fast or too slow. In these embodiments, the detected voltage 222-1 may increase from the holding voltage at the position 243 to the reduced voltage at the position 245 and then increase from the reduced voltage back to the nominal voltage at the position 246. In a manner similar to that described herein, the timing signal 221-1 may be altered to have a frequency corresponding to the detected voltage 222-1 through the conversion.

[0052] As illustrated by the timing signal 221-2, the frequency between the position 246 and the position 247 is slower than the frequency associated with the timing signal 221-1 and / or the nominal voltage. In this manner, the timing signal 221-1 is at a higher frequency between the position 246 and the position 247 than the timing signal 221-2. In this manner, the timing signal 221-1 represents the current voltage between the position 246 and the position 247, while the timing signal 221-2 is operating at a lower frequency than the frequency provided by the voltage 222-2 (e.g., the timing signal is too slow, etc.).

[0053] Figure 2C Example timing signals for voltage and clock frequency management are described according to some embodiments of the present disclosure. Figure 2C A first graphical representation 251 of a voltage aggressor IP 260, a voltage victim IP 261, an aggressor IP clock 262, and a victim IP clock 263 of a prior system is illustrated, and a second graphical representation 252 of an aggressor IP clock 264 and a victim IP clock 265 of the present disclosure is illustrated. Thus, the first graphical representation 251 of the prior system can be easily compared to the second graphical representation 252 of the present disclosure.

[0054] Referring to the first graphical representation 251, the voltage aggressor IP 260 can illustrate when the voltage of the system starts at a nominal voltage, moves to a holding voltage, and then moves back to the nominal voltage. The voltage victim IP 261 can illustrate an overshoot at location 266 and an undershoot at location 272. At location 266, the voltage spike or jump may be due to the aggressor IP clock 262 suddenly stopping. When the clock is suddenly gated or significantly slowed, the dynamic current drops and a voltage jump is generated at location 266, while the voltage regulator catches up and then returns to normal. At location 272, the voltage drop may be due to the aggressor IP clock 262 restarting and / or a sudden increase in dynamic current. In previous systems, an overshoot / undershoot protection band can be used to protect the system from the overshoot at location 266 and the undershoot at location 272.

[0055] Additionally, voltage victim IP 261 illustrates artifact overshoot / undershoot at location 268 and location 270. In some embodiments, a voltage regulator (e.g., Figure 1 101, etc.) may include artifacts in response to being instructed to change the voltage output. In some embodiments, the artifacts at location 268 and / or location 270 may be jumps (rapid increases) or dips (rapid decreases) based on the reaction of a particular voltage regulator to the instruction. In some embodiments, the voltage aggressor IP may share a voltage regulator with other voltage aggressor IPs and thus the voltage victim IP 261 may cause artifacts based on its performance. In other embodiments, the artifacts at location 268 and / or location 270 may be a jump (rapid increase) or a dip (rapid decrease) based on the reaction of a particular voltage regulator to the instruction. Figure 3 In some embodiments, the artifacts may be caused by leakage current and / or capacitance.

[0056] One or more of the following may cause the

[0057] Referring to the second graphical representation 252, the aggressor IP clock 264 of the present disclosure illustrates how the frequency of the timing signal decreases as the system transitions from the nominal voltage to the holding voltage. The victim IP clock 265 of the present disclosure illustrates that an overshoot at position 266 will result in a high frequency and an undershoot at position 272 will result in a reduced frequency. In some previous embodiments, a guard band is utilized to protect the system from the effects of overshoot / undershoot. In some embodiments, the guard band is a system tolerance for voltage interruptions. For example, the guard band may be a system tolerance range with high and low voltage extremes on either side of the target voltage. The present disclosure provides a tighter (better) tolerance range with high and low voltage extremes by monitoring voltage changes and adjusting the clock frequency in response to the voltage changes.

[0058] In some embodiments, the frequency of the timing signal may be adjusted during voltage spikes and / or voltage drops. For example, the frequency of the timing signal may be adjusted in real time during artifacts associated with a voltage regulator. As described herein, artifacts of a voltage regulator may be unexpected results of a non-ideal voltage regulator during operation. For example, an artifact may be an output voltage spike during a transition, such as a rapid change in load or current. In other embodiments, the frequency of the timing signal may be adjusted in real time when different aggressor IPs share the same voltage supply or voltage regulator. In these embodiments, different aggressor IPs may cause fluctuations in the detected voltage (e.g., voltage drops, voltage spikes, etc.). In these embodiments, the present disclosure may adjust the frequency of the timing signal to mitigate changes in voltage. However, previous systems may be negatively affected by voltage variations during the nominal voltage of the previous system.

[0059] In the previous embodiment, the victim IP clock 263 does not slow down during the voltage undershoot at location 270 or location 272. In this way, the voltage is reduced while the victim IP clock 263 remains constant. In order to ensure that the previous system functions, it may be necessary to ensure that the victim IP clock 263 is fully functional at the lower voltages present at location 270 and / or location 272. Maintaining this full functionality of the victim IP clock 263 may require additional resources, including (but not limited to): relatively faster units, relatively higher power, larger area, longer off time, and other resources.

[0060] In previous embodiments, a prerequisite for stopping a clock may include stopping the clock before starting to reduce the voltage. Stopping the clock may require the end or completion of a specific operation. In addition, a prerequisite for starting the clock may be to increase the voltage until a timeout before starting the clock or starting an operation to start the clock. In the present disclosure, these prerequisites can be removed because the clock does not have to be stopped before reducing the voltage and the voltage does not have to reach the target voltage before starting the clock or speeding up the clock.

[0061] Figure 3 An example system 380 including a voltage sensing circuit for voltage and clock frequency management according to some embodiments of the present disclosure is illustrated. The example system 380 (which may be referred to as an "apparatus" in alternative examples) includes a primary voltage regulator 101-1 and a secondary voltage regulator 101-2 configured to generate a power supply and apply it to the system 380. In some embodiments, the system 380 may include a primary voltage regulator 101-1 and a secondary voltage regulator 101-2 configured to generate a power supply and apply it to the system 380. Figure 1 Some or all of the functionality described herein may also be implemented by the system 100 as described herein. Figure 1 The system 100 referenced therein is executed.

[0062] The system 380 may include multiple partitions (e.g., partition A 105-1, partition B 105-N, etc.). In some embodiments, the primary voltage regulator 101-1 and / or the secondary voltage regulator 101-2 may be connected to the first switch 381-1 and / or the second switch 381-N. In these embodiments, the first switch 381-1 and / or the second switch 381-N may allow the primary voltage regulator 101-1 and / or the secondary voltage regulator 101-2 to provide power to corresponding components of multiple partitions. In some embodiments, the primary voltage regulator 101-1 and / or the secondary voltage regulator 101-2 may provide power to partition A 105-1, which may be utilized by the first voltage sensor 103-1 and / or the first clock controller 104-1 as described herein. In a similar manner, the primary voltage regulator 101-1 and / or the secondary voltage regulator 101-2 may provide power to the partition B 105-N, which may be utilized by the second voltage sensor 103-N and / or the second clock controller 104-N as described herein. In this manner, the first clock controller 104-1 may utilize the detected voltage from the first voltage sensor 103-1 to generate a timing signal for a component associated with the partition A 105-1. Similarly, the second clock controller 104-N may utilize the detected voltage from the second voltage sensor 103-N to generate a timing signal for a component associated with the partition B 105-N.

[0063] In some embodiments, one or more of the voltage sensors 103-1, 103-N may determine a characteristic of a voltage received from one or more of the voltage regulators 101-1, 101-2. As described herein, the characteristic of the voltage may be a detected voltage determined by one or more voltage sensors 103-1, 103-N. The detected voltage may be a voltage received at a corresponding switch (e.g., first switch 381-1, second switch 381-2, etc.) coupled to the primary voltage regulator 101-1 and / or the secondary voltage regulator 101-2.

[0064] In some embodiments, one or more of the voltage sensors 103-1, 103-N may determine when a characteristic of a voltage transitions by increasing the voltage or by decreasing the voltage. As described herein, a voltage transition may be a transition from a first power mode to a second power mode. In some embodiments, termination of a transition between a first power mode and a second power mode may occur. In these embodiments, the detected voltage transition may be detected in a manner similar to the initiation of a transition.

[0065] In some embodiments, one or more of the clock controllers 104-1, 104-N may generate timing signals for the system 380 (eg, SoC, external components, etc.) As described herein, the clock controllers 104-1, 104-2 may include timing circuitry to generate timing signals of a particular frequency.

[0066] In some embodiments, one or more of the clock controllers 104-1, 104-N may change the frequency of the generated timing signal in response to the characteristic of increasing voltage or decreasing voltage. As described herein, the generated timing signal may be locked to the detected voltage. In this way, the frequency of the timing signal may increase as the voltage increases, and the frequency of the timing signal may decrease as the voltage decreases.

[0067] In some embodiments, one or more of the clock controllers 104-1, 104-N may apply a timing signal having a modified frequency to one or more of the plurality of computing components or one or more components of the SoC. As described herein, the plurality of computing components may be external to the SoC. In other embodiments, one or more components of the SoC reside on the SoC and include one or more logic blocks. In some embodiments, one or more of the plurality of computing components include a memory device, a controller, a graphics processing unit, a processing device, or a logic block, or any combination thereof. In some embodiments, the SoC includes an application specific integrated circuit.

[0068] Figure 4 is a flow chart corresponding to a method 491 for voltage and clock frequency management according to some embodiments of the present disclosure. The method 491 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 491 is performed by Figure 1 One or more components of system 100 and / or Figure 3380. Although shown in a particular sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0069] At operation 492, method 491 may include detecting, by voltage sensing circuitry, a voltage associated with the SoC. In some embodiments, the voltage sensing circuitry may reside on the SoC and / or remote from the SoC. As described herein, the voltage associated with the SoC may be a voltage detected at a voltage regulator of the SoC. In this manner, voltages provided to a plurality of components associated with the SoC may be detected by the voltage sensing circuitry and the detected voltages may be provided to the timing management circuitry.

[0070] At operation 493, method 491 may include determining, by the voltage sensing circuitry, when the detected voltage transitions from the first voltage to the second voltage. As described herein, the voltage transitioning from the first voltage to the second voltage may be an indicator that the SoC is transitioning from the first power mode to the second power mode. In this way, the voltage sensing circuitry may be utilized to determine when the SoC transitions from the first power mode to the second power mode.

[0071] At operation 494, method 491 may include generating, by clock management circuitry coupled to the voltage sensing circuitry, a timing signal for the SoC. The clock management circuitry may include components to generate a clock signal of a particular frequency. Additionally, the clock management circuitry may include components to alter the frequency of the timing signal and / or receive the detected voltage from the voltage sensing circuitry.

[0072] At operation 495, method 491 may include changing, by the clock management circuitry in response to the transition from the first voltage to the second voltage, the frequency of the generated timing signal so that the frequency corresponds to the detected voltage during the transition. In these embodiments, the frequency of the timing signal is locked to change with the detected voltage. In this way, the frequency of the timing signal may increase when the detected voltage increases and decrease when the detected voltage decreases.

[0073] In some embodiments, method 491 may include determining activation of a retention mode of the SoC, detecting, by a voltage sensing circuitry, that a voltage associated with the SoC transitions to a lower voltage in response to activation of the retention mode, and changing, by a clock management circuitry, a frequency to a corresponding lower frequency based on the transition to the lower voltage. In these embodiments, the SoC transitions to a retention mode and a corresponding retention voltage. In these embodiments, the voltage sensing circuitry may detect a decrease in voltage from a nominal voltage to a retention voltage. As the voltage decreases from the nominal voltage to the retention voltage, the clock management circuitry may decrease the frequency of the timing signal at a corresponding rate until the voltage reaches the retention voltage and the clock management circuitry may stop generating the timing signal.

[0074] The method 491 may include generating, by the clock management circuitry, a clock signal at a frequency that directly corresponds to the detected voltage value. As described herein, the frequency of the timing signal may directly correspond to the detected voltage such that an increase in the detected voltage results in an increase in the frequency of the generated timing signal. In some embodiments, the method 491 may include generating, by the clock management circuitry, a clock signal in the absence of a predicted voltage associated with the SoC. Since the actual detected voltage is utilized, a predicted voltage value is not required to generate the frequency of the timing signal. By utilizing the actual detected voltage rather than the predicted voltage, the systems and devices described herein can be changed dynamically even when there is a termination during the transition between power modes.

[0075] Method 491 may include generating a clock signal by the clock management circuit system in the absence of: a speed-up precondition when the first voltage is less than the second voltage, and / or a slow-down precondition when the first voltage is greater than the second voltage. In some previous embodiments, the speed-up precondition of the previous system may include raising the voltage and / or increasing the frequency of the clock before starting the clock. Therefore, the present disclosure does not require increasing the voltage before starting the clock. The slow-down precondition may include stopping the clock and / or slowing down the clock before starting to reduce the voltage. However, the present disclosure is able to change the clocking frequency in response to the detected voltage and therefore does not need to utilize the speed-up precondition or the slow-down precondition.

[0076] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively convey the substance of their work to others skilled in the art. An algorithm herein is generally conceived of as a self-consistent sequence of operations leading to a desired result. Operations are those requiring physical manipulation of physical quantities. Typically, although not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, primarily for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0077] It should be remembered, however, that all of these and similar terms should be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may involve actions and processes of computer systems or similar electronic computing devices that manipulate and transform data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0078] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0079] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used in conjunction with programs according to the teachings herein, or it may prove convenient to build more specialized equipment to perform the methods. The structures of a variety of these systems will appear as set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It should be appreciated that a variety of programming languages ​​may be used to implement the teachings of the present disclosure as described herein.

[0080] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, which can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form that can be read by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory device, etc.

[0081] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be appreciated that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Accordingly, the description and drawings should be viewed in an illustrative rather than a restrictive sense.

Claims

1. A device (100) for clock frequency management, comprising: A voltage sensing circuit system (103) configured to: Detecting voltages associated with a system on chip SoC; and determining when the voltage transitions from a first voltage to a second voltage; and A management circuit system (104) configured to: generating a timing signal for the SoC; and The frequency of the generated timing signal is altered in response to the detected voltage transition.

2. The apparatus of claim 1 , wherein the management circuit system is configured to change the frequency of the timing signal by decreasing the frequency of the timing signal when the first voltage is greater than the second voltage and increasing the frequency of the timing signal when the first voltage is less than the second voltage.

3. The apparatus of claim 1, wherein the management circuitry is further configured to alter the frequency of the timing signal during voltage undershoot / overshoot.

4. The apparatus of claim 1, wherein the management circuitry is configured to lock the frequency of the timing signal to the detected voltage.

5. An apparatus according to any one of claims 1 to 4, wherein the management circuit system is further configured to change the frequency of the generated timing signal in the absence of clock management timing to force the timing signal to stop during a holding mode and restart the clock signal when the holding mode transitions to a nominal mode.

6. The apparatus of any one of claims 1-4, wherein the management circuitry is further configured to apply a power mode transition termination during a power mode transition.

7. A method for clock frequency management, comprising: detecting, by a voltage sensing circuit system (103), a voltage associated with a system on chip SoC; determining, by the voltage sensing circuitry (103), when the detected voltage transitions from a first voltage to a second voltage; generating a timing signal for the SoC by management circuitry (104) coupled to the voltage sensing circuitry (103); and The frequency of the generated timing signal is altered by the management circuitry (104) in response to the transition from the first voltage to the second voltage so that the frequency corresponds to the detected voltage during the transition.

8. The method according to claim 7, further comprising: Determining initiation of a hold mode of the SoC; detecting, by the voltage sensing circuitry, that the voltage associated with the SoC transitions to a lower voltage in response to the initiation of the retention mode; and The frequency is changed, by the management circuitry, to a corresponding lower frequency based on the transition to the lower voltage.

9. The method according to claim 8, further comprising: determining early termination of the hold mode of the SoC; detecting, by the voltage sensing circuitry, that the voltage associated with the SoC transitions to a higher voltage in response to the termination of the hold mode; and The frequency is changed, by the managing circuitry, to a corresponding higher frequency based on the transition to the higher voltage.

10. The method according to claim 7, further comprising: generating, by the management circuitry, the clock signal at the frequency corresponding directly to the detected voltage; and The clock signal is generated by the management circuitry in the absence of a predicted voltage associated with the SoC.

11. The method of claim 7, further comprising generating, by the management circuitry, the clock signal in the absence of a speed-up prerequisite comprising increasing the voltage to a target voltage prior to generating the timing signal.

12. A system (380) for clock frequency management, comprising: A plurality of computing components coupled to a system-on-chip (SoC), wherein the SoC comprises: Voltage regulator (101-1, 101-2); A voltage sensing circuit (103) is configured to: determining a voltage received from the voltage regulator (101-1, 101-2); and determining when a voltage transition corresponds to an increase in voltage or a decrease in voltage; and A management circuit system (104) configured to: generating a timing signal for the SoC; modifying the frequency of the generated timing signal in response to the increasing voltage or decreasing voltage; and The clocking signal having the altered frequency is applied to one or more of the plurality of computing components or one or more components of the SoC.

13. The system of claim 12, wherein a portion of the plurality of computing components are external to the SoC.

14. The system of claim 12, comprising a secondary voltage regulator coupled to the voltage sensing circuit, wherein a voltage regulator and the secondary voltage regulator are coupled to the voltage sensing circuit through a switch.

15. The system of any one of claims 12 to 14, wherein the one or more components of the SoC reside on the SoC and include one or more logic blocks.

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