Open-closed loop smooth switching system based on charge pump phase-locked loop

Abstract

The invention provides an open-closed loop smooth switching system based on a charge pump phase-locked loop, and the system comprises a reference clock fault detection module which is connected with the charge pump phase-locked loop and is used for detecting whether a reference clock breaks down or not and carrying out the fault indication control of the reference clock; the PLL locking detection module is used for carrying out locking indication control on a phase-locked loop according to the phase difference between the frequency division signal of the reference clock and the frequency division signal of the charge pump output clock; the ADC / DAC control module is used for carrying out charge pump open-loop auxiliary holding and charge pump phase-locked loop open-loop to closed-loop auxiliary release; and the PLL control state machine module controls a state machine to perform clock selection, entry of a holding state and exit of the holding state. According to the invention, fault information can be identified as early as possible, open-closed loop conversion and retention state entry or exit of the charge pump phase-locked loop are realized, the deviation between the reference clock obtained again by the charge pump and the initial frequency value is less than 0.15 ppm, switching is smoothly completed, and a subsequent circuit is not affected.

Description

Technical Field

[0001] The invention relates to the technical field of clock chips, and in particular to an open-closed loop smooth switching system based on a charge pump phase-locked loop. Background Art

[0002] The charge pump phase-locked loop is a phase-locked loop structure widely used in modern communication systems. It has the advantages of high speed, low power consumption, low jitter and low cost. It is mainly composed of a phase detector, a charge pump, a loop filter and a voltage-controlled oscillator (VCO). The charge pump phase-locked loop has been widely used in frequency synthesis, clock recovery and other circuits. Its basic principle is to control the on and off state of the charge pump by the phase difference and frequency difference between the external reference signal and the output signal of the divider. Under the control of the phase detector, the charge pump distributes the charge to the loop filter, thereby adjusting the output frequency of the VCO to synchronize it with the reference frequency.

[0003] The charge pump phase-locked loop (PLL) is widely used in many fields such as communication and microprocessor due to its advantages of large open-loop gain, high capture, high stability, and zero static phase error. When the active reference clock of the charge pump phase-locked loop (PLL) fails and disappears and the PLL remains open-loop, the existing method is used to solve it, which often leads to excessive frequency deviation of the clock output by the PLL. These deviations can cause the downstream circuits and communication links to overflow the FIFO, or the PLL itself loses lock. Summary of the invention

[0004] In order to overcome the shortcomings of the prior art, the purpose of the present invention is to provide an open-closed loop smooth switching system based on a charge pump phase-locked loop, which can identify fault information as early as possible and put the charge pump into a three-state in advance. At this time, the charge pump PLL is converted from a closed loop state to an open loop state. When the reference clock is stable, the present invention controls the charge pump phase-locked loop to exit the holding state. At this time, the PLL is converted from an open loop state to a closed loop state. In the process, the charge pump re-acquires the reference clock (from open loop to closed loop) and the deviation from the initial frequency value is less than 0.15ppm, and the switching is completed smoothly without affecting the subsequent circuits.

[0005] To achieve the above object, the present invention provides the following scheme: an open-closed loop smooth switching system based on a charge pump phase-locked loop, comprising a reference clock fault detection module, a PLL lock detection module, an ADC / DAC control module and a PLL control state machine module connected to the charge pump phase-locked loop;

[0006] The reference clock fault detection module is used to detect whether the reference clock fails and perform fault indication control of the reference clock;

[0007] The PLL lock detection module is used to perform lock indication control of the phase-locked loop according to the phase difference between the frequency-divided signal of the reference clock and the frequency-divided signal of the charge pump phase-locked loop output clock;

[0008] The ADC / DAC control module is used for assisting the charge pump open loop maintenance and assisting the charge pump phase-locked loop release from open loop to closed loop;

[0009] The PLL control state machine module is used to control the state machine to perform clock selection, entry into a hold state, and exit from a hold state, thereby realizing control of the open-loop and closed-loop indications of the charge pump phase-locked loop.

[0010] Optionally, the reference clock fault detection module includes:

[0011] A clock constraint unit, used for setting the reference clock frequency that needs to be greater than 1 / 2 times the main clock frequency as a first clock constraint, and setting the main clock frequency that needs to be greater than 1 / 2 times the reference clock frequency as a second clock constraint;

[0012] A fault judgment unit is used to judge whether two consecutive reference clock rising edges appear within four consecutive master clock rising edges. If not, the reference clock is judged to be faulty and the clock fault signal of the corresponding channel is set to 1;

[0013] The read-only warning unit is used to determine whether two consecutive master clock rising edges appear within four consecutive reference clock rising edges. If not, a read-only warning that the master clock frequency is too low is issued.

[0014] Optionally, the PLL lock detection module includes:

[0015] A phase-locked loop locking unit, used for determining whether a flag signal indicating that the phase difference between the divided clock signal of the reference clock and the divided clock signal of the PLL output clock is too large is a continuous low-level signal during the period when the locking counter continuously counts 2^n divided clock cycles of the reference clock when the phase difference between the divided clock signal of the reference clock and the divided clock signal of the PLL output clock is less than 4ns, and if so, issuing a phase-locked loop locking indication;

[0016] The lock clearing unit is used to send a clear lock indication when the phase difference between the divided clock signal of the reference clock and the divided clock signal of the PLL output clock is greater than 4ns, and the flag signal of the excessive phase difference between the divided clock signal of the reference clock and the divided clock signal of the PLL output clock is a high-level signal. The lock counter is cleared and the charge pump phase-locked loop returns to the re-lock counting state.

[0017] Optionally, the ADC / DAC control module includes:

[0018] A first auxiliary unit is used to sample the oscillator control voltage value during the closed loop period of the charge pump phase-locked loop;

[0019] The second auxiliary unit is used to maintain the frequency stability of the oscillator by using the oscillator control voltage value sampled by the DAC output after the charge pump switches from a closed loop to an open loop.

[0020] Optionally, the PLL control state machine module includes:

[0021] The idle unit is used to receive the start signal of the entire system and enter the initialization state;

[0022] An initialization unit, used for preloading configuration, initializing the control signal output by the state machine master clock to the analog terminal according to the register configuration, and resetting each counter in the state machine to 0;

[0023] A lock counting state unit, used to determine whether the phase difference between the divided clock signal of the reference clock and the divided clock signal of the PLL output clock is continuously less than 4ns during the period when the lock counter continuously counts 2^n divided clock cycles of the reference clock. If so, the clock lock flag output by the PLL lock detection module is 1, and the PLL enters a lock state;

[0024] A locking unit, used for jumping out of the locking state when a higher priority reference clock recovers to a fault-free state or the clock loses lock, and when a higher priority reference clock is recovered and the clock loses lock at the same time, the higher priority reference clock is restored preferentially;

[0025] A first holding state unit is used to restore the holding state entered by the higher priority clock, and the holding state of the higher priority clock is restored to output a control signal of the CP terminal, so that the CP is kept in a tri-state, the PLL is kept in an open-loop state, and then a reference clock is selected from high to low according to a preset clock priority table to jump out of the holding state;

[0026] The second holding state unit is used to enter the holding state when the clock fault signal jumps to 1, keep the CP in a tri-state, and output a CP terminal control signal to select other reference clocks and exit the holding state;

[0027] Reset divider unit, used to reset the state of R1 / N1 divider, and control the reset of R1 / N1 divider when the charge pump phase-locked loop changes from open loop to closed loop;

[0028] The DAC auxiliary release unit is used to use the frequency beat of the divided clock of the reference clock to increase the impedance of the drainage path bit by bit, and drain the large charge applied to the potential of the loop filter to the linear regulator through the low-impedance path inside the DAC to reduce the impact on the output frequency of the charge pump phase-locked loop, and complete the DAC auxiliary release in the process of the charge pump phase-locked loop from open loop to closed loop.

[0029] Optionally, the state machine master clock is the main frequency of the entire digital circuit, and the control signal output by the state machine to the analog end includes a charge pump control signal, a DAC analog circuit control signal, and a reset signal of R1 / N1 division.

[0030] Optionally, the locking unit includes:

[0031] The priority recovery subunit is used to preset the clock priority control circuit, monitor in real time whether a higher priority clock is recovered, and if so, enter the holding state of the higher priority clock to complete the switching of the higher priority reference clock;

[0032] The clock unlock subunit is used to enter the holding state of the current clock fault when the flag signal indicating that the phase difference between the divided clock signal of the reference clock and the divided clock signal of the PLL output clock is too large is at a high level, the clock lock flag is unlocked and set to 0, or the clock fails and the clock fault signal is 1.

[0033] Optionally, the PLL control state machine module further includes:

[0034] A clock selection unit, configured to determine whether the current clock has been recovered after a configured clock recovery waiting time, and if so, continue to use the current clock; if not, select a reference clock with a higher priority and no faults according to the clock priority table, and when all clocks are unavailable, maintain the current clock in a fault hold state until a reference clock is recovered;

[0035] The hold state exit unit includes a waiting for zero phase error mode and a DAC auxiliary release mode.

[0036] Optionally, the waiting for zero phase error mode waits for the low phase error flag output by the charge pump phase-locked loop to return to 0, and then the charge pump exits the hold state;

[0037] The DAC auxiliary release mode waits for the clock fault signal of the corresponding channel to be 0, resets the R1 / N1 divider, and diverts the large charge applied to the loop filter potential to the linear regulator through the low impedance path inside the DAC, thereby reducing the impact on the output frequency of the charge pump phase-locked loop, and completing the state exit mode of the DAC auxiliary release.

[0038] The present invention discloses the following technical effects by providing an open-closed loop smooth switching system based on a charge pump phase-locked loop:

[0039] 1. The present invention supports automatic switching of the reference clock of the charge pump phase-locked loop PLL. For example, 4 reference clocks can be configured, and the enable of each clock can be set by the user to be turned off / on, and the priority of the reference clock can be set. If the current clock fails, it can switch to the next priority reference clock. If a higher priority clock is restored, it can also automatically switch back to the higher priority clock.

[0040] 2. The number of clock cycles (a sign for locking) at which the PFD phase error is lower than the threshold value during the locking detection process of the present invention can be configured by the user.

[0041] 3. The reference clock fault detection module (LOSDetector module) of the present invention will identify the fault information of the reference clock as early as possible, and enter the holding state through the PLL control state machine (PLL1 FSM module) before the phase detector PFD1 or charge pump CP1 of the PLL is affected.

[0042] 4. The present invention is in the hold state (clock failure, PLL open loop), because the state is entered due to clock failure, the user can configure to wait for the clock to recover (time can be configured), if the clock is recovered, continue to use this reference clock, if not, select the next priority clock according to the priority table configured by the user in advance

[0043] 5. The present invention proposes two methods for smoothly exiting the PLL open-loop holding state (waiting for zero phase error, DAC auxiliary release) to control the charge pump phase-locked loop PLL to exit the three-state, so as to minimize the phase / frequency drop when the PLL is converted from open-loop to closed-loop.

[0044] 6. The core of the present invention is that after the PLL re-switches the reference clock, the frequency deviation caused by the closed-loop re-locking is restored to be less than 0.15ppm, and the reference clock switching is completed smoothly without affecting the subsequent circuits.

[0045] 7. The present invention supports enabling the DAC circuit to hold when the PLL is in an open-loop holding state, so that the CP terminal voltage is maintained at the average value of the previous closed-loop state.

[0046] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0048] Figure 1 A schematic diagram of a system architecture provided by an embodiment of the present invention;

[0049] Figure 2 A circuit diagram of a charge pump and an open-closed loop smooth switching system provided by an embodiment of the present invention;

[0050] Figure 3 A schematic diagram of state transition of a PLL control state machine provided by an embodiment of the present invention;

[0051] Figure 4 A schematic diagram of a clock selection design process provided by an embodiment of the present invention;

[0052] Figure 5 A schematic diagram of a clock selection logic flow provided by an embodiment of the present invention;

[0053] Figure 6 A schematic diagram of a state transition design process of a digital circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0054] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0055] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0056] like Figure 1-2 As shown, the present invention provides an open-closed loop smooth switching system based on a charge pump phase-locked loop, including a reference clock fault detection module (LOSDetector), a PLL lock detection module (Lock_detect), an ADC / DAC control module (DAC_ctrl) and a PLL control state machine module (PLL1 FSM) connected to the charge pump phase-locked loop.

[0057] 1. Reference clock fault detection module (LOSDetector)

[0058] It is used to detect whether the reference clock fails and control the clock failure flag. The reference clock failure detection module includes:

[0059] The fault judgment unit is used to judge whether two consecutive reference clock rising edges appear within four consecutive master clock rising edges (within three master clock cycles). If not, the reference clock is judged to be faulty and the clock fault signal (los_clkx (x=0 or 1 or 2 or 3)) of the corresponding channel is set to 1.

[0060] The read-only warning unit is used to determine whether two consecutive master clock rising edges appear within four consecutive reference clock rising edges. If not, a read-only warning that the master clock frequency is too low is issued.

[0061] The clock constraints for this module design are: 2 times the reference clock frequency (f_clkinx / 2) < the state machine main clock frequency (f_mainclk) < 2 times the reference clock frequency (f_clkinx*2)

[0062] 2. PLL lock detection module (Lock_detect)

[0063] It is used to determine the phase difference between the divided frequency signal of the reference clock and the divided frequency signal of the charge pump phase-locked loop output clock, and to perform the lock indication control of the phase-locked loop according to the determination result. The PLL lock detection module includes:

[0064] The phase-locked loop locking unit is used for when the phase difference between the divided clock (fref signal) of the reference clock and the divided clock (fdiv) of the PLL output clock is less than 4ns, the phase detector will not output the high-level signal of the flag signal (ph_err) that the phase difference between the fref and fdiv clocks is too large, and the locking counter determines whether the flag signal (ph_err) that the phase difference between the divided clock (fref signal) of the reference clock and the divided clock (fdiv) of the PLL output clock is too large continues to be a low-level signal during the process of continuously counting 2^n cycles of the divided clock (fref signal) of the reference clock, and if so, a phase-locked loop locking indication is issued. The number of continuous counting cycles can be configured according to the PLL loop locking time, and the PLL loop locking time is determined by the loop bandwidth and the parameters of the PLL analog circuit part.

[0065] The lock clearing unit is used to send a clear lock indication when the phase difference between the divided clock signal of the reference clock and the divided clock signal of the PLL output clock is greater than 4ns. The flag signal of excessive phase difference between the divided clock signal of the reference clock and the divided clock signal of the PLL output clock is a high-level signal, and the lock counter is cleared and the charge pump returns to the re-lock counting state.

[0066] 3. ADC / DAC control module (DAC_ctrl)

[0067] It is used to sample the voltage value of the charge pump phase-locked loop, auxiliary hold of the open loop, and auxiliary release from open loop to closed loop. The ADC / DAC control module includes:

[0068] The first auxiliary unit is used to sample the oscillator control voltage value during the closed loop period of the charge pump.

[0069] The second auxiliary unit is used to maintain the frequency stability of the oscillator by using the oscillator control voltage value sampled by the DAC output after the charge pump switches from closed loop to open loop when the reference clock fails.

[0070] 4. PLL control state machine module (PLL1 FSM)

[0071] Figure 3 This is the state transition diagram of the PLL control state machine, such as Figure 3 As shown, the PLL control state machine is used to control the state jump of the charge pump to enter and exit the clock selection hold state. The PLL control state machine module includes:

[0072] 4.1 IDLE

[0073] Idle state, receives the startup signal of the entire system, and enters the initialization state.

[0074] 4.2 Initialization Unit INIT

[0075] Initialization state (preload configuration), according to the register configuration, the control signal output by the initialization state machine FSM to the analog terminal, and the values ​​of each counter in the state machine FSM are reset to 0;

[0076] The state machine master clock is the main frequency of the entire digital circuit, and the reference clock fault detection module (LOSDetector), PLL lock detection module (Lock_detect), ADC / DAC control module (DAC_ctrl) and PLL control state machine module (PLL1 FSM) all work at this frequency. The control signals output by the state machine to the analog end include the charge pump control signal en_up / en_dn, the reset signal of the R1 / N1 divider and the DAC analog circuit control signal.

[0077] 4.3 Locking Count State Unit LOCKING

[0078] It is used to determine whether the phase difference between the divided clock signal of the reference clock and the divided clock signal of the PLL output clock has been less than 4ns during the period when the lock counter continuously counts 2^n divided clock cycles of the reference clock. If so, the clock lock flag output by the PLL lock detection module is 1 and enters the locked state.

[0079] Lock count state, because this state is entered when the clock fault signal (los_clkx) of the corresponding channel is 0 (design guarantee), los_clkx jumps to 1 in extreme cases, jumps to 1 and can enter the HOLDOVER_ERR state according to user configuration, or remain in this state. The clock lock flag (ld_flag) output by the PLL lock detection module (lock_detect module) is 1 to enter the LOCKED state.

[0080] 4.4 Locking unit LOCKED

[0081] Locked state. When there is a higher priority reference clock or the clock is out of lock, it will exit the locked state. When a higher priority reference clock and clock out of lock exist at the same time, the higher priority reference clock will be restored first. The locking unit includes:

[0082] 1) Priority recovery subunit

[0083] This state embeds a clock priority control circuit, which can monitor in real time whether a higher priority clock is recovered. If so, the higher priority hold state HOLDOVER_PRE is entered to complete the switching of the higher priority reference clock.

[0084] 2) Clock lock subunit

[0085] At this time, the analog PFD will output ph_err (a sign that the phase difference between fref and fdiv is too large) square wave pulse, reset the lock counting module (lock_detect module), and the flag (ld_flag) output by this module will be set to 0 when the lock is lost, or the clock fails, and the clock failure signal (los_clkinx) of the corresponding channel output by the reference clock failure detection module (los_detect module) is 1. If either of the two occurs, the HOLDOVER_EER holding state will be entered. The user can also configure not to enter the holding state, and then return to the LOCKING state.

[0086] 4.5 First Hold State Unit HOLDOVER_PRE

[0087] Figure 4 Design a flow chart for clock selection, such as Figure 4As shown, the first holding state unit is used to enter and maintain the restoration of a higher priority state, and the restoration of the higher priority holding state outputs a control signal at the CP end, keeps the CP in a tri-state, and the PLL in an open-loop state, and then selects the clock from high to low according to a preset clock priority table to jump out of the state.

[0088] Because when entering this state, there must be a higher priority clock recovery (the clock failure signal of the corresponding channel los_clkinx = 0), you can jump out of this state by selecting the clock from high to low according to the priority table. In this state, the control signal output at the CP end (en_up is set to 0, en_dn is set to 0) keeps the CP in a tri-state, and the PLL is in an open-loop state.

[0089] 4.6 Second Hold State Unit HOLDOVER_EER

[0090] When the clock fault signal jumps to 1, it enters and maintains the current clock fault state, keeps the CP in three-state, sets the output CP control signal en_up to 0, sets en_dn to 0, keeps the CP in three-state, keeps the PLL in open-loop state, selects other fault-free clocks according to the configuration and exits the hold state.

[0091] Among them, the HOLDOVER_EER state can wait for the clock to recover, and the HOLDOVER_PRE state is entered to switch to a higher priority clock without waiting time.

[0092] 4.7 Reset the divider unit HOLDQUIT_RES

[0093] Used to reset the R1 / N1 divider state, and after resetting the divider, control the charge pump from open loop to closed loop.

[0094] 4.8DAC auxiliary release unit HOLDQUIT_DAC

[0095] It is used to utilize the frequency beat of the divided clock of the reference clock to increase the impedance of the drainage path bit by bit, and drain the large charge applied to the potential of the loop filter to the linear regulator through the low-impedance path inside the DAC to reduce the impact on the output frequency of the charge pump phase-locked loop, and complete the DAC-assisted release of the charge pump phase-locked loop from open loop to closed loop.

[0096] 4.9 Clock Selection Unit

[0097] Figure 5 Select the logic flow chart for the clock, such as Figure 5As shown, if the hold state is entered due to a clock failure, the user can configure to wait for the clock to recover (the time is configurable). After waiting for the configured time, it is determined whether the current clock is recovered. If it is, the current clock continues to be used. If it is not, a clock with a higher priority and no fault is selected according to the clock priority table. When all clocks are unavailable, the current hold state is maintained until a clock is recovered.

[0098] 4.10 Exit unit in hold state

[0099] Figure 6 Design a flow chart for the state flow of a digital circuit, such as Figure 6 As shown, the hold state exit unit includes a waiting for zero phase error mode and a DAC auxiliary release mode.

[0100] 1) Waiting for zero phase error mode

[0101] Wait for the clock fault signal (los_clkx) of the corresponding channel to be 0 and the low phase error of the PFD. The PLL will output a low phase error flag (cycleslip). The reason for the cycleslip is that fref and fdiv have a frequency difference. Whether the fref frequency is slightly greater than the fdiv frequency, or the fref frequency is slightly less than the fdiv frequency, the rising edges of both will produce a process from slightly lagging (or leading) to slightly leading (or lagging). This process is the pulse width time of the cycleslip. Therefore, waiting for the cycleslip to return to 0 and then letting the PLL exit the hold state can charge the hold voltage (vtune voltage) of the ADC / DAC control module for a short period of time (or help the vtune voltage to discharge a small period of time), which helps to make the fdiv frequency converge to the fref frequency faster in the subsequent locking cycle.

[0102] 2) DAC assisted release method

[0103] Wait for the clock fault signal (los_clkx) of the corresponding channel to be 0, reset the R1 / N1 divider, and release the DAC auxiliary. The exit method of DAC auxiliary release can drain the large charge applied to the loop filter potential to the linear regulator through the low impedance path inside the DAC to reduce the impact on the charge pump PLL output frequency (f_vcxo). Use the frequency beat of fref to increase the impedance of this drainage path bit by bit.

[0104] Therefore, the present invention provides an open-closed loop smooth switching system based on a charge pump phase-locked loop, which can monitor the active reference clock of the charge pump phase-locked loop, identify fault information as early as possible, and put the charge pump into the three-state in advance. At this time, the PLL switches from the closed loop to the open loop state. When the reference clock is stable, the present invention controls the charge pump phase-locked loop to exit the holding state. At this time, the PLL switches from the open loop state to the closed loop state. In the process, the charge pump re-acquires the reference clock (from open loop to closed loop) and the deviation from the initial frequency value is less than 0.15ppm, and the switching is completed smoothly without affecting the subsequent circuits.

[0105] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0106] The principles and implementation methods of the present invention are described in this article using specific examples. The description of the above embodiments is only used to help understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. An open-closed loop smooth switching system based on a charge pump phase-locked loop, characterized in that: It includes a reference clock fault detection module connected to a charge pump phase-locked loop, a PLL lock detection module, an ADC / DAC control module and a PLL control state machine module; The reference clock fault detection module is used to detect whether the reference clock fails and perform fault indication control of the reference clock; The PLL lock detection module is used to perform lock indication control of the phase-locked loop according to the phase difference between the frequency-divided signal of the reference clock and the frequency-divided signal of the charge pump phase-locked loop output clock; The ADC / DAC control module is used for assisting the charge pump open loop maintenance and assisting the charge pump phase-locked loop release from open loop to closed loop; The PLL control state machine module is used to control the state machine to perform clock selection, entry into a hold state, and exit from a hold state, thereby realizing control of the open-loop and closed-loop indications of the charge pump phase-locked loop.

2. The open-closed loop smooth switching system based on a charge pump phase-locked loop according to claim 1, characterized in that: The reference clock fault detection module comprises: A clock constraint unit, used for setting the reference clock frequency that needs to be greater than 1 / 2 times the main clock frequency as a first clock constraint, and setting the main clock frequency that needs to be greater than 1 / 2 times the reference clock frequency as a second clock constraint; A fault judgment unit is used to judge whether two consecutive reference clock rising edges appear within four consecutive master clock rising edges. If not, the reference clock is judged to be faulty and the clock fault signal of the corresponding channel is set to 1; The read-only warning unit is used to determine whether two consecutive master clock rising edges appear within four consecutive reference clock rising edges. If not, a read-only warning that the master clock frequency is too low is issued.

3. The open-closed loop smooth switching system based on a charge pump phase-locked loop according to claim 2, characterized in that: The PLL lock detection module comprises: A phase-locked loop locking unit, used for determining whether a flag signal indicating that the phase difference between the divided clock signal of the reference clock and the divided clock signal of the PLL output clock is too large is a continuous low-level signal during the period when the locking counter continuously counts 2^n divided clock cycles of the reference clock when the phase difference between the divided clock signal of the reference clock and the divided clock signal of the PLL output clock is less than 4ns, and if so, issuing a phase-locked loop locking indication; The lock clearing unit is used to send a clear lock indication when the phase difference between the divided clock signal of the reference clock and the divided clock signal of the PLL output clock is greater than 4ns, and the flag signal of the excessive phase difference between the divided clock signal of the reference clock and the divided clock signal of the PLL output clock is a high-level signal. The lock counter is cleared and the charge pump phase-locked loop returns to the re-lock counting state.

4. The open-closed loop smooth switching system based on a charge pump phase-locked loop according to claim 3, characterized in that: The ADC / DAC control module comprises: A first auxiliary unit is used to sample the oscillator control voltage value during the closed loop period of the charge pump phase-locked loop; The second auxiliary unit is used to maintain the frequency stability of the oscillator by using the oscillator control voltage value sampled by the DAC output after the charge pump switches from a closed loop to an open loop.

5. The open-closed loop smooth switching system based on a charge pump phase-locked loop according to claim 4, characterized in that: The PLL control state machine module comprises: The idle unit is used to receive the start signal of the entire system and enter the initialization state; An initialization unit, used for preloading configuration, initializing the control signal output by the state machine main clock to the analog terminal according to the register configuration, and resetting each counter in the state machine to 0; A lock counting state unit, used to determine whether the phase difference between the divided clock signal of the reference clock and the divided clock signal of the PLL output clock is continuously less than 4ns during the period when the lock counter continuously counts 2^n divided clock cycles of the reference clock. If so, the clock lock flag output by the PLL lock detection module is 1, and the PLL enters a lock state; A locking unit, used for jumping out of the locking state when a higher priority reference clock recovers to a fault-free state or the clock loses lock, and when a higher priority reference clock is recovered and the clock loses lock at the same time, the higher priority reference clock is restored preferentially; A first holding state unit is used to restore the holding state entered by the higher priority clock, and the holding state of the higher priority clock is restored to output a control signal of the CP terminal, so that the CP is kept in a tri-state, the PLL is kept in an open-loop state, and then a reference clock is selected from high to low according to a preset clock priority table to jump out of the holding state; The second holding state unit is used to enter the holding state when the clock fault signal jumps to 1, keep the CP in a tri-state, and output a CP terminal control signal to select other reference clocks and exit the holding state; Reset divider unit, used to reset the state of R1 / N1 divider, and control the reset of R1 / N1 divider when the charge pump phase-locked loop changes from open loop to closed loop; The DAC auxiliary release unit is used to use the frequency beat of the divided clock of the reference clock to increase the impedance of the drainage path bit by bit, and drain the large charge applied to the potential of the loop filter to the linear regulator through the low-impedance path inside the DAC to reduce the impact on the output frequency of the charge pump phase-locked loop, and complete the DAC auxiliary release in the process of the charge pump phase-locked loop from open loop to closed loop.

6. The open-closed loop smooth switching system based on a charge pump phase-locked loop according to claim 5, characterized in that: The state machine master clock is the main frequency of the entire digital circuit. The control signal output by the state machine to the analog terminal includes a charge pump control signal, a DAC analog circuit control signal and a reset signal of R1 / N1 division.

7. The open-closed loop smooth switching system based on a charge pump phase-locked loop according to claim 6, characterized in that: The locking unit comprises: The priority recovery subunit is used to preset the clock priority control circuit, monitor in real time whether a higher priority clock is recovered, and if so, enter the holding state of the higher priority clock to complete the switching of the higher priority reference clock; The clock unlock subunit is used to enter the holding state of the current clock fault when the flag signal indicating that the phase difference between the divided clock signal of the reference clock and the divided clock signal of the PLL output clock is too large is at a high level, the clock lock flag is unlocked and set to 0, or the clock fails and the clock fault signal is 1.

8. The open-closed loop smooth switching system based on a charge pump phase-locked loop according to claim 7, characterized in that: The PLL control state machine module also includes: A clock selection unit, configured to determine whether the current clock has been recovered after a configured clock recovery waiting time, and if so, continue to use the current clock; if not, select a reference clock with a higher priority and no faults according to the clock priority table, and when all clocks are unavailable, maintain the current clock in a fault hold state until a reference clock is recovered; The hold state exit unit includes a waiting for zero phase error mode and a DAC auxiliary release mode.

9. The open-closed loop smooth switching system based on a charge pump phase-locked loop according to claim 8, characterized in that: The waiting for zero phase error mode waits for the low phase error flag output by the charge pump phase-locked loop to return to 0, and then the charge pump exits the hold state; The DAC auxiliary release mode waits for the clock fault signal of the corresponding channel to be 0, resets the R1 / N1 divider, and diverts the large charge applied to the loop filter potential to the linear regulator through the low impedance path inside the DAC, thereby reducing the impact on the output frequency of the charge pump phase-locked loop, and completing the state exit mode of the DAC auxiliary release.

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