GaN-based enhanced HEMT device structure and manufacturing method thereof

Abstract

The invention provides a GaN-based enhanced HEMT (High Electron Mobility Transistor) device structure and a manufacturing method thereof, a barrier stack comprises a first insertion layer, a first barrier layer, a second insertion layer, a second barrier layer, a third insertion layer and a third barrier layer which are sequentially stacked from bottom to top, the second insertion layer is used as an etching stop layer during groove etching, and the third insertion layer is used as an etching stop layer during groove etching. The thickness of the barrier layer in the groove region is reduced, so that the 2DEG concentration below the P-type GaN part can be reduced, and the threshold voltage of the device is improved; the third insertion layer is used as an etching stop layer when the P-type GaN layer is patterned, so that the over-etching depth of the barrier layer can be reduced, the retention thickness of the barrier layer can be improved, and the probability that electrons tunnel to the surface of the barrier layer can be reduced; due to the existence of the third barrier layer, the third insertion layer can be effectively prevented from being etched through, direct contact between the passivation layer and the second barrier layer is avoided, and interface traps can be further reduced. According to the invention, the optimization of the surface defects of the thick barrier layer and the barrier layer is realized, and the improvement of the performance and reliability of the device is facilitated.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductors and relates to a GaN-based enhanced HEMT device structure and a manufacturing method thereof. Background Art

[0002] Gallium nitride (GaN) high electron mobility transistor (HEMT) is an advanced power semiconductor device based on gallium nitride materials, which has the characteristics of high electron mobility, high power density, small size and high integration. GaN HEMT uses the AlGaN / GaN heterostructure. Through the piezoelectric effect generated when growing AlGaN film on GaN, a large number of electrons gather at the interface to form a high-mobility two-dimensional electron gas (2DEG) layer, which serves as a current path. Due to the high mobility of the two-dimensional electron gas, the on-resistance of GaN HEMT is smaller, and the output capacitance and gate capacitance are also smaller, which enables it to have higher switching speed and lower switching loss in high-frequency applications.

[0003] GaN-based HEMT devices are divided into ordinary and enhanced modes. Ordinary GaN-based HEMT devices are usually depletion mode (D-mode), which means that when no voltage is applied to the gate, the device is already in the on state, because the 2DEG generated at the AlGaN / GaN interface allows the device to conduct even at zero gate bias, while the enhanced GaN-based HEMT device is normally off (E-mode). When the gate is zero biased, the device is off and a positive gate voltage needs to be applied to turn on the device. The structural feature of the enhanced GaN HEMT device is that a layer of P-type GaN layer is grown on the top of the AlGaN barrier layer. The positive charge in this layer of P-GaN has a built-in voltage that is greater than the voltage generated by the piezoelectric effect, so it depletes the electrons in the 2DEG to form an enhanced structure. The advantage of this structure is that the internal parasitic parameters are small and the switching performance is better. Since the enhanced GaN HEMT can deplete the 2DEG in the channel under the gate at zero gate bias, making the device in the off state, they have the advantages of safety, energy saving and simplified circuit design, and are an important development direction for future power devices.

[0004] The current collapse phenomenon is one of the serious problems that currently affect the reliability of GaN HEMTs, which leads to a decrease in the device's saturation current and maximum transconductance, and an increase in on-resistance. A large number of experimental analyses have found that the thickness and surface defects of the GaN barrier layer have a significant effect on the current collapse phenomenon. Increasing the thickness of the barrier layer can reduce electron tunneling to the surface, reduce surface traps in the barrier layer, and reduce the probability of electron capture. However, an increase in the thickness of the barrier layer will lead to a decrease in the threshold voltage. This can lead to misconduction in applications, and it is also very difficult to reduce surface traps simply through process.

[0005] Therefore, how to provide a GaN-based enhanced HEMT device structure and a manufacturing method thereof to achieve optimization of the thick barrier layer and the surface defects of the barrier layer has become an important technical problem that needs to be solved urgently by those skilled in the art.

[0006] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and facilitating the understanding of those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0007] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a GaN-based enhancement mode HEMT device structure and a manufacturing method thereof, so as to solve the problems of unstable threshold voltage and more surface defects in the existing GaN-based enhancement mode HEMT device structure.

[0008] To achieve the above-mentioned and other related purposes, the present invention provides a method for manufacturing a GaN-based enhancement-mode HEMT device structure, comprising the following steps:

[0009] Providing a substrate, wherein one side of the substrate has a channel layer, wherein the channel layer includes an undoped GaN layer;

[0010] forming a barrier stack on the channel layer, the barrier stack comprising a first insertion layer, a first barrier layer, a second insertion layer, a second barrier layer, a third insertion layer and a third barrier layer stacked in sequence from bottom to top;

[0011] Performing etching to form a trench in the barrier stack, wherein the bottom of the trench stops at the second insertion layer;

[0012] forming a P-type GaN layer, wherein the P-type GaN layer covers the top surface of the barrier stack and the inner wall of the trench;

[0013] Etching to pattern the P-type GaN layer to obtain a P-type GaN portion, wherein the P-type GaN portion at least covers the bottom wall of the trench, and the etched area around the P-type GaN portion stops at the third insertion layer;

[0014] forming a passivation layer, the passivation layer covering the P-type GaN portion and covering the exposed surface of the third insertion layer;

[0015] A gate electrode and a source electrode and a drain electrode respectively located at both sides of the gate electrode are formed. The gate electrode penetrates the passivation layer and contacts the P-type GaN portion. The source electrode and the drain electrode penetrate the passivation layer and contact the third insertion layer.

[0016] Optionally, the first insertion layer, the second insertion layer and the third insertion layer all include AlN layers, and the first barrier layer, the second barrier layer and the third barrier layer all include AlGaN layers.

[0017] Optionally, the barrier stack has a thickness ranging from 12 to 20 nm.

[0018] Optionally, the thickness of the first insertion layer is in the range of 0.1 to 1 nm, the thickness of the second insertion layer is in the range of 0.3 to 1.5 nm, and the thickness of the third insertion layer is in the range of 0.3 to 1.5 nm.

[0019] Optionally, the passivation layer includes an AlN layer.

[0020] Optionally, the method of forming the barrier stack includes a MOCVD method.

[0021] Optionally, the P-type GaN portion includes a P-type GaN main portion located on the inner wall of the groove and a P-type GaN side portion extending horizontally from the top of the P-type GaN main portion to both sides, and a supporting portion formed by a portion of the third barrier layer is provided between the P-type GaN side portion and the third insertion layer.

[0022] Optionally, the substrate includes a substrate layer, a nucleation layer, a buffer layer and a C-doped GaN layer arranged in sequence from bottom to top.

[0023] Optionally, the substrate layer includes a Si layer, the nucleation layer includes an AlN layer, and the buffer layer includes an AlGaN-AlN superlattice layer.

[0024] The present invention also provides a GaN-based enhanced HEMT device structure, comprising:

[0025] A substrate, one side of the substrate having a channel layer, wherein the channel layer comprises an undoped GaN layer;

[0026] A barrier stack, located on the channel layer and comprising at least a first insertion layer, a first barrier layer, a second insertion layer, a second barrier layer and a third insertion layer stacked in sequence from bottom to top;

[0027] a groove opening from the top surface of the barrier stack and extending downward to the second insertion layer;

[0028] A P-type GaN portion at least covers the bottom wall of the trench, and a top layer of the barrier stack around the P-type GaN portion is the third insertion layer;

[0029] a passivation layer covering the P-type GaN portion and covering the third insertion layer around the P-type GaN portion;

[0030] A gate electrode and a source electrode and a drain electrode respectively located at both sides of the gate electrode, the gate electrode penetrates the passivation layer and contacts the P-type GaN portion, the source electrode and the drain electrode penetrate the passivation layer and contact the third insertion layer.

[0031] Optionally, the first insertion layer, the second insertion layer and the third insertion layer all include AlN layers, and the first barrier layer and the second barrier layer all include AlGaN layers.

[0032] Optionally, the barrier stack has a thickness ranging from 12 to 20 nm.

[0033] Optionally, the thickness of the first insertion layer is in the range of 0.1 to 1 nm, the thickness of the second insertion layer is in the range of 0.3 to 1.5 nm, and the thickness of the third insertion layer is in the range of 0.3 to 1.5 nm.

[0034] Optionally, the passivation layer includes an AlN layer.

[0035] Optionally, the P-type GaN portion includes a P-type GaN main portion located on the inner wall of the groove and a P-type GaN side portion extending horizontally from the top of the P-type GaN main portion to both sides, and the barrier stack also includes a third barrier layer located on the third insertion layer, and a support portion formed by the third barrier layer is provided between the P-type GaN side portion and the third insertion layer.

[0036] Optionally, the substrate includes a substrate layer, a nucleation layer, a buffer layer and a C-doped GaN layer arranged in sequence from bottom to top.

[0037] Optionally, the substrate layer includes a Si layer, the nucleation layer includes an AlN layer, and the buffer layer includes an AlGaN-AlN superlattice layer.

[0038] As described above, in the GaN-based enhanced HEMT device structure and the manufacturing method thereof of the present invention, the barrier stack includes a first insertion layer, a first barrier layer, a second insertion layer, a second barrier layer, a third insertion layer and a third barrier layer stacked in sequence from bottom to top, wherein the second insertion layer is used as an etching stop layer during trench etching, and the thickness of the barrier layer in the trench region becomes smaller, which can reduce the 2DEG concentration under the P-type GaN part, thereby increasing the threshold voltage of the device; the third insertion layer is used as an etching stop layer during patterning of the P-type GaN layer, which can reduce the over-etching depth of the barrier layer, increase the remaining thickness of the barrier layer, and reduce the probability of electron tunneling to the surface of the barrier layer, thereby reducing the surface traps of the barrier layer and reducing the probability of electrons being captured; the presence of the third barrier layer can effectively prevent the third insertion layer from being etched through, avoid direct contact between the passivation layer and the second barrier layer, and can further reduce interface traps. In short, the present invention realizes the optimization of thick barrier layers and surface defects of barrier layers, which helps to improve the performance and reliability of devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 Shown is a schematic diagram of a GaN HEMT structure.

[0040] Figure 2 Shown as an electron tunneling from a 2D electron gas to a surface trap.

[0041] Figure 3 The process flow chart shows the method for manufacturing the GaN-based enhancement mode HEMT device structure of the present invention.

[0042] Figure 4 A schematic structural diagram showing a substrate provided for the method for manufacturing a GaN-based enhanced HEMT device structure of the present invention.

[0043] Figure 5 It is a schematic diagram showing the structure obtained after forming a barrier stack on a channel layer according to the manufacturing method of the GaN-based enhancement mode HEMT device structure of the present invention.

[0044] Figure 6 It is a schematic diagram showing the structure obtained after forming a trench in the barrier stack according to the method for manufacturing the GaN-based enhancement mode HEMT device structure of the present invention.

[0045] Figure 7 It is a schematic diagram showing the structure obtained after forming a P-type GaN layer according to the method for manufacturing a GaN-based enhancement-mode HEMT device structure of the present invention.

[0046] Figure 8 It is a schematic diagram showing the structure obtained after patterning the P-type GaN layer in the method for manufacturing the GaN-based enhancement-mode HEMT device structure of the present invention.

[0047] Fig. 9It is a schematic diagram showing the structure obtained after forming a passivation layer according to the method for manufacturing a GaN-based enhanced HEMT device structure of the present invention.

[0048] Fig.10 It is a schematic diagram showing the structure obtained after forming the gate electrode, the source electrode and the drain electrode according to the manufacturing method of the GaN-based enhancement mode HEMT device structure of the present invention.

[0049] Description of Reference Numerals

[0050] 101 Si substrate layer

[0051] 102 Nucleation layer

[0052] 103 stress relief layer

[0053] 104 C-doped GaN layer

[0054] 105 Undoped GaN layer

[0055] 106 AlGaN barrier layer

[0056] 107 P-type GaN layer

[0057] 108 Passivation layer

[0058] 109 Gate electrode

[0059] 110 source electrode

[0060] 111 Drain electrode

[0061] 112 Two-dimensional electron gas

[0062] 113, 114, 115 Charge carriers

[0063] 116 Surface Trap

[0064] Steps S1 to S7

[0065] 201 substrate layer

[0066] 202 Nucleation layer

[0067] 203 Buffer layer

[0068] 204 C-doped GaN layer

[0069] 205 Channel Layer

[0070] 206 Barrier stack

[0071] 2061 First insertion layer

[0072] 2062 The First Barrier Layer

[0073] 2063 Second insertion layer

[0074] 2064 Second Barrier Layer

[0075] 2065 The third insertion layer

[0076] 2066 The Third Barrier Layer

[0077] 207 Groove

[0078] 208 P-type GaN layer

[0079] 208a P-type GaN

[0080] 2081 P-type GaN body

[0081] 2082 P-type GaN side

[0082] 209 Passivation layer

[0083] 210 Gate electrode

[0084] 211 Source electrode

[0085] 212 Drain electrode DETAILED DESCRIPTION

[0086] See also Figure 1 , which is a schematic diagram of a GaN HEMT structure, includes a Si substrate layer 101, a nucleation layer 102, a stress release layer 103 (also called a buffer layer), a C-doped GaN layer 104, an undoped GaN layer 105, an AlGaN barrier layer 106, a P-type GaN layer 107, a passivation layer 108, a gate electrode 109, a source electrode 110 and a drain electrode 111, wherein the undoped GaN layer 105 serves as a channel layer, and the AlGaN barrier layer 106 and the undoped GaN layer 105 form a heterostructure, and a two-dimensional electron gas 112 with high electron mobility can be generated at the interface between the two.

[0087] Figure 1 The source contact resistance R C,S , source access resistor R AC,S , channel resistance R CH , Drain access resistor R AC,D Contact resistance with drain R C,D .exist Figure 1 In the structure shown, the dynamic on-resistance (Dynamic R on There are three main factors:

[0088] (1) Buffer trapping: In the buffer layer, charge carriers may be trapped, affecting device performance. Figure 1 Schematically illustrates the charge carriers 113 trapped on the surface of the stress release layer 103;

[0089] (2) Gate instability: Gate instability may be related to the fluctuation of gate voltage, resulting in the threshold voltage (V TH ) changes △V TH ,in, Figure 1 Schematically illustrates the charge carriers 114 at the interface between the AlGaN barrier layer 106 and the P-type GaN layer 107;

[0090] (3) Surface trapping: On the device surface, charge carriers may be trapped by surface states, affecting the device's conduction performance. Figure 1 The charge carriers 115 at the interface between the AlGaN barrier layer 106 and the passivation layer 108 are shown in FIG. Figure 2 , showing a process of an electron e- tunneling from a two-dimensional electron gas (2DEG) to a surface trap 116 (trap). This is because there may be some defects on the surface of the AlGaN / GaN heterostructure, which can capture or release electrons as surface traps 116. When the electron e- is captured by the surface trap 116, the electron concentration in the 2DEG will decrease, which will increase the on-resistance of the device. In addition, spontaneous radiation (SRL) will be generated when electrons and holes recombine.

[0091] After extensive analysis and research, the inventors of the present application optimized the factors that may lead to an increase in dynamic on-resistance when designing and manufacturing the GaN-based enhancement-mode HEMT device structure, which helps to improve the performance and reliability of the device.

[0092] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0093] It should be emphasized that the term “include / comprises” when used herein refers to the presence of features, integers, steps or components, but does not exclude the presence or addition of one or more other features, integers, steps or components.

[0094] Features described and / or illustrated with respect to one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0095] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the schematic diagrams showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0096] For ease of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0097] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0098] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0099] The present invention provides a method for manufacturing a GaN-based enhanced HEMT device structure. Figure 3 , shown as a process flow chart of the method, comprising the following steps:

[0100] S1: providing a substrate, wherein one side of the substrate has a channel layer, and the channel layer includes an undoped GaN layer;

[0101] S2: forming a barrier stack on the channel layer, wherein the barrier stack includes a first insertion layer, a first barrier layer, a second insertion layer, a second barrier layer, a third insertion layer and a third barrier layer stacked sequentially from bottom to top;

[0102] S3: performing etching to form a trench in the barrier stack, wherein the bottom of the trench stops at the second insertion layer;

[0103] S4: forming a P-type GaN layer, wherein the P-type GaN layer covers the top surface of the barrier stack and the inner wall of the trench;

[0104] S5: performing etching to pattern the P-type GaN layer to obtain a P-type GaN portion, wherein the P-type GaN portion at least covers the bottom wall of the trench, and the etched area around the P-type GaN portion stops at the third insertion layer;

[0105] S6: forming a passivation layer, wherein the passivation layer covers the P-type GaN portion and covers the exposed surface of the third insertion layer;

[0106] S7: forming a gate electrode and a source electrode and a drain electrode respectively located on both sides of the gate electrode, wherein the gate electrode penetrates the passivation layer and contacts the P-type GaN portion, and the source electrode and the drain electrode penetrate the passivation layer and contact the third insertion layer.

[0107] The above steps will be described in detail below with reference to the structural diagram.

[0108] First see Figure 4 , performing the step S1: providing a substrate, one side of the substrate having a channel layer 205, and the channel layer 205 includes an undoped GaN layer (Undoped GaN).

[0109] Specifically, the channel layer 205 uses an undoped GaN layer to reduce impurity scattering, thereby improving the mobility of electrons, and helps to reduce leakage current in the device and improve the turn-off characteristics of the device.

[0110] As an example, the substrate includes a substrate layer 201 , a nucleation layer 202 , a buffer layer 203 and a C-doped GaN layer 204 arranged in sequence from bottom to top, wherein the channel layer 205 is located on the surface of the C-doped GaN layer 204 .

[0111] Specifically, the nucleation layer 202 is used to promote crystal growth, the buffer layer 203 is used to reduce stress caused by lattice mismatch, and the C-doped GaN layer 204 is used as a high resistance layer to reduce leakage of the device.

[0112] In some embodiments, the substrate layer 201 includes a Si layer, the nucleation layer 202 includes an AlN layer, and the buffer layer 203 includes an AlGaN-AlN superlattice layer (SL for short).

[0113] Specifically, the AlGaN-AlN superlattice layer is composed of alternating AlGaN layers and AlN layers. This structure helps to suppress the accumulation of internal strain, create a high-insulation buffer layer with good crystal quality, and reduce defects in the buffer layer, thereby helping to reduce the dynamic on-resistance of the device and enable the device to have low parasitic leakage current under high-voltage bias.

[0114] Specifically, the thickness of each layer in the substrate can be set according to actual needs and should not unduly limit the protection scope of the present invention. In one embodiment of the present invention, the thickness of the substrate layer 201 is about 1 mm, the thickness of the nucleation layer 202 is about 200 nm, the thickness of the buffer layer 203 is about 4 μm, and the average thickness of the C-doped GaN layer 204 is about 1 μm.

[0115] Please see again Figure 5 , perform the step S2: form a barrier stack 206 on the channel layer 205, the barrier stack including a first insertion layer 2061, a first barrier layer 2062, a second insertion layer 2063, a second barrier layer 2064, a third insertion layer 2065 and a third barrier layer 2066 stacked in sequence from bottom to top.

[0116] Specifically, the first insertion layer 2061 is located between the channel layer 205 and the first barrier layer 2062 , which helps to improve the mobility of two-dimensional electron gas (2DEG).

[0117] As an example, the first insertion layer 2061 , the second insertion layer 2063 , and the third insertion layer 2065 all include AlN layers, and the first barrier layer 2062 , the second barrier layer 2064 , and the third barrier layer 2066 all include AlGaN layers.

[0118] As an example, the thickness range of the barrier stack 206 is 12 to 20 nm, that is, the total thickness range of the first insertion layer 2061, the first barrier layer 2062, the second insertion layer 2063, the second barrier layer 2064, the third insertion layer 2065 and the third barrier layer 2066 is 12 to 20 nm.

[0119] As an example, the thickness of the first insertion layer 2061 is in the range of 0.1 to 1 nm, the thickness of the second insertion layer 2063 is in the range of 0.3 to 1.5 nm, and the thickness of the third insertion layer 2065 is in the range of 0.3 to 1.5 nm.

[0120] In one embodiment of the present invention, the total thickness of the barrier stack 206 is about 16 nm, wherein the thickness of the first insertion layer 2061 is about 0.3 nm, the thickness of the second insertion layer 2063 is about 0.5 nm, and the thickness of the third insertion layer 2065 is about 0.5 nm.

[0121] As an example, the method for forming the barrier stack includes metal organic chemical vapor deposition (MOCVD), which is an epitaxial technology for growing semiconductor materials, particularly suitable for growing III-V compound semiconductor materials, and can provide high-precision, high-purity, high-uniformity and high-repeatability thin film growth. The resulting thin film has low thermal defects and intrinsic impurities, and the film thickness can be controlled with atomic-level precision.

[0122] Please see again Figure 6 , perform the step S3: perform etching to form a trench 207 in the barrier stack 206 , and the bottom of the trench 207 stops at the second insertion layer 2063 .

[0123] As an example, the trench 207 is formed in the barrier stack 206 by semiconductor processes such as photolithography and etching. During the trench etching process, the second insertion layer 2063 serves as an etching stop layer.

[0124] Specifically, the groove 207 can reduce the thickness of the barrier layer in the gate region, thereby helping to reduce the 2DEG concentration under the P-type GaN portion, thereby increasing the threshold voltage of the device, while the area around the groove 207 still has a thicker barrier layer thickness, thereby having a higher 2DEG concentration. Moreover, since the barrier layer in the area around the groove 207 is thicker, it can reduce electron tunneling to the surface, reduce barrier layer surface traps, and reduce the probability of electrons being captured.

[0125] Please see again Figure 7 , executing the step S4: epitaxially growing a P-type GaN layer 208 , wherein the P-type GaN layer 208 covers the top surface of the barrier stack 206 and the inner wall of the trench 207 .

[0126] Specifically, the inner wall of the groove 207 mentioned in the present invention includes the bottom wall and the side wall of the groove 207 .

[0127] As an example, the growth thickness of the P-type GaN layer 208 is in the range of 0.5 to 1.5 micrometers, for example, 0.8 micrometers.

[0128] Please see again Figure 8, execute the step S5: perform etching to pattern the P-type GaN layer 208 to obtain a P-type GaN portion 208a, wherein the P-type GaN portion 208a at least covers the bottom wall of the groove 207, and the etched area around the P-type GaN portion 208a stops at the third insertion layer 2065.

[0129] As an example, the P-type GaN layer 208 is patterned by semiconductor processes such as photolithography and etching. During the etching of the P-type GaN layer 208, the third insertion layer 2065 serves as an etching stop layer, which can reduce the over-etching depth of the barrier layer, increase the retained thickness of the barrier layer, and reduce the probability of electron tunneling to the surface of the barrier layer, thereby reducing the surface traps of the barrier layer and reducing the probability of electrons being captured.

[0130] It should be pointed out that, although the third insertion layer 2065 serves as an etching stop layer in the process of patterning the P-type GaN layer 208, it is found that it is easily etched through in the actual production process. The present invention adds the third barrier layer 2066 on the third insertion layer 2065. In the process of etching the P-type GaN layer 208, the presence of the third barrier layer 2066 on the third insertion layer 2065 can effectively prevent the third insertion layer 2065 from being etched through, thereby avoiding direct contact between the subsequently formed passivation layer and the second barrier layer 2064, which can further reduce interface traps and improve device performance.

[0131] In some embodiments, the P-type GaN portion 208a is only located in the groove 207. In other embodiments, by controlling the photolithography image, the P-type GaN portion 208a obtained after etching includes not only a P-type GaN main body portion 2081 located on the inner wall of the groove 207, but also a P-type GaN side wing portion 2082 extending horizontally from the top of the P-type GaN main body portion 2081 to both sides. At this time, a supporting portion formed by a portion of the third barrier layer 2066 is provided between the P-type GaN side wing portion 2082 and the third insertion layer 2065, which helps to improve the stability of the gate region pattern and make the threshold voltage of the device more stable.

[0132] Please see again Fig. 9 , performing the step S6: forming a passivation layer 209 , wherein the passivation layer 209 covers the P-type GaN portion 208 a and covers the exposed surface of the third insertion layer 2065 .

[0133] Specifically, the passivation layer 209 is used to protect the device surface and reduce the influence of surface states.

[0134] In some embodiments, the passivation layer 209 includes an AlN layer, and the method for forming the passivation layer 209 includes an MOCVD method. Since the passivation layer 209 and the third insertion layer 2065 both use an AlN layer, that is, they use the same material, the passivation layer 209 is in direct contact with the third insertion layer 2065 rather than directly contacting the second barrier layer 2064, which is more helpful to improve interface traps.

[0135] Please see again Fig.10 , perform step S7: form a gate electrode 210 and a source electrode 211 and a drain electrode 212 respectively located on both sides of the gate electrode 210, the gate electrode 210 penetrates the passivation layer 209 and contacts the P-type GaN portion 208a, the source electrode 211 and the drain electrode 213 penetrate the passivation layer 209 and contact the third insertion layer 2065.

[0136] As an example, a contact hole is first formed at the corresponding position of the passivation layer 209 by semiconductor processes such as photolithography and etching, and then a metal layer is deposited and patterned to obtain the gate electrode 210, the source electrode 211 and the drain electrode 213. The spacing distance between the gate electrode 210 and the source electrode 211 and the spacing distance between the gate electrode 210 and the drain electrode 213 can be set according to the performance parameter requirements of the actual device, and no specific limitation is made in the present invention.

[0137] At this point, a GaN-based enhanced HEMT device structure is manufactured. The manufacturing method of the GaN-based enhanced HEMT device structure of the present invention utilizes multiple insertion layers combined with epitaxial regrowth to achieve the optimization of the thick barrier layer and the surface defects of the barrier layer, wherein the thick barrier layer reduces the probability of electron tunneling to the surface of the barrier layer, and the contact between the passivation layer and the third insertion layer can greatly reduce surface traps.

[0138] The present invention also provides a GaN-based enhanced HEMT device structure, which can be prepared by the above method.

[0139] For details, please refer to Fig.10The GaN-based enhanced HEMT device structure includes a substrate, a barrier stack 206, a groove 207, a P-type GaN portion 208a, a passivation layer 209, a gate electrode 210, and a source electrode 211 and a drain electrode 212 respectively located on both sides of the gate electrode 210, wherein one side of the substrate has a channel layer 205, the channel layer 205 includes an undoped GaN layer, the barrier stack 206 is located on the channel layer 205 and at least includes a first insertion layer 2061, a first barrier layer 2062, a second insertion layer 2063, a second barrier layer 2064 and a third insertion layer 2065 stacked in sequence from bottom to top, the groove 207 is formed from the barrier stack 206. The top surface of the barrier stack 206 is open and extends downward to the second insertion layer 2063, the P-type GaN portion 208a at least covers the bottom wall of the groove 207, the top layer of the barrier stack 206 around the P-type GaN portion 208a is the third insertion layer 2065, the passivation layer covers the P-type GaN portion 208a and covers the third insertion layer 2065 around the P-type GaN portion 208a, the gate electrode 210 penetrates the passivation layer 209 and contacts the P-type GaN portion 208a, the source electrode 211 and the drain electrode 212 penetrate the passivation layer 209 and contact the third insertion layer 2065.

[0140] In some embodiments, the P-type GaN portion 208a is only located in the groove 207. In other embodiments, the P-type GaN portion 208a includes not only a P-type GaN main portion 2081 located on the inner wall of the groove 207, but also a P-type GaN side portion 2082 extending horizontally from the top of the P-type GaN main portion 2081 to both sides. The barrier stack 206 also includes a third barrier layer 2066 located on the third insertion layer 2065. At this time, a supporting portion formed by the third barrier layer 2066 is provided between the P-type GaN side portion 2082 and the third insertion layer 2065, which helps to improve the stability of the gate region pattern and make the threshold voltage of the device more stable.

[0141] In summary, in the GaN-based enhanced HEMT device structure and its manufacturing method of the present invention, the barrier stack includes a first insertion layer, a first barrier layer, a second insertion layer, a second barrier layer, a third insertion layer and a third barrier layer stacked in sequence from bottom to top, wherein the second insertion layer is used as an etching stop layer during trench etching, and the thickness of the barrier layer in the trench area becomes smaller, which can reduce the 2DEG concentration under the P-type GaN part, thereby increasing the threshold voltage of the device; the third insertion layer is used as an etching stop layer during patterning of the P-type GaN layer, which can reduce the over-etching depth of the barrier layer, increase the remaining thickness of the barrier layer, and reduce the probability of electron tunneling to the surface of the barrier layer, thereby reducing the surface traps of the barrier layer and reducing the probability of electrons being captured; the presence of the third barrier layer can effectively prevent the third insertion layer from being etched through, avoid direct contact between the passivation layer and the second barrier layer, and can further reduce interface traps. In short, the present invention realizes the optimization of thick barrier layers and surface defects of barrier layers, which helps to improve the performance and reliability of devices. Therefore, the present invention effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.

[0142] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a GaN-based enhancement mode HEMT device structure, characterized in that: The following steps are involved: Providing a substrate, wherein one side of the substrate has a channel layer, wherein the channel layer includes an undoped GaN layer; forming a barrier stack on the channel layer, wherein the barrier stack comprises a first insertion layer, a first barrier layer, a second insertion layer, a second barrier layer, a third insertion layer and a third barrier layer stacked in sequence from bottom to top; Performing etching to form a trench in the barrier stack, wherein the bottom of the trench stops at the second insertion layer; forming a P-type GaN layer, wherein the P-type GaN layer covers the top surface of the barrier stack and the inner wall of the trench; Etching to pattern the P-type GaN layer to obtain a P-type GaN portion, wherein the P-type GaN portion at least covers the bottom wall of the trench, and the etched area around the P-type GaN portion stops at the third insertion layer; forming a passivation layer, the passivation layer covering the P-type GaN portion and covering the exposed surface of the third insertion layer; A gate electrode and a source electrode and a drain electrode respectively located at both sides of the gate electrode are formed. The gate electrode penetrates the passivation layer and contacts the P-type GaN portion. The source electrode and the drain electrode penetrate the passivation layer and contact the third insertion layer.

2. The method for manufacturing a GaN-based enhanced-mode HEMT device structure according to claim 1, characterized in that: The first insertion layer, the second insertion layer, and the third insertion layer each include an AlN layer, and the first barrier layer, the second barrier layer, and the third barrier layer each include an AlGaN layer.

3. The method for manufacturing a GaN-based enhanced-mode HEMT device structure according to claim 1, characterized in that: The thickness of the barrier stack is in the range of 12 to 20 nm.

4. The method for manufacturing a GaN-based enhanced-mode HEMT device structure according to any one of claims 1 to 3, characterized in that: The thickness of the first insertion layer is in the range of 0.1 to 1 nm, the thickness of the second insertion layer is in the range of 0.3 to 1.5 nm, and the thickness of the third insertion layer is in the range of 0.3 to 1.5 nm.

5. The method for manufacturing a GaN-based enhancement mode HEMT device structure according to any one of claims 1 to 3, characterized in that: The passivation layer includes an AlN layer.

6. The method for manufacturing a GaN-based enhancement mode HEMT device structure according to any one of claims 1 to 3, characterized in that: The method of forming the barrier stack includes a MOCVD method.

7. The method for manufacturing a GaN-based enhancement mode HEMT device structure according to any one of claims 1 to 3, characterized in that: The P-type GaN portion includes a P-type GaN main portion located on the inner wall of the groove and a P-type GaN side portion horizontally extending from the top of the P-type GaN main portion to both sides, and a supporting portion formed by a portion of the third barrier layer is provided between the P-type GaN side portion and the third insertion layer.

8. The method for manufacturing a GaN-based enhancement mode HEMT device structure according to any one of claims 1 to 3, characterized in that: The substrate comprises a substrate layer, a nucleation layer, a buffer layer and a C-doped GaN layer which are arranged in sequence from bottom to top.

9. The method for manufacturing a GaN-based enhancement mode HEMT device structure according to claim 8, characterized in that: The substrate layer includes a Si layer, the nucleation layer includes an AlN layer, and the buffer layer includes an AlGaN-AlN superlattice layer.

10. A GaN-based enhancement mode HEMT device structure, characterized in that: include: A substrate, one side of the substrate having a channel layer, wherein the channel layer comprises an undoped GaN layer; A barrier stack, located on the channel layer and comprising at least a first insertion layer, a first barrier layer, a second insertion layer, a second barrier layer and a third insertion layer stacked in sequence from bottom to top; a groove opening from the top surface of the barrier stack and extending downward to the second insertion layer; A P-type GaN portion at least covers the bottom wall of the trench, and a top layer of the barrier stack around the P-type GaN portion is the third insertion layer; a passivation layer covering the P-type GaN portion and covering the third insertion layer around the P-type GaN portion; A gate electrode and a source electrode and a drain electrode respectively located at both sides of the gate electrode, the gate electrode penetrates the passivation layer and contacts the P-type GaN portion, the source electrode and the drain electrode penetrate the passivation layer and contact the third insertion layer.

11. The GaN-based enhancement mode HEMT device structure according to claim 10, characterized in that: The first insertion layer, the second insertion layer, and the third insertion layer each include an AlN layer, and the first barrier layer and the second barrier layer each include an AlGaN layer.

12. The GaN-based enhancement mode HEMT device structure according to claim 10, characterized in that: The thickness of the barrier stack is in the range of 12 to 20 nm.

13. The GaN-based enhancement mode HEMT device structure according to any one of claims 10 to 12, characterized in that: The thickness of the first insertion layer is in the range of 0.1 to 1 nm, the thickness of the second insertion layer is in the range of 0.3 to 1.5 nm, and the thickness of the third insertion layer is in the range of 0.3 to 1.5 nm.

14. The GaN-based enhancement mode HEMT device structure according to any one of claims 10 to 12, characterized in that: The passivation layer includes an AlN layer.

15. The GaN-based enhancement mode HEMT device structure according to any one of claims 10 to 12, characterized in that: The P-type GaN portion includes a P-type GaN main portion located on the inner wall of the groove and a P-type GaN side portion extending horizontally from the top of the P-type GaN main portion to both sides. The barrier stack also includes a third barrier layer located on the third insertion layer. A supporting portion formed by the third barrier layer is provided between the P-type GaN side portion and the third insertion layer.

16. The GaN-based enhancement mode HEMT device structure according to any one of claims 10 to 12, characterized in that: The substrate comprises a substrate layer, a nucleation layer, a buffer layer and a C-doped GaN layer which are arranged in sequence from bottom to top.

17. The GaN-based enhancement mode HEMT device structure according to claim 16, characterized in that: The substrate layer includes a Si layer, the nucleation layer includes an AlN layer, and the buffer layer includes an AlGaN-AlN superlattice layer.

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