Clock signal control soft PUF (Physical Unclonable Function) based on coding circuit and application method thereof

Abstract

The invention discloses a clock signal control soft PUF (Physical Unclonable Function) based on a coding circuit and an application method thereof, the clock signal control soft PUF comprises the coding circuit, a clock signal generator and a register module, the coding circuit can access externally input image information data, and the image information data is simultaneously used as an input excitation signal of the clock signal control soft PUF; the clock signal generator is used for generating three groups of clock signals of which the frequencies are sequentially increased, the clock cycles of the three groups of clock signals are all smaller than the critical path of the coding circuit, and each group of clock signals is an overclocking clock signal which can enable the coding circuit to be in an abnormal working state; if the external input image information data is accessed, the internal data transmission is abnormal, and at the moment, the coding circuit generates an output signal irrelevant to the input image information data and outputs the output signal to the register module for storage; the method has the advantages of being high in safety and low in resource consumption.

Description

Technical Field

[0001] The present invention relates to a soft PUF, and in particular to a clock signal controlled soft PUF based on an encoding circuit and an application method thereof. Background Art

[0002] With the explosive development of the Internet of Things and multimedia technology, monitoring systems are widely used in people's daily lives. By the end of 2023, there will be more than 1 billion monitoring devices in use around the world. After capturing image data, the monitoring system quantifies, compresses, and encodes it into code stream information that can carry image features, which can be transmitted to various terminal devices through the Internet of Things. The transmission process of image data between IoT devices faces serious security challenges. During the transmission process of the Internet of Things, traditional image information encryption encrypts image data through obfuscated address encryption, HLS (HTTP Live Streaming) encryption technology, and anti-hotlink encryption technology. Although these encryption technologies are easy to implement, these traditional encryption schemes are not very secure. Hackers can easily decrypt image data after obtaining the key. The image data code stream is exposed to the Internet of Things and public places during the transmission process, and is easily stolen and maliciously attacked. Once the image data code stream is stolen by criminals, a large amount of privacy information will be leaked. Physical Unclonable Function (PUF) is an emerging hardware security primitive with characteristics such as lightweight and unclonability. The random PUF response it generates provides a new solution for securely encrypting image data under resource-constrained conditions.

[0003] Traditional hardware PUFs use specific circuit structures to generate unclonable, unique random output responses. These PUFs are called hardware PUFs. Common hardware PUFs include ring-oscillator PUFs (RO PUFs), arbiter PUFs (APUFs), and static random access memory (SRAM) PUFs. Lim et al. proposed a delay-based arbiter PUF, which uses the different delays of electrical signals in gate circuits and connecting wires in integrated circuits to implement PUF circuits. Suh et al. proposed a ring oscillator PUF using the delay information difference of electrical signals in integrated circuits. Its structure is easier to implement on integrated circuits and has higher stability. Since the response of APUF and RO PUF depends on the path delay deviation, and since the timing path in the chip is a linear superposition of switch and register delays, APUF and RO PUF have poor resistance to machine learning. In addition, arbiter PUF and ring oscillator PUF are usually implemented on dedicated integrated circuits, which will cause a large resource overhead. Although SRAM PUF is easy to implement, it uses the random power-on state in the SRAM cell to generate a response. Its random feature response needs to rely on the power-on cycle, and obtaining the SRAM PUF response requires continuous charging and discharging of the circuit, which will cause a lot of energy consumption. After nearly two decades of research and exploration, hardware PUF has shown unique value in the field of information security, but with the rapid development of Internet of Things technology, more and more application scenarios usually require security protection in resource-limited environments. In addition, because hardware PUF needs to add additional hardware resources or change the existing device structure when protecting information, this will increase the design cycle and manufacturing cost of the circuit. Moreover, the hardware equipment of some systems cannot be replaced, which makes it difficult for traditional hardware PUF to meet these needs.

[0004] The chip operates according to the expected logical functions under normal operation. However, when the external voltage, clock excitation, external temperature and other factors are changed, the chip operates in an abnormal state. At this time, the data transmission between the internal registers of the chip will have timing violations, causing the entire chip to operate abnormally. These abnormal responses can characterize the chip identity information under certain conditions. This phenomenon provides a theoretical basis for the research and implementation of soft PUF (Software PUF, SPUF). Soft PUF changes the external excitation to make the chip work in a specific state, thereby generating a PUF response that can characterize the chip characteristics. Soft PUF obtains the response information of the chip under abnormal operation to extract the random process deviation of the chip. It does not need to change the original circuit structure, does not need to add additional hardware resources, and does not need to replace the existing hardware equipment. It realizes the extraction of chip feature responses and establishes a mapping relationship between abnormal responses and chip features. In terms of soft PUF design, Maiti proposed a processor PUF that uses the differences in error conditions when the processor executes instructions at different frequencies to generate a PUF response. Although this PUF does not occupy additional hardware resources, it needs to accurately overclock the operation to extract processor error information multiple times at different frequencies when extracting the PUF response, which has poor randomness and poor security. Wang proposed a scan chain PUF that extracts PUF responses by inserting data selectors between registers and using the uncertainty characteristics of trigger sampling data in the case of timing violations. However, this scan chain PUF needs to add multiple data selectors to the original circuit. Although it has higher security, it consumes more resources. Summary of the invention

[0005] One of the technical problems to be solved by the present invention is to provide a clock signal controlled soft PUF based on an encoding circuit which has high security and low resource consumption.

[0006] The technical solution adopted by the present invention to solve one of the above technical problems is: a clock signal controlled soft PUF based on a coding circuit, including a coding circuit, a clock signal generator and a register module; the clock signal generator is connected to the coding circuit, the coding circuit is connected to the register module, the coding circuit can access external input image information data, and the image information data is also used as the input excitation signal of the clock signal controlled soft PUF; the clock signal generator is used to generate three groups of clock signals, the clock periods of the three groups of clock signals are all less than the critical path of the coding circuit, the three groups of clock signals are recorded as CLK1, CLK2 and CLK3, and the frequencies of CLK1, CLK2 and CLK3 increase successively; CLK1, CLK2 and CLK3 are all capable of enabling the coding The overclocked clock signal of the circuit is in an abnormal working state. When the encoding circuit is in an abnormal working state, if the external input image information data is connected, its internal data transmission will be abnormal. At this time, the encoding circuit generates an output signal that is unrelated to the input image information data and outputs it to the register module for storage. The output signal generated by the encoding circuit when the image information data is connected to the external input under the control of CLK1 is recorded as R1, the output signal generated by the encoding circuit when the image information data is connected to the external input under the control of CLK2 is recorded as R2, and the output signal generated by the encoding circuit when the image information data is connected to the external input under the control of CLK3 is recorded as R3. R1, R2 and R3 are spliced ​​to form the output response R1R2R3 of the clock signal-controlled soft PUF.

[0007] The register module includes three registers, which are respectively called register 1, register 2 and register 3. The register 1 is used to store R1, the register 2 is used to store R2, and the register 3 is used to store R3.

[0008] Compared with the prior art, the advantage of the clock signal controlled soft PUF of the present invention is that three groups of clock signals CLK1, CLK2 and CLK3 are generated by the clock signal generator, the frequencies of the three groups of clock signals are increased accordingly, the periods of the three groups of clock signals are all smaller than the critical path of the encoding circuit, the three groups of overclocked clock signals are used as the encoding circuit clocks in turn, the encoding circuit works abnormally under the action of the overclocked clock to generate abnormal information, and the abnormal information can characterize the characteristics of the encoding circuit, and the clock signal controlled soft PUF does not change the circuit structure when generating abnormal information, and does not require additional hardware overhead, because the abnormal response of the encoding circuit depends on the internal register arrangement of the encoding circuit Therefore, it is very difficult to directly extract abnormal responses from the inside of the coding circuit, and brute force cracking and modeling attacks are almost impossible to achieve on the clock signal control soft PUF. Therefore, the clock signal control soft PUF of the present invention has high security. In addition, three groups of incremental overclocked clock signals are used as the coding circuit clock to generate three groups of abnormal responses. The three groups of abnormal responses are spliced ​​to form the clock signal control soft PUF response, which can further expand the clock signal control soft PUF response range. The clock signal control soft PUF consumes less resources, has a large number of soft PUF responses and high security, providing a solution to the security problem in the resource-constrained Internet of Things system.

[0009] One of the technical problems to be solved by the present invention is to provide an application method of a clock signal controlled soft PUF based on an encoding circuit, which has high security and low resource consumption.

[0010] The technical solution adopted by the present invention to solve one of the above technical problems is: an application method of controlling a soft PUF based on a clock signal of an encoding circuit, comprising the following steps:

[0011] Step 1: Use the signal generator to generate CLK1, input CLK1 and external image information data into the encoding circuit, at which time the encoding circuit enters an abnormal working state, generates an output signal R1 and stores it in the register module; use the signal generator to generate CLK2, input CLK2 and external image information data into the encoding circuit, at which time the encoding circuit enters an abnormal working state, generates an output signal R2 and stores it in the register module; use the signal generator to generate CLK3, input CLK3 and external image information data into the encoding circuit, at which time the encoding circuit enters an abnormal working state, generates an output signal R3 and stores it in the register module;

[0012] Step 2: Use the signal generator to generate a clock signal that can put the encoding circuit in a normal working state, and record the clock signal as CLK4, wherein the clock period of CLK4 is greater than the critical path of the encoding circuit; input CLK4 and external image information data into the encoding circuit, and then the encoding circuit enters a normal working state, encodes the external input image information data, obtains a corresponding binary code stream R4, and stores the code stream R4 in the register module;

[0013] Step 3: Obtain R1, R2 and R3 from the register module, perform Gray code encoding on R1 and R2, R1 and R3, and R2 and R3 respectively, record the result obtained after Gray code encoding of R1 and R2 as R5, record the result obtained after Gray code encoding of R1 and R3 as R6, and record the result obtained after Gray code encoding of R2 and R3 as R7;

[0014] Step 4: Perform XOR operations on R5 and R6, R5 and R7, and R6 and R7 respectively. The result of the XOR operation of R5 and R6 is recorded as R8, the result of the XOR operation of R5 and R7 is recorded as R9, and the result of the XOR operation of R6 and R7 is recorded as R 10 ;

[0015] Step 5: Connect R8, R9 and R 10 Concatenate to form the encrypted response R 11 , R 11 =R8R9R 10 ;

[0016] Step 6: Get R4 from the register module and compare R4 with R 11 Perform an XOR operation and record the result as R 12 , R 12 That is the encrypted ciphertext, and the encryption of the external input image information data is completed.

[0017] The register module includes 4 registers, which are respectively called register 1, register 2, register 3 and register 4. R1 is stored in the register 1, R2 is stored in the register 2, R3 is stored in the register 3, and R4 is stored in the register 4.

[0018] Compared with the prior art, the application method of the clock signal controlled soft PUF of the present invention has the advantage that the output response of the clock signal controlled soft PUF under the three groups of overclocked clocks CLK1, CLK2 and CLK3 is confused by Gray code encoding and XOR operation, thereby improving the robustness and security of the output response of the clock signal controlled soft PUF. In addition, the output response of the obfuscated clock signal controlled soft PUF is used to encrypt the image code stream R4 by XOR operation. Therefore, the application method of the present invention uses the output response and XOR operation of the clock signal controlled soft PUF to replace the traditional encryption algorithm, which effectively reduces resource overhead while ensuring the security of the image code stream. Moreover, the clock signal controlled soft PUF has the characteristic of naturally generating random keys, eliminating the need to store any keys on the device. Compared with the traditional sensitive information encryption method, the encryption method of the image code stream based on the output response of the clock signal controlled soft PUF can effectively reduce resource overhead and reduce the risk of information leakage. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 Schematic diagram of a clock signal controlled soft PUF based on an encoding circuit of the present invention;

[0020] Figure 2 It is a schematic diagram of the working state of the soft PUF under different clock frequencies controlled by the clock signal based on the encoding circuit of the present invention;

[0021] Figure 3 A 2D grayscale image of the output response of the soft PUF controlled by the clock signal of the encoding circuit according to the present invention;

[0022] Figure 4 A statistical histogram and a fitting diagram of the average HD of the output response of the soft PUF controlled by the clock signal of the encoding circuit according to the present invention;

[0023] Figure 5 It is a schematic diagram of the autocorrelation of the output response of the soft PUF controlled by the clock signal of the encoding circuit according to the present invention;

[0024] Figure 6 The bit error rate of the soft PUF under different power supply voltages controlled by the clock signal of the encoding circuit of the present invention;

[0025] Figure 7 The bit error rate of the soft PUF at different temperatures controlled by the clock signal of the encoding circuit of the present invention;

[0026] Figure 8 The present invention is a flow chart of an application method of controlling a soft PUF based on a clock signal of an encoding circuit. DETAILED DESCRIPTION

[0027] The present invention discloses a clock signal controlled soft PUF based on a coding circuit. The clock signal controlled soft PUF based on a coding circuit of the present invention is further described in detail below in conjunction with the embodiments of the accompanying drawings.

[0028] Example: Figure 1 As shown, a clock signal controlled soft PUF based on a coding circuit includes a coding circuit, a clock signal generator and a register module; the clock signal generator is connected to the coding circuit, the coding circuit is connected to the register module, the coding circuit can access external input image information data, and the image information data is also used as an input excitation signal for the clock signal controlled soft PUF; the clock signal generator is used to generate three groups of clock signals, the clock periods of the three groups of clock signals are all smaller than the critical path of the coding circuit, the three groups of clock signals are recorded as CLK1, CLK2 and CLK3, and the frequencies of CLK1, CLK2 and CLK3 increase in sequence; CLK1, CLK2 and CLK3 are all super-fast signals that can cause the coding circuit to be in an abnormal working state Frequency clock signal, when the encoding circuit is in an abnormal working state, if the external input image information data is connected, its internal data transmission will be abnormal. At this time, the encoding circuit generates an output signal that is unrelated to the input image information data and outputs it to the register module for storage. The output signal generated by the encoding circuit when the image information data is connected to the external input under the control of CLK1 is recorded as R1, the output signal generated by the encoding circuit when the image information data is connected to the external input under the control of CLK2 is recorded as R2, and the output signal generated by the encoding circuit when the image information data is connected to the external input under the control of CLK3 is recorded as R3. R1, R2 and R3 are spliced ​​to form the clock signal to control the output response R1R2R3 of the soft PUF.

[0029] In this embodiment, the register group module includes three registers, which are respectively called register 1, register 2 and register 3. Register 1 is used to store R1, register 2 is used to store R2, and register 3 is used to store R3.

[0030] In this embodiment, when the clock signal controls the soft PUF to work, the clock frequency is increased to make the encoding circuit in an abnormal working state to generate abnormal information that can characterize the encoding circuit. Figure 2 As shown, the coding circuit is in two working states under different clock signals: normal working state and abnormal working state. In the normal working state, the coding circuit can complete the encoding of the input image information data, and no timing violation will occur between the internal registers of the coding circuit. The normal working of the coding circuit cannot generate abnormal information. Therefore, the clock signal of the present invention controls the soft PUF to work in Figure 2In the abnormal working state, the clock signal controls the soft PUF to operate in an abnormal state, the clock frequency increases, the power consumption of the encoding circuit increases, and timing violations occur in some paths inside the encoding circuit. The clock signal controls the soft PUF to produce information results with the characteristics of the encoding circuit under the action of the overclocked clock.

[0031] In order to verify the performance of the clock signal controlled soft PUF based on the coding circuit of the present invention, the clock signal controlled soft PUF based on the coding circuit of the present invention is simulated.

[0032] The randomness of the PUF response can be used to characterize the distribution of the PUF output response logic 0 and logic 1. Formula (1) can be used to calculate the PUF information entropy:

[0033] Randomness=(1-|2P(r=1)-1|)×100% (1)

[0034] In formula (1), p(r=1) represents the probability of logic 1 in the PUF response. Ideally, the probability of PUF output response logic 0 and 1 is 0.5, and the randomness is 100%. In order to study the random distribution of the output response of the soft PUF controlled by the clock signal under the overclocked clock, 20 Monte Carlo simulations were performed under three groups of overclocked clocks to simulate the random process deviation of 20 soft PUFs controlled by the clock signal. Figure 3 The figure shows a grayscale image of the 9000-bit random output result of the clock signal controlled soft PUF. White pixels represent the PUF response output logic 0, and black pixels represent the PUF response output logic 1. The 9000-bit responses generated by 20 Monte Carlo simulations are statistically analyzed. The probabilities of logic 0 and logic 1 are 48.1% and 51.9%, respectively. It can be found that the clock signal controlled soft PUF of the present invention has good randomness.

[0035] Uniqueness refers to the difference in output responses to the same stimulus between different PUF individuals with the same PUF structure, that is, the ability of the PUF circuit to generate unique identity information, which is calculated by the inter-chip Hamming distance (Hamming Distance, HD). Under ideal conditions, when the same challenge is applied between different PUF individuals, the uniqueness should be 50%. Formula (2) can be used to calculate the inter-chip Hamming distance:

[0036]

[0037] Uniqueness represents the average inter-chip HD of k different PUF individuals. In formula 2, k represents the PUF individual r. i and r j represents the PUF response generated by the i-th and j-th PUF individuals, HD(r i ,r j) is the Hamming distance between the i-th and j-th PUF individuals, and the E(HD) of the clock signal controlled soft PUF of the present invention calculated by formula (2) is inter ) is 48.87%, which is close to the ideal value of 50%, indicating that the present invention has good uniqueness. Figure 4 As shown, 20 Monte Carlo simulations are completed for the clock signal control soft PUF, and the HD distribution of the output responses of the 20 Monte Carlo simulations is statistically analyzed, which obeys the normal distribution with a mathematical expectation of μ = 0.4887 and a standard deviation of σ = 0.0616.

[0038] Autocorrelation describes the correlation between the random sequence of PUF circuit responses, that is, the correlation between the current response sequence and the past response sequence, and is used to evaluate whether the PUF can generate random independent responses. The ACF test results can reflect the ability of the PUF circuit to resist autocorrelation attacks. The autocorrelation test is performed on the 60,000-bit response generated by 20 Monte Carlo simulations of the clock signal controlled soft PUF. Figure 5 As shown, within the 95% confidence interval, the autocorrelation test value is 0.0204, which is close to the ideal value of 0.

[0039] Security requires that the designed PUF circuit is difficult for an attacker to predict a new stimulus PUF response through a known stimulus response pair. The security of the PUF is usually tested using the NIST test suite. The NIST statistical test suite can be used to evaluate the randomness of the PUF response and pseudo-random numbers. A 60,000-bit random response is generated from the clock signal controlled soft PUF as the NIST input. These inputs are divided into 50 groups of separate bit streams and subjected to different NIST tests. Table 1 shows the NIST test results of the clock signal controlled soft PUF output response. The average P value of the test results is greater than 0.01, indicating that the clock signal controlled soft PUF of the present invention has high security.

[0040] Table 1 NIST test

[0041]

[0042] The robustness of the clock signal controlled soft PUF is affected by system noise, power supply voltage and ambient temperature changes. In order to evaluate the robustness of the clock signal controlled soft PUF of the present invention, the robustness of the PUF is evaluated by testing the bit error rate of the clock signal controlled soft PUF in different environments. Figure 6 As shown in the figure, when the three clocks CLK1, CLK2 and CLK3 are tested respectively, the bit error rate of the clock signal controlling the soft PUF when the supply voltage changes from 1.0V to 1.4V, the worst soft bit error rate of the encoding circuit under voltage change is 26.53%. Figure 7As shown in the figure, when the three clock groups CLK1, CLK2 and CLK3 are tested respectively, the bit error rate of the clock signal controlled soft PUF is 33.34% when the external temperature changes from -20°C to 120°C. It can be proved that the clock signal controlled soft PUF of the present invention has good robustness.

[0043] The present invention also discloses an application method of the above-mentioned coding circuit-based clock signal control soft PUF. The application method of the coding circuit-based clock signal control soft PUF of the present invention is further described in detail below in conjunction with the accompanying drawings.

[0044] Example: Figure 8 As shown, an application method of controlling a soft PUF based on a clock signal of an encoding circuit comprises the following steps:

[0045] Step 1: Use a signal generator to generate CLK1, input CLK1 and external image information data into the encoding circuit, at this time the encoding circuit enters an abnormal working state, generates an output signal R1 and stores it in the register module; use a signal generator to generate CLK2, input CLK2 and external image information data into the encoding circuit, at this time the encoding circuit enters an abnormal working state, generates an output signal R2 and stores it in the register module; use a signal generator to generate CLK3, input CLK3 and external image information data into the encoding circuit, at this time the encoding circuit enters an abnormal working state, generates an output signal R3 and stores it in the register module;

[0046] Step 2: Use a signal generator to generate a clock signal that can put the encoding circuit in a normal working state, and record the clock signal as CLK4, where the clock period of CLK4 is greater than the critical path of the encoding circuit; input CLK4 and external image information data into the encoding circuit, and the encoding circuit enters a normal working state at this time, encodes the external input image information data, generates a corresponding binary code stream R4, and stores the code stream R4 in the register module;

[0047] Step 3: Get R1, R2 and R3 from the register module, perform Gray code encoding on R1 and R2, R1 and R3, and R2 and R3 respectively, record the result obtained after Gray code encoding of R1 and R2 as R5, record the result obtained after Gray code encoding of R1 and R3 as R6, and record the result obtained after Gray code encoding of R2 and R3 as R7;

[0048] Step 4: Perform XOR operations on R5 and R6, R5 and R7, and R6 and R7 respectively. The result of the XOR operation of R5 and R6 is recorded as R8, the result of the XOR operation of R5 and R7 is recorded as R9, and the result of the XOR operation of R6 and R7 is recorded as R 10 ;

[0049] Step 5: Connect R8, R9 and R 10 Concatenate to form the encrypted response R 11 , R 11 =R8R9R 10 ;

[0050] Step 6: Get R4 from the register module and compare R4 with R 11 Perform an XOR operation and record the result as R 12 , R 12 That is the encrypted ciphertext, and the encryption of the external input image information data is completed.

[0051] In this embodiment, the register module includes 4 registers, which are respectively called register 1, register 2, register 3 and register 4. R1 is stored in register 1, R2 is stored in register 2, R3 is stored in register 3, and R4 is stored in register 4.

[0052] The application method of the clock signal controlled soft PUF of the present invention improves the robustness and security of the output response of the clock signal controlled soft PUF by confusing the output response of the clock signal controlled soft PUF under three groups of overclocked clocks CLK1, CLK2 and CLK3 using Gray code encoding and XOR operation. In addition, the output response of the obfuscated clock signal controlled soft PUF is encrypted using the XOR operation code stream R4. Therefore, the application method of the present invention uses the output response and XOR operation of the clock signal controlled soft PUF to replace the traditional encryption algorithm, which effectively reduces resource overhead while ensuring the security of the image code stream. Moreover, the clock signal controlled soft PUF has the characteristic of naturally generating random keys, eliminating the need to store any keys on the device. Compared with the traditional sensitive information encryption method, it can effectively reduce resource overhead and reduce the risk of information leakage.

Claims

1. A clock signal controlled soft PUF based on an encoding circuit, characterized in that It includes a coding circuit, a clock signal generator and a register module; the clock signal generator is connected to the coding circuit, the coding circuit is connected to the register module, the coding circuit can access external input image information data, and the image information data is also used as the input excitation signal of the clock signal to control the soft PUF; the clock signal generator is used to generate three groups of clock signals, the clock periods of the three groups of clock signals are all smaller than the critical path of the coding circuit, the three groups of clock signals are recorded as CLK1, CLK2 and CLK3, the frequencies of CLK1, CLK2 and CLK3 increase in sequence; CLK1, CLK2 and CLK3 are all overclocked clock signals that can make the coding circuit in an abnormal working state, when the When the encoding circuit is in an abnormal working state, if the external input image information data is connected, its internal data transmission will be abnormal. At this time, the encoding circuit generates an output signal that is unrelated to the input image information data and outputs it to the register module for storage. The output signal generated by the encoding circuit when the image information data is connected to the external input under the control of CLK1 is recorded as R1, the output signal generated by the encoding circuit when the image information data is connected to the external input under the control of CLK2 is recorded as R2, and the output signal generated by the encoding circuit when the image information data is connected to the external input under the control of CLK3 is recorded as R3. R1, R2 and R3 are spliced ​​to form the output response R1R2R3 of the clock signal controlled soft PUF.

2. According to claim 1, a clock signal controlled soft PUF based on an encoding circuit is characterized in that The register module includes three registers, which are respectively called register 1, register 2 and register 3. The register 1 is used to store R1, the register 2 is used to store R2, and the register 3 is used to store R3.

3. An application method of the clock signal control soft PUF based on the coding circuit according to claim 1, characterized in that The following steps are involved: Step 1: Use the signal generator to generate CLK1, input CLK1 and external image information data into the encoding circuit, at which time the encoding circuit enters an abnormal working state, generates an output signal R1 and stores it in the register module; use the signal generator to generate CLK2, input CLK2 and external image information data into the encoding circuit, at which time the encoding circuit enters an abnormal working state, generates an output signal R2 and stores it in the register module; use the signal generator to generate CLK3, input CLK3 and external image information data into the encoding circuit, at which time the encoding circuit enters an abnormal working state, generates an output signal R3 and stores it in the register module; Step 2: Use the signal generator to generate a clock signal that can put the encoding circuit in a normal working state, and record the clock signal as CLK4, wherein the clock period of CLK4 is greater than the critical path of the encoding circuit; input CLK4 and external image information data into the encoding circuit, and then the encoding circuit enters a normal working state, encodes the external input image information data, obtains a corresponding binary code stream R4, and stores the code stream R4 in the register module; Step 3: Obtain R1, R2 and R3 from the register module, perform Gray code encoding on R1 and R2, R1 and R3, and R2 and R3 respectively, record the result obtained after Gray code encoding of R1 and R2 as R5, record the result obtained after Gray code encoding of R1 and R3 as R6, and record the result obtained after Gray code encoding of R2 and R3 as R7; Step 4: Perform XOR operations on R5 and R6, R5 and R7, and R6 and R7 respectively. The result of the XOR operation of R5 and R6 is recorded as R8, the result of the XOR operation of R5 and R7 is recorded as R9, and the result of the XOR operation of R6 and R7 is recorded as R 10 ; Step 5: Connect R8, R9 and R 10 Concatenate to form the encrypted response R 11 , R 11 =R8R9R 10 ; Step 6: Get R4 from the register module and compare R4 with R 11 Perform an XOR operation and record the result as R 12 , R 12 That is the encrypted ciphertext, and the encryption of the external input image information data is completed.

4. The application method of clock signal control soft PUF based on coding circuit according to claim 3 is characterized in that The register module includes 4 registers, which are respectively called register 1, register 2, register 3 and register 4. R1 is stored in the register 1, R2 is stored in the register 2, R3 is stored in the register 3, and R4 is stored in the register 4.

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