Semiconductor device structure, preparation method thereof and chip

Abstract

The invention discloses a semiconductor device structure, a preparation method thereof and a chip, and belongs to the technical field of semiconductor devices. The semiconductor device structure comprises a gold-silver alloy bump and a UBM layer, and the UBM layer is composed of a seed layer, a diffusion barrier layer and an adhesion layer or composed of the diffusion barrier layer and the adhesion layer. The diffusion barrier layer is composed of a platinum group element simple substance and / or an alloy containing a platinum group element, preferably composed of platinum, rhodium, iridium or an alloy thereof; the bottom of the gold-silver alloy bump is connected with the seed layer or the diffusion barrier layer, and the adhesion layer is connected with a chip electrode. By improving the UBM layer, the combination reliability of the gold-silver alloy bump and the UBM layer is improved, the obtained semiconductor device structure can pass a high-end chip reliability test, and a flip chip is prepared by replacing gold with gold-silver alloy.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor devices and relates to a semiconductor device structure and a preparation method and a chip thereof. Background Art

[0002] Flip chip technology is mainly divided into two categories. One is reflow solder, including tin, tin-lead alloy, tin-silver alloy, gold-tin alloy, etc. Although the current lead-free soldering material technology is very mature, the solder is liquid under high temperature and may cause bridging between adjacent solder bumps under pressure, which is not suitable for fine-pitch flip chip applications. The other is bonding through pure gold bumps, in which the gold bumps are electrically connected to the substrate through hot press soldering or anisotropic conductive adhesive. Although the reliability of gold bumps is very good and there is no bridging problem between adjacent gold bumps, the material cost of gold is very high. With the increasing price of gold, the development of new materials to replace gold is currently a hot topic of research. Considering the excellent properties of gold bumps, such as anti-oxidation, anti-sulfurization, hardness, roughness, and solderability, there are not many solutions that can replace gold. Among them, gold-silver alloy replacing gold bumps is one of the most promising solutions.

[0003] TWI469288B discloses electroplated gold-silver bumps, which involves the problem of preventing silver from oxidizing. The top surface or side surface of the gold-silver bump is electroplated or chemically plated with one of gold, palladium, copper or nickel to prevent silver from oxidizing, wherein copper or nickel is more easily oxidized than silver. TW201044527A discloses electroplated gold-silver bumps containing no less than 80% silver content, and then a protective layer is formed on the gold-silver surface by replacing gold or reducing gold to prevent silver from oxidizing. TW201019440A discloses that the material of the silver bump can be selected from pure silver or silver alloy, and the silver alloy system of these silver bumps can contain no less than 80% silver content, and then a layer of pure gold or gold alloy is plated on the surface of the silver alloy to solve the problem of anti-oxidation.

[0004] CN117542818B can significantly improve the anti-oxidation or anti-sulfurization performance of silver in gold-silver bumps by increasing the gold content in gold-silver bumps to more than 60%. The anti-oxidation and anti-sulfurization problems of gold-silver bumps are solved by first preparing a gold-silver alloy body with a gold content of 20% to 50% as a connecting layer at a low current density in the same electroplating tank, and then preparing a very thin protective layer with a gold content of more than 60% on the surface of the bump at a high current density. In order to solve the poor welding that may be caused by silver oxidation, CN118398588B selectively removes metallic silver on the surface of the bump by electrochemical etching to form a nano-mesoporous gold structure, which will not affect the hardness of the bump itself and solve the anti-oxidation and anti-sulfurization problems of the gold-silver bumps.

[0005] Although the above solutions propose solutions to the problems of hardness, oxidation resistance or poor welding caused by sulfurization of gold and silver bumps, they do not mention the bonding strength between the gold and silver bumps and different metal layers during the manufacturing process. After the bump is prepared, it needs to undergo various reliability tests, such as TCT (Temperature Cycle Test): -65℃(15min) ~150℃(15min), more than 700 cycles, PCT (Pressure Cooker Test): 121℃, 100% RH, 2atm, 168 hrs, THT (Temperature Humidity Test): 85℃ / 85% RH, 1000 hrs, HTST (High Temperature Storage Life Test): 150℃,1000 hrs, LTST (Low Temperature Storage Life Test): -65℃,1000 hrs, etc. to test the bonding strength between the bump and the under bump metal layer UBM (Under Bump Metal). Specifically, the bump that has undergone the reliability test can be subjected to a thrust shear test to check whether the UBM layer underneath is exposed.

[0006] Most reliability failures occur due to poor bonding between the bump and the UBM layer, so the choice of UBM material metal is very important for the bonding force. CN105895604B mentions the preparation of the bump, wherein the material of the electroplated conductive bump is selected from gold, copper, nickel, silver or their alloys, and the UBM material is selected from titanium / copper, titanium tungsten / gold or silver-containing alloys. CN116564916A mentions that the UBM layers used for the gold bump are titanium layer, titanium tungsten layer and gold layer from near to far from the electrode pad. By changing the UBM layer structure, adding a titanium layer, and reducing the thickness of the titanium tungsten layer, the bonding force of the bump is increased. US20230369270A1 In order to solve the reliability problem of bump-bonded IC devices at high temperatures, the bump material is selected from gold, copper or non-conductive materials, and the UBM layer is formed by a titanium / gold stack. US20190214357A1 mentioned that the technical problem encountered in the process of creating bumps on the chip to connect to the substrate in flip chip technology is that the manufacturing yield of the bump structure is low. The yield is improved by developing additional etching processes. The bump material used is gold and the UBM material is titanium tungsten alloy. US10629444B2 describes a new bump structure, which is considered to be a substitute for gold bumps in display driver IC packaging. The bump material used is a three-layer copper-nickel-gold layer. The UBM layer includes a Ti layer and a Cu layer on the Ti layer, or includes a TiW layer and a Cu layer on the TiW layer. TW200633093A provides a method for manufacturing a metal bump, which is composed of gold (Au), and the metal layer is composed of a titanium tungsten alloy (TiW) metal layer and a gold (Au) metal layer. US6664128B2 provides a bump manufacturing process, wherein the material forming the conductive layer is selected from aluminum, titanium, titanium-tungsten alloy, chromium, gold, silver and copper, wherein the UBM layer includes a layer selected from the following groups: aluminum / nickel-vanadium / copper layer, titanium / nickel-vanadium / copper layer, titanium-tungsten / nickel-vanadium / copper layer and chromium / nickel-vanadium / copper layer.

[0007] In order to solve the problem that the gold-silver alloy bump and the existing UBM layer cannot pass the high-temperature cycle reliability test, CN119340299A proposes that the difference in thermal expansion coefficient between the gold-silver alloy bump and the adhesive layer is below 9ppm / K, which can solve the bonding problem of semiconductor devices during the high-temperature cycle (350 cycles) reliability test. However, for some high-end DDIC (Display Driver IC) chips, the high-temperature cycle test is more stringent, with the number of cycles reaching 700 or even more than 1,000 cycles, and it is still difficult to completely eliminate the possibility of interface bonding failure.

[0008] There is an urgent need to improve the bonding reliability between the gold-silver alloy bump and the UBM layer to ensure that semiconductor devices based on the gold-silver alloy bump pass high-end chip reliability tests, thus laying the foundation for realizing the use of gold-silver alloy to replace gold in the preparation of flip chips. Summary of the invention

[0009] The purpose of the present invention is to provide a semiconductor device structure and a preparation method and chip thereof. By improving the UBM layer, the bonding reliability of the gold-silver alloy bump and the UBM layer is improved, and the obtained semiconductor device structure can pass the reliability test of high-end chips, and the gold-silver alloy can replace pure gold to prepare flip chips. After careful research, the inventor found that the failure mechanism of the gold-silver alloy is: during the reliability test, the silver atoms in the gold-silver alloy migrate to the adhesion layer (titanium or titanium-tungsten alloy) through the gold seed layer under high temperature environment, and the bonding force between silver and titanium or titanium-tungsten alloy is poor, and even if no thrust is applied, separation will occur between the interfaces.

[0010] According to diffusion theory, diffusion between metals is explained by vacancies or interstitial mechanisms. At the same time, diffusion is affected by crystal structure. If the crystal structures of two metals are the same, the lattice constants are close, the interface energy is relatively low, and the interface bonding force is high, diffusion is easy to occur. Otherwise, if the lattice structures are very different, the lattice constants are very different, the interface energy is relatively high, the interface bonding force is weak, and diffusion will be more difficult. As shown in Table 1, gold and silver are both face-centered cubic structures. The atomic radius of silver is 1.44 Å and the lattice constant is 4.086Å. The atomic radius of gold is 1.44 Å and the lattice constant is 4.078 Å. Therefore, the chance of diffusion is greater, which also explains why gold-silver alloys are prone to interface failure at high temperatures. In order to prevent the silver in the bump from diffusing to the adhesion layer through the gold seed layer and causing a decrease in bonding force, it is necessary to find a diffusion layer material to prevent the diffusion of silver to the adhesion layer. At the same time, this diffusion layer material also has the properties of precious metals to avoid the decrease in interface bonding force caused by oxidation during the material preparation process.

[0011] Table 1 Crystal structure, lattice constant and atomic radius of different precious metals

[0012] The inventors found that platinum group metals are a good choice. As shown in Table 1, the lattice constants of platinum group elements are close to those of gold and silver, the interface binding energy is low, and the binding force is strong. When diffusion occurs, since the atomic radius of silver atoms is larger than that of platinum group elements, these metals diffuse toward silver, thereby blocking the diffusion of silver atoms into the adhesion layer.

[0013] Based on this important discovery, the present invention proposes corresponding solutions, which are as follows: The primary aspect of the present invention is to provide a semiconductor device structure, including a gold-silver alloy bump and a UBM layer, wherein the UBM layer is composed of a seed layer, a diffusion barrier layer and an adhesion layer, or is composed of a diffusion barrier layer and an adhesion layer; the diffusion barrier layer is composed of a single substance of a platinum group element and / or an alloy containing a platinum group element; the device structure is sequentially as follows from top to bottom: the bottom of the gold-silver alloy bump is connected to the seed layer, the seed layer is connected to the diffusion barrier layer, the diffusion barrier layer is connected to the adhesion layer, and the adhesion layer is connected to the chip electrode; or the bottom of the gold-silver alloy bump is connected to the diffusion barrier layer, the diffusion barrier layer is connected to the seed layer, the seed layer is connected to the adhesion layer, and the adhesion layer is connected to the chip electrode; or the bottom of the gold-silver alloy bump is connected to the diffusion barrier layer, the diffusion barrier layer is connected to the adhesion layer, and the adhesion layer is connected to the chip electrode. By adding a diffusion barrier layer between the gold-silver bump and the adhesion layer, silver atoms are prevented from migrating to the adhesion layer interface, thereby solving the problem of interface failure caused by the diffusion of silver from the bump to the adhesion layer. The advantage of doing this is that UBM materials can be prepared simultaneously by magnetron sputtering or evaporation plating, and the bonding force between interfaces is better; compared with the use of electroplating and other methods to prepare the barrier layer, it reduces equipment investment and avoids cross-contamination between different plating solutions; the thickness of the metal diffusion layer film prepared by magnetron sputtering or evaporation plating is more uniform and controllable, thereby shortening the subsequent etching time and increasing the production rate and chip yield.

[0014] Preferably, the diffusion barrier layer is composed of one or more of platinum, rhodium, iridium and alloys thereof.

[0015] Furthermore, the thickness of the seed layer is 0-500 nm (the thickness of 0 means that the seed layer is removed), the thickness of the adhesion layer is 10-1000 nm, and the thickness of the diffusion barrier layer is 10-1000 nm.

[0016] Furthermore, the seed layer is gold or a gold alloy.

[0017] Furthermore, the adhesion layer is titanium or a titanium alloy, preferably titanium-tungsten or titanium-nitrogen alloy.

[0018] Furthermore, the thickness of the gold-silver alloy bump is 5-20 μm.

[0019] Furthermore, the gold content in the gold-silver alloy bump is 10-60wt%. If the gold content is too low, the hardness, roughness, anti-oxidation and sulfidation properties of the gold-silver alloy bump are too different from those of the gold bump; if the gold content is too high, firstly, the hardness is too high and defects such as gold nodules are easily generated, and secondly, it is difficult to reduce costs.

[0020] Another aspect of the present invention is to provide a method for preparing the semiconductor device structure, comprising the following steps: S1: preparing an adhesion layer, a diffusion barrier layer and a seed layer in sequence on a chip wafer by physical vapor deposition (such as evaporation or magnetron sputtering) to obtain a UBM layer; or preparing an adhesion layer, a seed layer and a diffusion barrier layer in sequence on a chip wafer by physical vapor deposition (such as evaporation or magnetron sputtering) to obtain a UBM layer; or preparing an adhesion layer and a diffusion barrier layer in sequence on a chip wafer by physical vapor deposition (such as evaporation or magnetron sputtering) to obtain a UBM layer; S2 applies photoresist and exposes the area to be plated; S3 prepares a gold-silver alloy bump by electroplating using a gold-silver electroplating solution; S4 removes excess photoresist and UBM layer.

[0021] The key to the preparation method provided by the present invention is to add a diffusion barrier layer on the adhesion layer, and the diffusion barrier layer can be located on the gold seed layer or below the gold seed layer. The specific operations include physical vapor deposition to prepare the adhesion layer, the diffusion barrier layer and the seed layer, coating the photoresist, and electroplating to prepare the gold-silver alloy bump, etc., all of which can adopt the technical solutions disclosed in the prior art.

[0022] Another aspect of the present invention is to provide a chip, wherein the chip includes the semiconductor device structure provided by the present invention.

[0023] Furthermore, the chip is a liquid crystal driver chip, a memory chip, a logic chip or a radio frequency power chip.

[0024] The technical solution provided by the present invention solves the technical problem that the gold-silver alloy bump and the existing UBM layer cannot pass the high and low temperature cycle reliability test. The obtained semiconductor device structure and the corresponding chip can pass various reliability tests, making it feasible to replace the pure gold bump with the gold-silver alloy, thereby greatly reducing the production cost of the flip chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 This is a FIB-SEM (focused ion beam scanning electron microscope) photo of the interface of a semiconductor device constructed with gold-silver alloy bumps with different gold contents after annealing at 280°C for 8 hours.

[0026] Figure 2 This is a semiconductor device constructed with gold-silver alloy bumps with a gold content of 45%, and the interface FIB-SEM photos after annealing at 280°C for different times.

[0027] Figure 3 It is a schematic diagram of the semiconductor device structure provided by the present invention.

[0028] Figure 4It is a FIB-SEM interface image of the semiconductor device structure of Example 1 and Comparative Example 1 annealed at 280° C. for 12 hours.

[0029] Reference numerals: 101 - wafer substrate, 102 - electrode, 103 - passivation layer, 104 - adhesion layer, 105 - diffusion barrier layer or seed layer, 106 - seed layer or diffusion barrier layer, 107 - gold-silver alloy bump. DETAILED DESCRIPTION

[0030] The technical solution of the present invention is described clearly and completely below in conjunction with the accompanying drawings of the specification. Obviously, the described implementation is only a part of the implementation of the present invention, not all of the implementations. Based on the implementation of the present invention, all other implementations obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0031] In the previous work, the inventor found that the semiconductor devices constructed with existing gold-silver alloy bumps are difficult to pass the reliability test of high-end chips represented by DDIC. In order to reveal the failure mechanism of the semiconductor devices constructed with existing gold-silver alloy bumps, the following research was carried out.

[0032] DDIC reliability tests take a long time, such as TCT (-65℃(15min) ~ 150℃(15min), 700 cycles or even more than 1000 cycles), HTST (150℃, 1000 hrs), etc. In order to accelerate the development of materials, the inventors have developed a new method based on the time-temperature equivalent effect to simulate device failure by shortening the time under high temperature conditions.

[0033] Gold-silver alloy bumps with different gold contents were used to construct semiconductor devices. The semiconductor devices included gold-silver alloy bumps and UBM layers. The gold contents in the gold-silver alloys were 20%, 45%, and 100% (pure gold), respectively. The UBM layer included an adhesion layer and a seed layer. The adhesion layer was a TiW alloy with a thickness of 320nm. The seed layer was pure gold with a thickness of 80nm. The three semiconductor devices were annealed at 280℃ for 8 hours, and the interface morphology of the gold-silver alloy bumps and the UBM layer was observed by FIB-SEM. The results are shown in the figure. Figure 1 As shown. Figure 1 It can be seen that the interface between the gold-silver alloy bump with a gold content of 20% and the UBM layer has separated, while the interface between the gold content of 45% and pure gold has not separated.

[0034] A semiconductor device was constructed using a gold-silver alloy bump with a gold content of 45%. The semiconductor device includes a gold-silver alloy bump and a UBM layer. The UBM layer includes an adhesion layer and a seed layer. The adhesion layer is a TiW alloy with a thickness of 320nm; the seed layer is pure gold with a thickness of 80nm. The failure mechanism was studied by annealing at 280℃ for 4h, 8h and 12h respectively, and the changes in the interface structure during the annealing process were studied. The results are as follows Figure 2 As shown. Figure 2 After annealing for 4 hours, the interface did not separate, but there was a discontinuous layer at the interface (as indicated by the white arrow). The layer gradually disappeared with the extension of annealing time. After annealing at 280℃ for 12 hours, the edge interface separated. Since the layer is located above the adhesion layer and is a very thin layer, it can be concluded that it is a gold seed layer. With the extension of annealing time, silver gradually diffuses into gold and finally forms a uniform gold-silver alloy. Due to the weak bonding between silver and TiW, the interface fails after annealing for 12 hours.

[0035] In order to verify the diffusion of silver atoms in gold, the inventors designed an experiment to verify this. First, 8 μm of 20% gold content gold-silver alloy was electroplated on the wafer, and then 1 μm of pure gold plating was electroplated. EDX was used to detect the gold and silver content in the original pure gold plating after silver diffused into the pure gold plating under different annealing conditions from the top of the plating. The detection voltage was 20KV, so the detection depth was about 400-500 nm. The results are shown in Table 2.

[0036] Table 2 Gold and silver contents in the original pure gold coating after silver diffusion under different annealing conditions

[0037] As can be seen from Table 2, when there is no annealing, no silver atoms can be detected in the gold-plated layer. As the annealing time is extended from 8h to 24h, the detectable silver atoms in the gold-plated layer increase from 8.55% to 15.4%. This experiment proves that silver diffuses very quickly in gold at 280°C. Based on the above experiments, the gold atoms and the TiW interface in the adhesion layer have strong bonding force, and the interface will not separate after annealing at 280°C, but the silver atoms and the TiW layer in the adhesion layer have weak bonding force. As more silver atoms diffuse to the adhesion layer interface through the gold seed layer, the interface failure of the device is eventually caused.

[0038] Next, a semiconductor device with a diffusion barrier layer added to the UBM layer is prepared and reliability testing is carried out. Example 1

[0039] A semiconductor device structure, such as Figure 3As shown, the bottom layer is a silicon-based wafer substrate 101, on which transistors have been deployed; the external connection lines of the transistors are aluminum electrodes or copper electrodes 102; both sides of the electrodes are passivation layers 103, and the passivation layer materials can be selected from silicon dioxide or silicon nitride and other materials. The main function is to protect and isolate the circuit, and it is prepared by evaporation or magnetron sputtering; the UBM layer is above the electrode, and from bottom to top are the adhesion layer 104, the diffusion barrier layer 105, and the seed layer 106. The material of the adhesion layer 104 is titanium, with a thickness of 250nm; the material of the diffusion barrier layer 105 is platinum, with a thickness of 50nm; the material of the seed layer 106 is gold, with a thickness of 50nm; the gold content in the gold-silver alloy bump 107 is 20wt%, and the thickness is 9μm.

[0040] The specific preparation process is as follows. On the completed 12-inch liquid crystal driver chip wafer, first use magnetron sputtering to sputter the Ti adhesion layer. The sputtering conditions are: vacuum degree 2.3mTorr, bias voltage 90V, power 5kW, and sputtering time 200s; then switch the Pt target in the same cavity to sputter the Pt diffusion barrier layer. The sputtering conditions are: vacuum degree 2.1mTorr, bias voltage 60V, power 2kW, and sputtering time 120s; finally, switch the Au target in the same cavity to sputter the Au seed layer. The sputtering conditions are: vacuum degree 2.7mTorr, bias voltage 60V, power 2kW, and sputtering time 150s. Nitrogen is introduced to cool down and take out the wafer. Spin-coat the photoresist JSR 121 on the wafer and expose the area to be electroplated. The photoresist height is 20μm. After plasma cleaning, a gold-silver alloy electroplating solution was used to prepare a gold-silver conductive metal layer. The plating temperature was 30°C, the pH was 9.0, the current density was 0.5ASD, the electroplating time was 36 minutes, the bump height after electroplating was about 9μm, and the gold content of the bump was 20%. Finally, the photoresist and UBM layers were removed. Reliability test: annealing at 280°C for 12 hours, and the interface morphology was observed using FIB-SEM. Example 2

[0041] A semiconductor device structure, the overall structure is the same as that of Example 1, except that: the structure of the UBM is a TiW adhesion layer of 320 nm, an Au seed layer of 80 nm, and a Pt diffusion barrier layer of 100 nm from bottom to top; the gold content in the gold-silver alloy bump is 60wt% and the thickness is 5μm. The overall preparation process is similar to that of Example 1, and the magnetron sputtering target and sputtering parameters change accordingly according to the change of the UBM structure. Example 3

[0042] A semiconductor device structure, the overall structure is the same as that of Example 1, except that: the structure of the UBM is respectively a TiW adhesion layer of 320 nm, an Au seed layer of 80 nm, and a platinum-rhodium alloy diffusion barrier layer of 100 nm from bottom to top; the gold content in the gold-silver alloy bump is 10wt%, and the thickness is 20μm. The overall preparation process is similar to that of Example 1, and the magnetron sputtering target and sputtering parameters change accordingly according to the change of the UBM structure. Example 4

[0043] A semiconductor device structure, the overall structure is the same as that of Example 1, except that: the structure of the UBM from bottom to top is respectively a TiW adhesion layer of 320 nm, a platinum-iridium alloy diffusion barrier layer of 100 nm, and an Au seed layer of 50 nm. The overall preparation process is similar to that of Example 1, and the magnetron sputtering target and sputtering parameters are changed accordingly according to the change of the UBM structure. Example 5

[0044] A semiconductor device structure, the overall structure is the same as that of Example 1, except that: the structure of the UBM is, from bottom to top, a Ti adhesion layer of 100 nm, an Ir diffusion barrier layer of 100 nm, and an Au seed layer of 50 nm. The overall preparation process is similar to that of Example 1, and the magnetron sputtering target and sputtering parameters are changed accordingly according to the change of the UBM structure. Example 6

[0045] A semiconductor device structure, the overall structure is the same as that of Example 1, except that: the structure of the UBM is respectively a Ti adhesion layer of 1000 nm, an Au seed layer of 500 nm, and an Ir diffusion barrier layer of 50 nm from bottom to top. The overall preparation process is similar to that of Example 1, and the magnetron sputtering target and sputtering parameters are changed accordingly according to the change of the UBM structure. Example 7

[0046] A semiconductor device structure, the overall structure is the same as that of Example 1, except that: the structure of the UBM is respectively a Ti adhesion layer of 100 nm, an Au seed layer of 80 nm, and a Rh diffusion barrier layer of 100 nm from bottom to top. The overall preparation process is similar to that of Example 1, and the magnetron sputtering target and sputtering parameters are changed accordingly according to the change of the UBM structure. Example 8

[0047] A semiconductor device structure, the overall structure is the same as that of Example 1, except that: the structure of the UBM from bottom to top is respectively a Ti adhesion layer of 100 nm, a Rh diffusion barrier layer of 50 nm, and an Au seed layer of 500 nm. The overall preparation process is similar to that of Example 1, and the magnetron sputtering target and sputtering parameters are changed accordingly according to the change of the UBM structure. Example 9

[0048] A semiconductor device structure, the overall structure is the same as that of Example 1, except that: the structure of the UBM is respectively a Ti adhesion layer of 100 nm and a Rh diffusion barrier layer of 100 nm from bottom to top. The overall preparation process is similar to that of Example 1, and the magnetron sputtering target and sputtering parameters are changed accordingly according to the change of the UBM structure. Example 10

[0049] A semiconductor device structure, the overall structure is the same as that of Example 1, except that: the structure of the UBM is a Ti adhesion layer of 10 nm and a Pd diffusion barrier layer of 1000 nm from bottom to top. The overall preparation process is similar to that of Example 1, and the magnetron sputtering target and sputtering parameters are changed accordingly according to the change of the UBM structure. Embodiment 11

[0050] A semiconductor device structure, the overall structure is the same as that of Example 1, except that: the structure of the UBM is a TiN adhesion layer of 100 nm and a Pt diffusion barrier layer of 10 nm from bottom to top. The overall preparation process is similar to that of Example 1, and the magnetron sputtering target and sputtering parameters are changed accordingly according to the change of the UBM structure. Example 12

[0051] A semiconductor device structure, the overall structure is the same as that of Example 1, except that: the structure of the UBM is respectively a TiW adhesion layer of 100 nm and an Ir diffusion barrier layer of 100 nm from bottom to top. The overall preparation process is similar to that of Example 1, and the magnetron sputtering target and sputtering parameters are changed accordingly according to the change of the UBM structure.

[0052] The results show that the device prepared in the above embodiment will not undergo interface separation even if annealed at 280°C for 12h. Therefore, forming a diffusion barrier layer with a single substance or alloy of platinum group elements can solve the problem of poor bonding of the device after reliability testing due to the diffusion of silver into the UBM adhesion layer.

[0053] Comparative Example 1 A semiconductor device structure, the overall structure is the same as that of Example 1, except that: the UBM layer is an adhesion layer 104 and a seed layer 106 from bottom to top, that is, compared with Example 1, the UBM layer does not have a diffusion barrier layer 105, and the interface is separated after annealing at 280°C for 12h, such as Figure 4 shown.

[0054] Although the embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and cannot be understood as limiting the present invention. A person skilled in the art may change, modify, replace and modify the above embodiments within the scope of the present invention without departing from the principles and purpose of the present invention. The protection scope of the present invention is defined by the claims and their equivalent technical solutions.

Claims

1. A semiconductor device structure, comprising a gold-silver alloy bump and a UBM layer, characterized in that: The UBM layer is composed of a seed layer, a diffusion barrier layer and an adhesion layer, or a diffusion barrier layer and an adhesion layer; the diffusion barrier layer is composed of a single substance of a platinum group element and / or an alloy containing a platinum group element; the device structure is as follows from top to bottom: the bottom of the gold-silver alloy bump is connected to the seed layer, the seed layer is connected to the diffusion barrier layer, the diffusion barrier layer is connected to the adhesion layer, and the adhesion layer is connected to the chip electrode; or the bottom of the gold-silver alloy bump is connected to the diffusion barrier layer, the diffusion barrier layer is connected to the seed layer, the seed layer is connected to the adhesion layer, and the adhesion layer is connected to the chip electrode; or the bottom of the gold-silver alloy bump is connected to the diffusion barrier layer, the diffusion barrier layer is connected to the adhesion layer, and the adhesion layer is connected to the chip electrode.

2. The semiconductor device structure according to claim 1, characterized in that: The diffusion barrier layer is composed of one or more of platinum, rhodium, iridium or alloys thereof.

3. The semiconductor device structure according to claim 1, characterized in that The thickness of the seed layer is 0-500 nm, the thickness of the adhesion layer is 10-1000 nm, and the thickness of the diffusion barrier layer is 10-1000 nm.

4. The semiconductor device structure according to claim 1, characterized in that: The seed layer material is gold or gold alloy.

5. The semiconductor device structure according to claim 1, characterized in that: The material of the adhesion layer is titanium or titanium alloy.

6. The semiconductor device structure according to claim 5, characterized in that: The material of the adhesion layer is titanium, titanium-tungsten or titanium-nitrogen alloy.

7. The semiconductor device structure according to claim 1, characterized in that: The thickness of the gold-silver alloy bump is 5-20 μm.

8. The semiconductor device structure according to claim 1, characterized in that: The gold content in the gold-silver alloy bump is 10-60wt%.

9. The method for preparing a semiconductor device structure according to any one of claims 1 to 8, characterized in that: The following steps are involved: S1: preparing an adhesion layer, a diffusion barrier layer and a seed layer in sequence on a chip wafer by a physical vapor deposition method to obtain a UBM layer; or preparing an adhesion layer, a seed layer and a diffusion barrier layer in sequence on a chip wafer by a physical vapor deposition method to obtain a UBM layer; or preparing an adhesion layer and a diffusion barrier layer in sequence on a chip wafer by a physical vapor deposition method to obtain a UBM layer; S2 applies photoresist and exposes the area to be plated; S3 prepares a gold-silver alloy bump by electroplating using a gold-silver electroplating solution; S4 removes excess photoresist and UBM layer.

10. A chip, characterized in that: The chip comprises the semiconductor device structure according to any one of claims 1-8.

11. The chip according to claim 10, characterized in that: The chip is a liquid crystal drive chip, a memory chip, a logic chip or a radio frequency power chip.

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