Dynamic current-sharing layout design method and system for multi-chip parallel power module

Abstract

The invention belongs to the field of power semiconductor devices, and discloses a dynamic current-sharing layout design method and system for a multi-chip parallel power module, and the method comprises two aspects of main power loop layout and wiring and driving loop layout and wiring. A main power loop is designed in a vertical commutation manner, and parallel chip source electrodes and drain electrodes are designed in an integrated manner, so that quasi-common-source-electrode inductors of the chips are consistent and integrated, and parallel dynamic current sharing of multiple gallium nitride chips is facilitated; wiring of the driving loop is in vertical commutation and is vertical to the main power loop, mutual inductance of the power loop to the driving loop is basically zero, and parallel dynamic current sharing of gallium nitride chips is facilitated; when the design is met and grid leading-out ends and Kelvin source leading-out ends of the four chips are symmetrical about the symmetry axis of the main power loop, the mutual inductance of the main power loop to a part of wiring from a drive to each chip grid is equal, and the mutual inductance of the main power loop to a wiring from a Kelvin source to a drive ground of each chip is also equal. And an excellent gallium nitride multi-chip parallel dynamic current sharing effect can be realized.

Description

Technical Field

[0001] The present invention belongs to but is not limited to the technical field of power semiconductor devices, and in particular relates to a dynamic current sharing layout design method and system for a multi-chip parallel power module. Background Art

[0002] In the field of power electronics, power semiconductor devices are the core components for efficient conversion and control of electric energy. The third-generation wide bandgap semiconductor materials, silicon carbide (SiC) and gallium nitride (GaN), have brought revolutionary improvements to the performance of converters with their excellent electrical properties. In particular, gallium nitride (GaN), due to its unique two-dimensional electron gas structure, exhibits better electron mobility, which means that GaN devices have faster switching speeds, thereby improving the response speed and working efficiency of the converter. In addition, GaN devices have lower switching losses and are more efficient in high-frequency applications, which helps to reduce the size and weight of passive devices, which is especially important for application scenarios with limited space. The application of gallium nitride devices has begun to penetrate into multiple industries, including data centers and electric vehicles, with power levels of 10kW to 100kW and higher. However, the manufacturing process of GaN chips is still immature, which limits the effective area and current capacity of a single chip. At present, the more mature one is 650V planar gallium nitride, with a maximum current of GaNsystems150A and Visic 200A for a single chip. Therefore, multiple chips are usually packaged in parallel to obtain a high-current power module to meet the application of high-power occasions.

[0003] Unreasonable layout design of multi-chip GaN power modules will lead to uneven dynamic current distribution. Uneven dynamic current distribution will lead to inconsistent chip switching losses, further leading to inconsistent junction temperatures of parallel chips, and then to uneven performance degradation rates and thermal-mechanical stress of parallel chips, and finally to a significant reduction in module reliability and service life. Therefore, it is very important to design dynamic current sharing for multi-chip parallel gallium nitride (GaN) power modules.

[0004] In order to solve the problem of dynamic current sharing of multi-chip parallel GaN power modules, Cheng Jun and others from GaN Systems established an equivalent circuit for parallel GaN chips and performed a segmented analysis of the turn-on and turn-off processes. They pointed out that the inconsistency of the self-inductance of the drive circuit has little effect on the current sharing. The mutual inductance of the power circuit to the drive circuit and the quasi-common source inductance seriously affect the gate voltage in the di / dt stage, which in turn affects the dynamic current sharing of multi-chip parallel GaN. They also gave design suggestions for minimizing and equalizing the quasi-common source inductance and the mutual inductance of the power circuit to the drive circuit.

[0005] In terms of power circuit design, commercial GaN parallel modules currently use a planar commutation structure, and the source layout of the parallel chips is seriously inconsistent, resulting in poor dynamic current sharing of the modules. In terms of drive circuit design, when a driver chip is used to drive parallel GaN chips, a symmetrical and consistent drive circuit design method is used, such as Figure 1 As shown. (a)(b) are discrete device design schemes, where (a) the driver chip is placed on one side, and the drive signal wiring first reaches the middle of the four chips, and then extends to both sides, driving two GaN chips each, making the two sides symmetrical. (b) The driver chip is in the middle of the four parallel GaN chips, and extends to both sides, driving two GaN chips each, and the two sides are completely symmetrical. Li B et al. proposed a hybrid packaging form to realize a double-sided heat dissipation parallel GaN module, but still placed the driver chip in the middle of the four parallel GaN chips, extending to both sides, driving two GaN chips each, and the two sides are completely symmetrical. In addition, when performing double-sided heat dissipation design, it is necessary to add gaskets to highly match the driver chip and GaN chip.

[0006] In view of the above analysis, the technical problems that need to be solved urgently in the prior art are:

[0007] There is no complete design guidance and theoretical analysis on how to layout and design planar GaN multi-chip parallel dynamic current sharing modules. It is urgent to analyze the impact of layout and wiring on the dynamic current sharing of GaN multi-chip parallel, and provide a complete set of dynamic current sharing layout design theory and guidance for multi-chip parallel GaN power modules. Summary of the invention

[0008] In view of the problems existing in the prior art and the unique symmetrical dual-gate structure of planar GaN, the present invention provides a dynamic current sharing layout design method and system for a multi-chip parallel power module.

[0009] The present invention is implemented as follows: a dynamic current sharing layout design method for a multi-chip parallel power module, characterized in that the method includes two aspects: main power circuit layout and wiring and drive circuit layout and wiring.

[0010] Furthermore, the main power circuit layout and wiring design principles are as follows:

[0011] The four GaN chips connected in parallel at each switch tube position are named die1 to die4, and are placed side by side in a "hand in hand" manner;

[0012] The half-bridge module power chip layout and wiring and decoupling capacitors are constructed into a vertical commutation structure;

[0013] The source and drain of the parallel chips are interconnected nearby while meeting the insulation requirements, and the source and drain layout and wiring of multiple parallel chips are integrated into a whole.

[0014] Furthermore, the layout and wiring of the driving circuit are designed according to the following principles:

[0015] The right gate g1 of die1 is interconnected with the left gate g2 of die2 and led out, the right gate g3 of die3 is interconnected with the left gate g4 of die4 and led out, and the two lead-out terminals are symmetrical about the symmetry axis of the main power circuit;

[0016] The source of die1 closest to the right gate g1 leads to the Kelvin source ks1; the source of die2 closest to the left gate g2 leads to the Kelvin source ks2; the source of die3 closest to the right gate g3 leads to the Kelvin source ks3; the source of die4 closest to the left gate g4 leads to the Kelvin source ks4, ks1-ks2 and ks3-ks4 are symmetrical about the symmetry axis of the main power circuit;

[0017] The driver chip to the chip gate is horizontally wired while meeting insulation requirements, connecting the two gate leads in sequence. The chip Kelvin source lead is horizontally wired to the ground potential of the driver circuit in sequence, and overlaps with the horizontal wiring from the driver chip to the chip gate, forming a vertical commutation structure.

[0018] Another object of the present invention is to provide a dynamic current sharing layout design system for multi-chip parallel GaN power modules, the system specifically comprising:

[0019] Main power circuit design module, used for layout and wiring of the main power circuit;

[0020] A drive circuit design module is used for layout and wiring of the drive circuit;

[0021] The heat dissipation module is used to design the heat dissipation performance of the module.

[0022] In combination with the above technical solutions and the technical problems solved, the advantages and positive effects of the technical solutions to be protected by the present invention are as follows:

[0023] First, the gallium nitride multi-chip parallel connection solution proposed in the present invention is simple in design, and the power circuit and the drive circuit are respectively integrated into a vertical commutation design, which has a significant current sharing effect and is easy to design.

[0024] The present invention separates the drive circuit and the power circuit horizontally. The power circuit part only has a GaN chip and a gasket with the same thickness as the chip, and does not contain other drive circuit devices with inconsistent thickness. When the ceramic substrate is welded on the top of the chip, compared with the existing gallium nitride parallel module that designs the drive circuit above the power circuit, the present invention avoids the problem of height matching between the GaN chip and the driver chip, and also removes the gasket on the top of the gallium nitride chip, further reducing the thermal resistance and improving the heat dissipation performance of the module.

[0025] The present invention analyzes the mechanism of dynamic current sharing of multiple GaN chips in parallel from the perspective of magnetic field, and provides a theoretical explanation for the significant current sharing effect of the multi-chip parallel solution proposed by the present invention.

[0026] Second, as auxiliary evidence of the inventiveness of the claims of the present invention, it is also reflected in the following important aspects:

[0027] (1) The technical solution of the present invention solves a technical problem that people have been eager to solve but have never been able to solve successfully:

[0028] The multi-chip parallel GaN module parallel dynamic current sharing solution proposed in the present invention adopts an integrated vertical commutation structure design in terms of power circuit layout, integrates the drain and source layout and wiring of multiple chips, and the quasi-common source inductance of multiple chips is consistent and can be integrated, which solves the problem of circulating current between quasi-common source inductances in the rising and falling stages of the switching process, affecting the gate voltage and thus affecting the dynamic current sharing. In terms of the drive circuit, an integrated symmetrical vertical commutation layout design perpendicular to the power circuit is adopted, so that the mutual inductance of the power circuit to the drive circuit is close to 0, and the mutual inductance of the power circuit to each part of the four chip drive circuits is basically consistent, which solves the problem of uneven current distribution caused by inconsistent effects of the power circuit on each drive circuit in the rising and falling stages of the switching process.

[0029] In summary, the technical solutions of the present invention achieve the design requirements of multi-chip parallel gallium nitride power modules proposed by predecessors to minimize and equalize the quasi-common source inductance and the mutual inductance of the power circuit to the drive circuit, and solve the technical problems that people have always been eager to solve but have never been successful.

[0030] (2) The expected benefits and commercial value of the technical solution of the present invention after transformation are:

[0031] The technical solution of the present invention can be applied to the design of a module with four planar gallium nitride chips in parallel. Currently, the maximum current is four gallium nitride chips with a rated voltage of 650V and a rated current of 150A from GaNsystems, with a module rated current of 600A and a maximum rated power of 390kW. It can be applied to applications with power levels of 10kW to 250kW and above, such as servers, on-board chargers, and main drive inverters for electric vehicles, which will further improve the performance of high-power inverters. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1The present invention provides an existing gallium nitride multi-chip parallel drive circuit design scheme, (a) a symmetrical design in which four GaN discrete device parallel drive circuits are placed on one side of a power circuit, (b) a symmetrical design in which four GaN discrete device parallel drive circuits are placed in the middle of a power circuit, and (c) a symmetrical design in which four chip parallel drive circuits of a double-sided heat dissipation GaN module are placed in the middle of a power circuit;

[0033] Figure 2 Commercial planar gallium nitride with two symmetrical gate electrodes provided by the embodiments of the present invention, (a) VisIC, (b) Infineon, (c) Yungai Semiconductor;

[0034] Figure 3 1 is a main power circuit layout and wiring design provided by an embodiment of the present invention: (a) front view, (b) side view;

[0035] Figure 4 The driving circuit layout and wiring design provided by the embodiment of the present invention;

[0036] Figure 5 The overall design of the gallium nitride multi-chip parallel double-sided heat dissipation module provided by the embodiment of the present invention;

[0037] Figure 6 This is a schematic diagram of a multi-chip parallel GaN half-bridge module flexible circuit board (FPC) provided by an embodiment of the present invention, (a) upper tube drive circuit, (2) lower tube drive circuit, (c) main power circuit;

[0038] Figure 7 : is a layout design diagram of a gallium nitride multi-chip parallel FPC provided by an embodiment of the present invention, (a) top view, (b) bottom view;

[0039] Figure 8 1 is a Main-DPC layout design diagram provided by an embodiment of the present invention, (a) a top view, (b) a bottom view;

[0040] Fig. 9 1 is a layout design diagram of an up-DPC provided by an embodiment of the present invention, (a) a top view, (b) a bottom view;

[0041] Fig.10 This is a 28mm*28mm*10mm heat sink design provided by an embodiment of the present invention, (a) top view, (b) lower right view;

[0042] Fig.11 This is an equivalent circuit diagram of a quasi-common source inductor with an integrated vertical commutation structure provided by an embodiment of the present invention;

[0043] Fig.12(a) a structural diagram of a horizontal commutation module provided by an embodiment of the present invention, and (b) a quasi-common source inductor equivalent circuit diagram of a horizontal commutation module;

[0044] Fig.13 This is a vertical commutation magnetic field distribution diagram of a power circuit of a gallium nitride multi-chip parallel module provided by an embodiment of the present invention;

[0045] Fig.14 It is a diagram of magnetic field distribution and mutual inductance extraction generated by a power circuit on a driving circuit provided by an embodiment of the present invention;

[0046] Fig.15 is a system module diagram provided by an embodiment of the present invention;

[0047] Fig.16 LTspice simulation results provided by an embodiment of the present invention, (a) multi-pulse waveform, (b) turn-on waveform (left) and turn-off waveform (right) when the on-current is 15A, (c) turn-on waveform (left) and turn-off waveform (right) when the on-current is 40A;

[0048] Fig.17 It is a steady-state result of solid-fluid heat transfer simulation in COMSOL of a multi-chip parallel-connected gallium nitride power module of the present invention provided by an embodiment of the present invention;

[0049] Fig.18 It is a physical module provided by an embodiment of the present invention, (a) a pulse experiment module, (b) a continuous experiment module;

[0050] Fig.19 The embodiments of the present invention provide (a) a multi-pulse experimental waveform, (b) a turn-on transient waveform, and (c) a turn-off transient waveform;

[0051] Fig. 20 (a) 300V / 50A continuous experimental waveform and (b) module steady-state operating temperature distribution provided by the embodiments of the present invention. DETAILED DESCRIPTION

[0052] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0053] The embodiment of the present invention is based on the fact that the inconsistency of the self-inductance value of the driving circuit has little effect on the current sharing, and minimizes and equalizes the multi-chip quasi-common source inductance and the mutual inductance of the power circuit to the driving circuit. The multi-chip GaN parallel design suggestion is for planar gallium nitride with two symmetrical gates such as Figure 2, provides a dynamic current sharing layout design method for multi-chip parallel power modules, which mainly includes two aspects: main power circuit layout and wiring and drive circuit layout and wiring, and is analyzed using four chips in parallel.

[0054] First, the following design principles are proposed for the layout and wiring of the main power circuit:

[0055] The four GaN chips connected in parallel at each switch tube position are named die1 to die4, and are placed side by side in a "hand in hand" manner;

[0056] The half-bridge module power chip layout and wiring and decoupling capacitors are constructed into a vertical commutation structure;

[0057] The source and drain of the parallel chip are interconnected nearby under the condition of meeting the insulation requirements, and the source and drain layout of multiple parallel chips are wired as a whole. The integrated layout can integrate the quasi-source inductors of multiple chips, remove the quasi-common source inductor circulating current, and reduce the impact on the dynamic current sharing of multiple parallel chips.

[0058] Secondly, the following design principles are proposed for the layout and wiring of the drive circuit:

[0059] like Figure 4 The right gate g1 of die1 and the left gate g2 of die2 are interconnected and led out; the right gate g3 of die3 and the left gate g4 of die4 are interconnected and led out, and the two lead-out ends are symmetrical about the symmetry axis of the main power circuit.

[0060] like Figure 4 , the source of die1 closest to the right gate g1 leads to the Kelvin source ks1; the source of die2 closest to the left gate g2 leads to the Kelvin source ks2; the source of die3 closest to the right gate g3 leads to the Kelvin source ks3; the source of die4 closest to the left gate g4 leads to the Kelvin source ks4. ks1-ks2 and ks3-ks4 are symmetrical about the symmetry axis of the main power circuit. The physical connection between the Kelvin source and the power source is only Figure 4 Leading point.

[0061] The driver chip to the chip gate is wired horizontally while meeting the insulation requirements, and the two gate leads are connected in sequence. The chip Kelvin source lead is horizontally wired and connected to the driving circuit ground potential in sequence, and overlaps with the horizontal wiring from the driver chip to the chip gate, forming a vertical commutation structure. The advantages are: ① the driving circuit forms a vertical commutation result with low self-inductance; ② the mutual inductance of the power circuit to the four chip driving circuits is basically equal and close to 0. ③ The mutual inductance of each part of the power circuit to the four chip driving circuits is equal, and the current sharing effect is significant. (Theoretical analysis from the magnetic field perspective will be given later)

[0062] According to the layout and wiring design principles proposed in the present invention, taking a gallium nitride chip with a rated voltage of 650V, a rated current of 60A and a model number of GS-065-060-2-D2 as an example, a hybrid double-sided packaging solution of a flexible circuit board (FPC) and a direct copper plating (DPC) substrate is adopted to describe in detail the multi-chip GaN power module parallel dynamic current sharing layout design method and processing solution proposed in the present invention.

[0063] Multi-chip parallel GaN power module dynamic current sharing layout design structure framework:

[0064] The main power circuit is constructed with two layers of FPC and DPC. Figure 7 As shown in the left figure, the GaN chip pads are designed in a "hand-in-hand" arrangement on the upper copper layer of the FPC. The source and drain pads of the GaN chip are connected as a whole according to the electrical relationship and pad shape by copper plating. The upper copper and lower copper of the FPC are connected through vias at the GaN chip pad position. The lower copper performs RDL on the GaN source and drain. Figure 7 Right picture, welding with the corresponding position of the upper copper of main-DPC Figure 8 In addition, DPC designs the busbar and output terminal connections based on electrical connection and insulation considerations: DC+, DC-, and AC. The DC+ busbar (also DC-) is connected through DPC vias to form a vertical commutation structure, such as Figure 8 Right picture.

[0065] The drive circuit is designed with FPC, and the components used in the drive circuit are packaged with SMD. The components used in the drive circuit are packaged with SMD, and the pads are designed on the top. The driver chip and peripheral circuits are located on the left side of the GaN chip. According to the drive loop layout design guide in Section 2, the layout of the driver to the four GaN gates and the layout of the four GaN Kelvin sources to the driver ground are placed in the top and bottom copper layers of the FPC, respectively. In addition, Figure 8 On the left, the top copper layer of the main DPC corresponding to the FPC drive position is connected to the ground potential to form a shielding layer to reduce the electromagnetic interference of the main power circuit magnetic field to the drive circuit.

[0066] In addition, it is necessary to design a gasket, a heat dissipation substrate (up-DPC), a heat sink, and a positioning pad. The thickness of the gasket is the same as that of the chip. It is used to connect the chip source and the chip heat dissipation top surface to achieve the same potential as the chip substrate surface and the source, and at the same time play a role in balancing and supporting the up-DPC. The up-DPC acts as an insulator, and the heat sink can be welded on its top surface. There are positioning pads on the FPC to align it when soldering to the main DPC. The assembly diagram of the module is as follows Figure 5As shown, the GaN chip, spacer and driving circuit are soldered on the top of the FPC, and the bottom of the FPC is soldered on the top of the main DPC. The GaN chip and the top of the spacer are soldered to the bottom of the upper PCB, the heat sink is soldered to the bottom of the main PCB and the top of the upper PCB, and finally the cooling fan is installed on the heat sink.

[0067] Specific steps for dynamic current sharing layout design of multi-chip parallel GaN power modules:

[0068] Step 1: Design the GS-065-060-2-D2 GaN die schematic library and package library in Altium Designer.

[0069] Step 2: Design the flexible printed circuit (FPC) schematic in Altium Designer. This case design will build a GaN half-bridge power module. The flexible printed circuit (FPC) contains a power GaN chip and its drive circuit. Each switch position of the half bridge uses 4 GaN chips in parallel, and the upper and lower switches are driven by a driver chip respectively. The drive circuit design adopts the solution selection and design recommended by GaNsystems' "GN001Application Guide Design with GaN Enhancementmode HEMT". The schematic design is as follows Figure 6 Shown: (a) upper tube driving circuit, (b) lower tube driving circuit, (c) main power circuit.

[0070] Step 3: Design the layout and wiring of the GaN chip in the flexible circuit board (FPC) in Altium Designer. A two-layer flexible circuit board (FPC) structure is used. The GaN chip pad is designed on the upper copper layer of the flexible circuit board (FPC). The chip pad position is connected to the upper copper layer and the lower copper layer through vias. The lower copper layer is connected to the main-DPC for RDL. The four chips at each switch tube position are arranged in a straight line in the form of "hand in hand", and the upper and lower switch tubes are aligned and arranged in the appropriate position. The source and drain pads of the GaN chip are connected as a whole according to the electrical relationship and pad shape by copper plating.

[0071] Step 4: Design the driver layout and wiring in the flexible printed circuit (FPC) in Altium Designer. The devices used in the driver circuit are packaged in SMD, and the pads are designed on the upper surface. The driver chip and peripheral circuit layout and wiring follow the scheme recommended by "GN001 Application Guide Design with GaN Enhancement mode HEMT" and are placed on the left (or right) side of the gallium nitride chip. The gate g1 on the right side of die1 is interconnected with the gate g2 on the left side of die2 and led out; the gate g3 on the right side of die3 is interconnected with the gate g4 on the left side of die4 and led out, and the two lead-out ends are symmetrical about the symmetry axis of the main power circuit. The gate wiring of the drive signal to each chip starts from the drive resistor and is copper-plated to the two lead-out ends in sequence, and is laid out on the lower copper layer. The source of die1 closest to the right gate g1 leads to the Kelvin source ks1; the source of die2 closest to the left gate g2 leads to the Kelvin source ks2; the source of die3 closest to the right gate g3 leads to the Kelvin source ks3; the source of die4 closest to the left gate g4 leads to the Kelvin source ks4, ks1-ks2 and ks3-ks4 are symmetrical about the symmetry axis of the main power circuit. The Kelvin source wiring from the driving ground to each chip starts from the driving ground and is copper-plated to the four lead-out points in sequence, and is laid out on the upper copper layer, overlapping with the gate wiring from the driving signal to each chip.

[0072] Steps 1-4 complete the design of the flexible printed circuit (FPC). The layout design of the flexible printed circuit (FPC) is as follows: Figure 7 As shown, the upper surface is the GaN chip and driver, and the lower surface is the RDL of the GaN chip source and drain. At the same time, the lower surface is provided with pads 1-7 and RDL pads for welding and fixing the flexible circuit board (FPC) and the main-DPC.

[0073] Step 5: Design the main-DPC required for the main power circuit in solidworks. Use a DPC with a Cu / ALN / Cu0.3mm / 0.635mm / 0.3mm structure. According to the flexible circuit board (FPC) layout and chip RDL distribution designed in steps 1-4, design the copper layer on the main-DPC surface. Figure 8 The D and S on the upper side of the DPC shown are the RDL welding points of the chip on the flexible circuit board (FPC). The DPC designs the busbar and output terminal connections: DC+, DC-, and AC based on electrical connection and insulation considerations and chip position. The left copper layer is connected to the ground potential at the bottom of the drive circuit to form a shielding layer to reduce the electromagnetic interference of the main power circuit magnetic field to the left drive circuit. The DC+ busbar (can also be DC-, and the busbar terminal position is adjusted at the same time) is connected through the DPC via to form a vertical commutation structure.

[0074] Step 6: Design the chip top connection up-DPC in solidworks. Use Cu / ALN / Cu0.3mm / 0.635mm / 0.3mm structure DPC. Fig. 9 As shown, the top heat sink plays the role of ① connecting the chip source and the heat sink through the gasket to achieve the same potential between the chip heat sink and the source. ② Isolation, the heat sink can be welded on the other side of the DPC.

[0075] Step 7: Design a gasket. The gasket is 0.27mm, which is basically consistent with the thickness of the chip. It is used to connect the chip source and the heat dissipation surface, and at the same time plays a role in balancing and supporting the DPC.

[0076] Step 8: Design the radiator according to the position and space of the upper and lower pipes of the half-bridge, such as Fig.10 This case is designed with a 28mm*28mm*10mm radiator and 2.5mm studs on the radiator, which is suitable for installing a 30mm*30mm small fan.

[0077] Physical processing steps of multi-chip parallel dynamic current sharing GaN power module:

[0078] Step 1: Prepare the designed flexible circuit board (FPC), main-DPC, up-DPC, GaN chip, decoupling capacitors and devices required for the driving circuit according to the design steps.

[0079] Step 2: The chip, gasket and flexible circuit board (FPC) are reflow soldered using 227℃ Sn99Cu0.7Ag0.3 solder paste.

[0080] Step 3: Place the flexible printed circuit (FPC) on the main-DPC, the up-DPC on the top of the chip, the heat sink on the top and bottom, and the decoupling capacitors and terminals on the main-DPC. The components used in the drive circuit are placed on the flexible printed circuit (FPC). Use 183℃ Sn63Pb37 solder paste for reflow soldering.

[0081] Step 4: Glue filling: use silicone gel (Nusil-R2188) to fill the gap between the upper and lower DPCs to enhance the insulation of the module.

[0082] Step 5: Install other external components such as pillars, small fans, etc.

[0083] The dynamic current sharing layout design method for multi-chip parallel power modules proposed in the present invention analyzes the current sharing mechanism:

[0084] 1. The power drain and source of the parallel GaN chips are integrated and form a vertical commutation structure. The current path of each chip is the same and can be regarded as a whole. Figure 3 , the Kelvin source is set on the source closest to the extraction gate, such as Figure 4 ks1, ks2, ks3, ks4, and other positions have no physical connection with the power source. Therefore, the quasi-common source inductors of the four chips can be regarded as a whole, such as Fig.11 Medium cs , which solves the problem of inconsistent quasi-common source inductance in horizontal commutation structure, such as Fig.12 .

[0085] 2. The power circuit forms a vertical commutation structure, the drive circuit forms a vertical commutation structure, the drive circuit is physically decoupled from the power circuit and is located above the power circuit, and the commutation paths are perpendicular to each other, such as Figure 3 and 4 .

[0086] 3. During the switching process, the switch tube commutates, and the commutation current flows through the vertical commutation formed by the power loop and the decoupling capacitor. The upper and lower conductors flow through commutation currents of equal magnitude and opposite directions. The magnetic fields inside parallel plane conductors increase each other, and the magnetic fields outside parallel plane conductors cancel each other. At the same time, the magnetic fields form a closed loop. The front view of the power vertical commutation loop and the magnetic field distribution are shown in the figure. Fig.13 shown.

[0087] 4. Select three points a, b, and c on the upper side of the power loop. Point c is located at the symmetry axis, and points a and b are symmetrical about point c. The magnetic field at each point is the integral of the magnetic field of the parallel plane conductor unit current at this point.

[0088] 5. When the commutation current is evenly distributed horizontally in the conductor, the magnetic field strength at point c is horizontal. Points a and b have horizontal and vertical components. Points a and b are symmetrical about the axis of symmetry. The magnetic field strength in the horizontal direction is equal in magnitude and direction. Fig.13 middle The magnetic field strength in the vertical direction is equal in magnitude and opposite in direction. Fig.13 middle And due to the edge effect, the magnetic field strength is stronger at the edge of the power loop.

[0089] 6. The drive circuit is designed above the main power circuit. The horizontal magnetic field strength does not pass through the drive circuit, and the vertical magnetic field passes through the drive circuit. The drive circuit design proposed by the present invention has a schematic diagram of the vertical magnetic field strength of the layout and wiring from the drive chip to the chip gate and the Kelvin source to the drive ground. Fig.14 The magnetic field through which the driver chip-to-chip gate wiring and the Kelvin source-to-driver ground wiring pass is equal in magnitude and opposite in direction (the starting direction of the wiring changes).

[0090] 7. Biot-Savart Law: The mutual inductance of the power circuit to the drive circuit is: M=B / I.

[0091] 8. The magnetic flux passing through the driver chip to the chip gate wiring increases as the wiring extends from left to right, and reaches the maximum when it reaches the symmetry axis. The magnetic flux decreases as it extends to the right across the symmetry axis, and the magnetic flux is equal at the position symmetrical to the symmetry axis. This is because the area symmetrical to the symmetry axis is Fig.14 The magnetic field integral of the area circled symmetrically about the axis of symmetry is 0. The magnetic flux distribution from the Kelvin source to the driving ground wiring is similar, but in the opposite direction. Therefore, the total magnetic flux generated by the main circuit commutation passing through the driving loop (driving resistor to chip gate wiring and Kelvin source to driving ground wiring) is basically 0.

[0092] 9. Based on the above analysis, the design proposed by the present invention has equal mutual inductance between the main power circuit and each part of the four chip drive circuits. The mutual inductance between the vertical commutation power circuit and the drive chip to chip gate wiring increases from the edge to the middle, and the positions symmetrical about the symmetry axis are equal. The mutual inductance between the vertical commutation power circuit and the Kelvin source to the drive ground wiring increases from the edge to the middle, and the positions symmetrical about the symmetry axis are equal. The signs of the two are opposite, and the sum of the two is basically 0.

[0093] 10. The driver loop layout is routed from the left side of the power loop to the right side, and 31 points are uniformly selected as the gate and Kelvin source lead-out points. Ansys simulation is used to extract the partial inductance between the power loop and the driver to the chip gate and between the power loop and the Kelvin source to the driver ground, such as Fig.14 As shown, the mutual inductance is basically equal on the axis of symmetry, and the sum of the two is close to 0, which confirms the above theoretical analysis.

[0094] Conclusion: The main power circuit is commutated vertically, and the source and drain of the parallel chip are integrated, so that the quasi-common source inductance of the chip is consistent and integrated, which is conducive to the dynamic current sharing of multiple GaN chips in parallel; when the drive circuit wiring is vertically commutated and designed perpendicular to the main power circuit, the mutual inductance of the power circuit to the drive circuit is basically 0, which is conducive to the dynamic current sharing of GaN chips in parallel; when the above design is met and the drive lead-out terminal and the Kelvin source lead-out terminal are symmetrical about the symmetry axis of the main power circuit, the mutual inductance of the main power circuit to the drive to chip gate wiring and the mutual inductance of the Kelvin source to the drive ground wiring are equal, which can achieve excellent dynamic current sharing effect of multiple GaN chips in parallel.

[0095] like Fig.15 As shown, an embodiment of the present invention provides a dynamic current sharing layout design system for a multi-chip parallel GaN power module, comprising:

[0096] Main power circuit design module, used for layout and wiring of the main power circuit;

[0097] The drive circuit design module is used for layout and routing of the drive circuit.

[0098] The heat dissipation module is used for heat dissipation design of the module.

[0099] According to the method described in the present invention, a multi-chip parallel GaN power module is designed using a gallium nitride chip with a rated voltage of 650V, a rated current of 60A, and a model number of GS-065-060-2-D2, and the dynamic current sharing effect is verified.

[0100] The design module was imported into Ansys Q3D software and the inductance and mutual inductance were extracted. Table 1 lists the extracted values ​​of the main power loop and the lower drive loop, where L gx is the value of the inductance from the positive electrode of the drive power decoupling capacitor to the GaN chip x gate, L sx is the inductance from the chip x Kelvin source to the negative electrode of the driver power decoupling capacitor, L p is the inductance value of the main power loop. The bold data on the diagonal of the table are self-inductance values, and the other data are mutual inductance values.

[0101] The parasitic inductance in Table 1 is imported into LTspice to construct an equivalent simulation circuit. The simulation results are shown in Fig.16 The figure shows that the on-state current of the four GaN chips connected in parallel is equal. There is some dynamic current non-uniformity in the turn-on and turn-off transients. g = 10Ω, the maximum turn-on transient current non-uniformity is 1.35 A, and the maximum turn-off transient current non-uniformity is 0.78 A. In addition, the current non-uniformity is basically independent of the magnitude of the turn-on current.

[0102] The designed module was imported into Comsol software for thermal resistance extraction. The thermal resistance from the GaN chip to the top copper layer of the up-DPC was 0.16K / W, the thermal resistance from the GaN chip to the bottom copper layer of the main-DPC was 0.62K / W, and the double-sided heat dissipation thermal resistance was 0.144K / W. The solid fluid heat transfer simulation of the multi-chip parallel GaN power module was also performed. The loss of each chip was 15W. Two small fans with an air intake of 10CFM were used. The maximum temperature of the module was 75.5℃. Fig.17 .

[0103] Fig.18 For the actual module, the left picture does not have the up-DPC and heat sink welded. A 4mm thick gasket is used to raise the flexible printed circuit (FPC) so that the Rogowski coil can be placed in the hole. The current flowing through each chip is measured to verify the current sharing effect. The pulse experiment waveform is as follows Fig.19 As shown in (a), the currents of the four chips are equal when they are on. Fig.19 (b) shows the transient waveforms of turn-on and turn-off; the transient currents of the four chips are basically the same, and the experimental waveforms are consistent with the simulation waveforms. The maximum unequal currents of turn-on and turn-off transients are also close to the simulation results, which are 1.3A and 0.84A respectively.

[0104] The complete DPC and FPC hybrid double-sided cooling GaN power module is processed using the process steps proposed in the present invention; the module is as follows Fig.18 As shown in the figure on the right, at this time, it is impossible to measure the current of each chip, but only the total current output by the parallel chips. Fig. 20 The left figure shows the voltage and current waveforms during continuous operation at 300V bus voltage, 50A current amplitude, pure inductive load and 245kHz output frequency. Fig. 20 The figure on the right shows the temperature distribution of the module in steady-state operation under double-sided forced air cooling working conditions. The highest temperature appears in the middle of the two layers of DPC and the isolated power supply, and the temperature on the surface of the upper DPC is 54.1°C, proving that the module has the ability to operate continuously.

[0105] Table 1: Extracted values ​​of partial self-inductance and mutual inductance of the designed multi-chip parallel GaN power module Unit: nH

[0106]

[0107] It should be noted that the embodiments of the present invention can be implemented by hardware, software, or a combination of software and hardware. The hardware part can be implemented using dedicated logic; the software part can be stored in a memory and executed by an appropriate instruction execution system, such as a microprocessor or dedicated design hardware. It can be understood by a person of ordinary skill in the art that the above-mentioned devices and methods can be implemented using computer executable instructions and / or contained in a processor control code, such as a carrier medium such as a disk, CD or DVD-ROM, a programmable memory such as a read-only memory (firmware), or a data carrier such as an optical or electronic signal carrier. Such code is provided on the carrier medium. The device and its modules of the present invention can be implemented by hardware circuits such as very large-scale integrated circuits or gate arrays, semiconductors such as logic chips, transistors, etc., or programmable hardware devices such as field programmable gate arrays, programmable logic devices, etc., can also be implemented by software executed by various types of processors, and can also be implemented by a combination of the above-mentioned hardware circuits and software, such as firmware.

[0108] The above description is only a specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Any modifications, equivalent substitutions and improvements made by any technician familiar with the technical field within the technical scope disclosed by the present invention and within the spirit and principle of the present invention should be covered by the protection scope of the present invention.

Claims

1. A dynamic current sharing layout design method for multi-chip parallel power modules, characterized in that: The following steps are involved: 1) Main power circuit layout and wiring design: When planar GaN chips are connected in parallel, they are placed side by side in a "hand in hand" format to form a symmetrical layout; The power circuit layout of the half-bridge module adopts a vertical commutation structure; The source and drain of the parallel chips are interconnected as close as possible while meeting the insulation requirements, and the source and drain layout and wiring of multiple parallel chips form an integrated whole. 2) Driving circuit layout and wiring design: For the four chips connected in parallel, chip 1 and chip 2 "hold hands" and lead out the gate, and chip 3 and chip 4 "hold hands" and lead out the gate, and the two lead-out terminals are symmetrical about the symmetry axis of the main power circuit; the Kelvin source lead-out terminals of the four chips select the source closest to the gate lead-out terminal of each chip, and are basically symmetrical about the symmetry axis. The drive signal wiring is horizontally wired under the condition of meeting the insulation requirements, connected to the chip gate lead-out terminals in sequence, and the gate wiring is ensured to be symmetrical about the symmetry axis of the main power circuit; The Kelvin source lead-out wiring is horizontally connected to the ground potential of the driving circuit and overlaps with the driving signal wiring up and down to form a vertical commutation structure to reduce the self-inductance value of the driving circuit and make the mutual inductance of the power circuit to the driving circuit close to zero.

2. The method according to claim 1, characterized in that The main power circuit layout design includes: The vertical commutation integrated design of the power circuit makes the drain and source circuits and layout of each parallel chip exactly the same, so the quasi-common source inductance is the same and can be integrated. There will be no circulating current between the quasi-common source inductors, thereby reducing the impact on the gate voltage and dynamic current.

3. The method according to claim 1, characterized in that The drive circuit layout design includes: The drive circuit is horizontally separated from the power circuit, and the drive circuit is placed on the left or right side of the power circuit. The power circuit only contains the gallium nitride power chip and gaskets of the same height without other components of different heights; therefore, the power chip does not need to be height matched when welding the ceramic substrate, and the top of the chip can be directly welded to the bottom of the ceramic substrate to reduce thermal resistance. The signal wiring from the driver chip to the chip gate and the wiring from the Kelvin source to the driving ground form a vertical commutation structure, and are perpendicular to the power loop, and the mutual inductance between the power loop and the driving loop is basically 0. When the chip gate lead-out end is symmetrical about the symmetry axis of the power loop, the partial mutual inductance of the power loop and the driving signal line of each chip is equal; when the Kelvin source is symmetrical about the symmetry axis, the partial mutual inductance of the power loop and the Kelvin source to the driving ground wiring of each chip is equal; the mutual inductance of the power loop to each part of the driving loop of each chip can be equal, and excellent dynamic current sharing characteristics can be achieved.

4. The method according to claim 1, characterized in that: The layout of the main power circuit and the drive circuit can adopt a hybrid packaging solution combining a Cu / ALN / Cu direct copper plating (DPC) substrate and a flexible printed circuit board (FPC), wherein: The main power circuit uses DPC substrate and FPC for busbar connection and power chip layout connection; The drive circuit is laid out on the FPC, and the FPC is welded above the main power circuit to form a sandwich structure with double-sided heat dissipation.

5. The method according to claim 1, characterized in that The main power circuit can be constructed with two layers of FPC and DPC. The pads of the GaN chip are designed to be arranged "hand in hand" on the upper copper layer of the FPC. The source and drain pads of the GaN chip are connected as a whole according to the electrical relationship and pad shape by copper plating. The upper copper and lower copper of the FPC are connected through vias at the position of the GaN chip pads. The lower copper performs RDL welding on the GaN source and drain and the corresponding position of the upper copper of the main-DPC. The main-DPC designs the busbar and output terminals according to electrical connection and insulation and connects them through vias to form a vertical commutation structure.

6. The method according to claim 1, characterized in that The drive circuit can be designed on the FPC. The components used in the drive circuit are packaged in SMD, with the pads designed on the top. The drive chip and peripheral circuits are located on the left side of the gallium nitride chip. The top copper layer of the main DPC corresponding to the FPC drive position is connected to the ground potential to form a shielding layer to reduce the electromagnetic interference of the main power circuit magnetic field on the drive circuit.

7. A dynamic current sharing design system for multi-chip parallel power modules, characterized in that: The system includes: Main power circuit module: includes multiple planar GaN chips, which are placed side by side in a "hand-in-hand" form and interconnected through a vertical commutation structure to form an integrated layout. The layout makes the quasi-source inductance of each chip basically consistent, reducing the impact of the quasi-common source inductance circulating current on the current sharing; Driving circuit module: including the driving chip and peripheral circuits on the FPC, the driving signal wiring and the chip Kelvin source lead-out wiring are horizontally connected in sequence to form a vertical commutation structure, and the driving circuit wiring and the main power circuit wiring are arranged vertically to each other; Heat dissipation module: including gasket, heat dissipation substrate (up-DPC) and heat sink. The thickness of the gasket is the same as that of the chip. It is used to connect the chip source and the chip heat dissipation top surface to achieve the same potential as the chip substrate surface and the source, and at the same time play the role of balancing and supporting the up-DPC. The up-DPC plays an insulating role and is welded to the heat dissipation surface of the GaN chip, and the heat sink is welded on the other side. The Main-DPC and up-DPC form a sandwich structure to achieve double-sided heat dissipation of the module.

8. The system according to claim 7, characterized in that The main power circuit module further comprises: Decoupling capacitor bank, used to minimize the parasitic inductance of the power loop in the vertical commutation structure and to ensure the consistency of the current path; The bus terminals, including DC+, DC- and AC output terminals, are arranged on the DPC substrate, and the DC+ or DC- vias are connected to form a vertical commutation path.

9. The system according to claim 7, characterized in that The layout design of the drive circuit module is as follows: The driving signal wiring and the Kelvin source wiring overlap each other in the vertical commutation structure, and the magnetic field cancellation effect is used to make the total mutual inductance of the power circuit to the driving circuit close to zero. The signal wiring from the driver chip to the chip gate and the wiring from the chip Kelvin source to the driver ground are symmetrically distributed about the symmetry axis of the main power loop, ensuring that the mutual inductance value of each part of the power loop to each chip driver loop is equal, thereby achieving a significant dynamic current sharing effect.

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