Preparation method of high-precision large-area ultrathin hollow hard mask

Abstract

The invention belongs to the field of micro-nano manufacturing, and particularly relates to a preparation method of a high-precision large-area ultrathin hollowed-out hard mask. The invention provides a preparation method of a high-precision large-area ultrathin hollowed-out hard mask, and the method comprises the steps: carrying out the multi-step etching of a thin film layer deposited on the front surface of a silicon substrate, keeping a part of thickness of the thin film layer in the first etching process, and completely etching the thin film layer after the wet etching of the silicon substrate is completed. When the pattern size is smaller or the thin film layer is thinner, the thin film layer can be prevented from being broken in the wet etching process.

Description

Technical Field

[0001] The present application belongs to the field of micro-nano manufacturing, and specifically relates to a method for preparing a high-precision, large-area, ultra-thin hollow hard mask. Background Art

[0002] Hollow hard mask technology is an advanced micro-nano processing method that uses a hard mask with precisely defined holes to achieve direct deposition or transfer of materials to form patterns at the micron to nanometer scale. This technology provides an efficient, low-cost and environmentally friendly patterning solution for the field of micro-nano manufacturing with its characteristics of no need for photosensitive resist, reusability and high throughput. Hollow hard masks are usually made of hard materials such as silicon carbide and silicon nitride to ensure good mechanical strength and chemical stability. It has a wide range of applications, including biosensors, flexible substrate patterning, photonic crystal structures, nanoelectronics, biological sample patterning, and screening and self-assembly of charged particles. In addition, the development of dynamic mask lithography technology has further expanded its application potential in the manufacture of complex three-dimensional structures, making it occupy an important position in micro-nano manufacturing technology.

[0003] At present, the preparation of such hollow patterns generally uses silicon nitride or silicon oxide as a hard mask layer to carry the pattern, and the pattern transfer of the hard mask layer is completed by deep ultraviolet lithography and dry etching, and then the deep silicon etching process is used to etch the silicon substrate to obtain the hollow structure. However, in the existing deep silicon etching process, wet etching is the cheapest and simplest method, which is widely used in industry and production. However, because the film layer is in high-temperature liquid for a long time, the violent liquid flow and excessive surface tension during the flow and drying of the liquid in wet etching can easily cause the film layer to break. Especially when the film layer is thin, the area is large, and the film pattern is dense, the mechanical strength of the hollow pattern layer will drop rapidly, and it is more likely to break during the wet etching process. There is an urgent need for a large-area, low-stress, high-density pattern ultra-thin hollow hard mask preparation process. Summary of the invention

[0004] In order to solve the defects of the prior art, the present application provides a method for preparing a large-area, low-stress, and high-density pattern ultra-thin hollow hard mask, specifically, depositing a thin film layer and a hard mask layer, such as a silicon nitride layer, on both sides of a silicon substrate, and performing an annealing process, and then completing the pattern transfer by etching, and then etching the silicon substrate using a wet etching process, and finally performing a secondary deposition of metal and film layer materials; wherein the front pattern of the thin film layer is etched in multiple steps, and a portion of the thickness is retained during the first etching process so that the thin film layer remains intact in the wet etching process environment, and then the pattern of the thin film layer is completely etched after the wet etching process is completed; in addition, the secondary deposition of metal and film layer materials can further reduce the pattern size of the hollow pattern layer, breaking through the limitations of photolithography.

[0005] The present application provides a method for preparing a high-precision large-area ultra-thin hollow hard mask, comprising the following steps:

[0006] 1) depositing a thin film layer on the front side of the silicon substrate, depositing a hard mask layer on the back side of the silicon substrate, and annealing;

[0007] 2) using a photolithography process and a dry etching process to transfer the front pattern to the thin film layer; wherein, when etching the thin film layer using the dry etching process, a portion of the thickness of the thin film layer is reserved and the integrity of the thin film layer is maintained;

[0008] 3) Using photolithography and dry etching processes to transfer the backside pattern to the hard mask layer to form a window for etching the silicon substrate;

[0009] 4) using a wet etching process to completely etch the silicon substrate between the front pattern and the back pattern to form an etching hole;

[0010] 5) A dry etching process is used to completely etch the reserved partial thickness of the thin film layer corresponding to the front pattern on the thin film layer, wherein the direction of the complete etching is from the front to the back of the silicon substrate, to obtain a hollow hard mask.

[0011] The method further includes: coating the surface of the hollow hard mask.

[0012] A second aspect of the present application provides a hard mask, which is prepared by the preparation method of the first aspect.

[0013] The beneficial effects of this application are:

[0014] 1. The present application can produce a large-area, ultra-thin hollow pattern layer with a small-size pattern. Through a two-step etching method, the thin film layer can maintain its integrity during deep silicon etching of the silicon substrate, thereby avoiding the fragmentation of the thin film layer during wet etching of the silicon substrate.

[0015] 2. The present application can obtain a clean and tidy hollow pattern layer. The two-step etching method allows the thin film layer to remain intact after the wet etching of the silicon substrate is completed. Therefore, it is allowed to use a cleaning solution such as piranha solution to clean the precursor, which can effectively clean the impurities remaining during the etching process.

[0016] 3. This application uses a hollow hard mask to perform front or back coating to further reduce the size of the hollow hard mask pattern. By precisely controlling the coating process, the limitations of the photolithography pattern can be broken through.

[0017] 4. This application uses a reasonable design of the back pattern so that the chips can be directly shredded after the entire process is completed, avoiding the slicing process.

[0018] The present application can prepare micron and nanometer-scale hollow patterns on thin layers of sub-micron-thick silicon nitride, silicon oxide, silicon carbide, aluminum oxide, etc., and the area of ​​the ultra-thin hollow pattern layer prepared can reach square centimeters. It has the advantages of large area, low stress, high pattern density, low thickness, no deformation, no collapse, and no breakage. The process is simple, time-saving and low-cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is a schematic diagram of the cross-sectional structure of the hollow hard mask of the present application.

[0020] Among them, 1 is a silicon substrate, 2 is a thin film layer formed by growing silicon nitride by LPCVD on the front side, 3 is a hard mask layer formed by growing silicon nitride by LPCVD on the back side, 4 is a metal layer, 5 is silicon nitride grown by PECVD on the front side, and 6 is silicon nitride grown by PECVD on the back side.

[0021] Figure 2 This is the hollow hard mask manufacturing process using a single-step etching process in Comparative Example 1.

[0022] Figure 3 This is the hollow hard mask manufacturing process using a two-step etching process in Example 1.

[0023] Figure 4 This is a schematic diagram of the front and back pattern designs of this application.

[0024] Among them, (a) is a schematic diagram of the design of the microhole array on the front side, and (b) is a schematic diagram of the design of the back side for hollowing out and etching the silicon substrate.

[0025] Figure 5 This is the hollow hard mask prepared in Comparative Example 1.

[0026] Among them, (a) is a schematic diagram of the prepared micropore array, in which the pore diameter is 3 μm and the pore spacing is 6 μm. (b) to (c) show the fragmentation of part of the micropore array structure under a light microscope, and the final pattern layer is mostly fragmented.

[0027] Figure 6 This is the hollow hard mask prepared in Example 1.

[0028] Among them, (a) is a schematic diagram of the prepared micropore array, in which the pore diameter is 1 μm and the pore spacing is 2 μm. (b) to (c) show that the array structure of the silicon nitride graphic layer is intact and has a good yield. (d) to (e) show the silicon sidewall angle and smooth morphology of the substrate after wet etching. DETAILED DESCRIPTION

[0029] The following describes the implementation of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific implementations, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application.

[0030] Before further describing the specific implementation methods of the present application, it should be understood that the scope of protection of the present application is not limited to the specific specific implementation methods described below; it should also be understood that the terms used in the examples of the present application are for describing specific specific implementation methods rather than for limiting the scope of protection of the present application; in the specification and claims of the present application, unless otherwise expressly stated herein, the singular forms "a", "an" and "the" include plural forms.

[0031] When the embodiments give numerical ranges, it should be understood that, unless otherwise specified in the present application, the two endpoints of each numerical range and any numerical value between the two endpoints can be selected. Unless otherwise defined, all technical and scientific terms used in the present application have the same meaning as those generally understood by those skilled in the art. In addition to the specific methods, equipment, and materials used in the embodiments, according to the grasp of the prior art by those skilled in the art and the record of the present application, any method, equipment, and material of the prior art similar or equivalent to the methods, equipment, and materials described in the embodiments of the present application can also be used to realize the present application.

[0032] The purpose of this application is to provide a method for preparing a high-precision large-area ultra-thin hollow hard mask, which can prepare an ultra-thin hollow pattern layer with large area, low stress, high pattern density and no deformation. The basic method is: the pattern is transferred to a thin film layer (such as a silicon nitride layer) deposited on a silicon substrate by a photolithography process, and an annealing process is performed, followed by etching of the thin film layer, and then the silicon substrate is etched by a deep silicon etching method, and finally the metal coating on the back and the secondary deposition of double-sided silicon nitride are completed. It should be emphasized that annealing after the silicon nitride is deposited can effectively eliminate residual stress to improve mechanical stability, and obtain silicon nitride with an average stress as low as 19.28Mpa; and the thin film layer is etched in multiple steps, by retaining part of the thickness of the thin film layer during the etching process, and then completely etching the thin film layer after the wet etching of the silicon substrate is completed, it can prevent the thin film layer from breaking during the wet etching process when the pattern size is smaller or the thin film layer is thinner.

[0033] In the present application, the substrate refers to the material prepared in the previous step in the method of the present application.

[0034] The present application provides a method for preparing a high-precision large-area ultra-thin hollow hard mask, comprising the following steps:

[0035] 1) depositing a thin film layer on the front side of the silicon substrate, depositing a hard mask layer on the back side of the silicon substrate, and annealing;

[0036] 2) using a photolithography process and a dry etching process to transfer the front pattern to the thin film layer; wherein, when etching the thin film layer using the dry etching process, a portion of the thickness of the thin film layer is reserved and the integrity of the thin film layer is maintained;

[0037] 3) Using photolithography and dry etching processes to transfer the backside pattern to the hard mask layer to form a window for etching the silicon substrate;

[0038] 4) using a wet etching process to completely etch the silicon substrate between the front and back patterns to form an etching hole;

[0039] 5) A dry etching process is used to completely etch the reserved partial thickness of the thin film layer corresponding to the front pattern on the thin film layer, wherein the direction of the complete etching is from the front to the back of the silicon substrate, to obtain the hollow hard mask.

[0040] The method further includes: coating the hollow hard mask.

[0041] In the present application, the high precision means that the thin film layer of the hard mask prepared by the present application finally has a low thickness of 10nm~10μm (for example, 240nm, 150nm, 50nm), and the pore size of the front pattern can reach 8nm~50μm, and the pore spacing can reach a density of 10nm~100μm.

[0042] In this application, the large area refers to the hard mask prepared in this application having a surface area of ​​0.1 to 10 cm 2 The area can reach square centimeters.

[0043] In a specific embodiment of the present application, in step 1), the thickness of the silicon substrate can be 10 μm to 5000 μm, for example, it can be 10 μm, 20 μm, 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, 100 μm, 200 μm, 300 μm, 400 μm, 500 μm, 600 μm, 700 μm, 800 μm, 900 μm, 1000 μm, 2000 μm, 3000 μm, 4000 μm, 5000 μm, and the crystal orientation can be <100> type.

[0044] In a specific embodiment of the present application, in step 1), the silicon wafer is double-sided polished and cleaned.

[0045] There is no limitation on the double-sided polishing method, and the silicon wafer only needs to be double-sided polished. The double-sided polishing methods that can be used include but are not limited to chemical mechanical polishing (CMP) and simultaneous double-sided polishing technology (DSP).

[0046] The cleaning can be completed in a megasonic cleaning machine, and the specific steps may be: first, the silicon substrate is placed in an acetone solution for ultrasonic cleaning for 5 to 8 minutes (for example, 5 minutes, 6 minutes, 7 minutes, 8 minutes), then placed in an isopropanol solution for ultrasonic cleaning for 5 to 8 minutes (for example, 5 minutes, 6 minutes, 7 minutes, 8 minutes), and finally placed in deionized water for ultrasonic cleaning for 3 to 5 minutes (for example, 3 minutes, 4 minutes, 5 minutes). After taking out, the surface of the substrate is blown dry with a nitrogen gun.

[0047] In a specific embodiment of the present application, step 1) may also include removing residual moisture and / or organic matter on the surface of the silicon wafer before depositing a thin film layer and a hard mask layer.

[0048] In a specific embodiment of the present application, the removal of residual moisture and / or organic matter on the surface of the silicon wafer can be carried out by baking the substrate at 150-180°C for more than 8 minutes. For example, the temperature can be 150°C, 160°C, 170°C, 180°C, and the time can be 8 minutes, 9 minutes, 10 minutes, 11 minutes, 12 minutes and above.

[0049] In a specific embodiment of the present application, in step 1), the thin film layer refers to a thin film formed on the surface of a silicon wafer, which carries a circuit pattern transferred by a photolithography process. The front thin film layer is etched to form a hollow pattern layer. The material of the thin film layer can be selected from silicon nitride, silicon oxide, aluminum oxide, silicon carbide, or a composite multilayer material thereof.

[0050] The hard mask layer is also used to carry the pattern transferred by the photolithography process and as a mask when etching the silicon substrate. The material of the hard mask layer can be selected from silicon nitride, silicon oxide, aluminum oxide, silicon carbide, or a composite multilayer material thereof.

[0051] In a specific embodiment of the present application, in step 1), the deposition of a thin film layer and a hard mask layer adopts a chemical vapor deposition process.

[0052] In one embodiment of the present application, the chemical vapor deposition process is a low-pressure chemical vapor deposition process. Specifically, the deposition rate in the low-pressure chemical vapor deposition process can be 5 to 20 nm / min (for example, 5 nm / min, 10 nm / min, 15 nm / min, 20 nm / min), and the reaction precursors are dichlorosilane (SiH2Cl2) and ammonia (NH3).

[0053] In a specific embodiment of the present application, in step 1), the thickness of the deposited thin film layer and the hard mask layer is 10nm to 10μm, for example, 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 200nm, 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, 1μm, 2μm, 3μm, 4μm, 5μm, 6μm, 7μm, 8μm, 9μm, 10μm, and the thickness of the deposited thin film layer is reduced after two etchings to obtain the final thin film layer thickness. The thickness of the thin film layer of the present application is relatively thin. Under the condition of the thin film layer thickness, the integrity of the thin film layer can be maintained during etching by the method of the present application.

[0054] In a specific embodiment of the present application, in step 1), the annealing is performed in a rapid annealing furnace (RTA), the annealing temperature may be 800°C to 1100°C, for example, 800°C, 850°C, 900°C, 950°C, 1000°C, 1050°C, 1100°C, the annealing time may be 0.5 to 5 min, for example, 0.5 min, 1 min, 1.5 min, 2 min, 2.5 min, 3 min, 3.5 min, 4 min, 4.5 min, 5 min, and an inert gas such as N2 or Ar is introduced during the annealing. In the present application, the residual stress can be effectively eliminated to improve the mechanical stability through annealing and annealing conditions, and the silicon nitride with an average stress as low as 19.28 Mpa is obtained, which can effectively prevent the stress concentration points at the graphics from breaking and cracking during the etching process.

[0055] In a specific embodiment of the present application, step 1) may also include cleaning and drying the substrate after the above deposition and annealing.

[0056] In a specific embodiment of the present application, in step 2), before using photolithography technology, it also includes removing organic matter on the surface of the thin film layer and / or improving the hydrophobicity of the surface of the thin film layer. The methods used include but are not limited to organic solvent cleaning (such as acetone, isopropanol or ethanol), ultrasonic cleaning, plasma cleaning, megasonic cleaning, and ozone water cleaning.

[0057] In a specific embodiment of the present application, oxygen plasma is used to bombard the thin film layer to remove organic matter on the surface of the thin film layer; the bombardment time can be 0.5min to 1.5min, for example, 0.5min, 0.7min, 0.9min, 1.1min, 1.3min, 1.5min.

[0058] In a specific embodiment of the present application, in step 2), the front pattern is an array periodic pattern or other arbitrary pattern.

[0059] In a specific embodiment of the present application, the pore size of the array periodic pattern can be 8nm to 50μm, for example, it can be 8nm, 9nm, 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 200nm, 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, 1μm, 2μm, 3μm, 4μm, 5μm, 6μm, 7μm, 8μm, 9μm, 10μm, 20μm, 30μm, 40μm, 50μm.

[0060] In a specific embodiment of the present application, the hole spacing of the array periodic pattern is 10nm to 100μm, for example, it can be 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 200nm, 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, 1μm, 2μm, 3μm, 4μm, 5μm, 6μm, 7μm, 8μm, 9μm, 10μm, 20μm, 30μm, 40μm, 50μm, 60μm, 70μm, 80μm, 90μm, 100μm.

[0061] In a specific embodiment of the present application, the hole spacing of the array periodic pattern is 1.1 to 10 times the hole diameter, for example, it can be 1.1 times, 2 times, 3 times, 4 times, 5 times, 6 times, 7 times, 8 times, 9 times, or 10 times.

[0062] In a specific embodiment of the present application, the array periodic pattern of the present application has a high density. Through the method of the present application, the integrity of the thin film layer can still be maintained under the condition of the array pattern.

[0063] In a specific embodiment of the present application, in step 2), the photolithography technology is selected from any one or more of contact lithography, deep ultraviolet lithography, extreme ultraviolet lithography, maskless laser direct writing, stepper lithography, electron beam lithography, and nanoimprinting, and the front pattern is transferred to the front photoresist through the photolithography technology.

[0064] In certain embodiments of the present application, in step 2), the photolithography technology may be contact photolithography or maskless laser direct writing.

[0065] In a specific embodiment of the present application, the photoresist used in the photolithography technology in step 2) is selected from any one or more of AZ5214, S1818, S1805, SPR3612, SPR220-3, SPR220-7, UV-135G, PMMA, SU-8, and the steps and parameters of the photolithography process are adjusted according to different photoresists.

[0066] In certain embodiments of the present application, in step 2), in the photolithography technology, the glue coating can be completed by single-step spin coating of a glue spreader, and the glue coating thickness can be 50nm to 10μm, for example, it can be 50nm, 100nm, 200nm, 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, 1μm, 2μm, 3μm, 4μm, 5μm, 6μm, 7μm, 8μm, 9μm, 10μm, which can improve the resolution of the photolithography process and improve the clarity of the pattern.

[0067] The soft baking, exposure, post-baking, development, and film hardening processes are conventional processes in the art, and conventional methods in the art can be used and adjusted according to actual conditions.

[0068] In a specific embodiment of the present application, the soft baking time may be 45 to 60 seconds, for example, 45 seconds, 50 seconds, 55 seconds, or 60 seconds.

[0069] In certain embodiments of the present application, the exposure process can be completed in a maskless lithography apparatus, a stepper lithography apparatus, an electron beam lithography apparatus, or a contact lithography apparatus, and the steps and parameters can be adjusted according to the selection of the exposure process.

[0070] The development process may use AZ MIF300 developer or an alkaline developer containing 2.38% TMAH (tetramethylammonium hydroxide), and the development time may be 30 to 60 seconds, for example, 30s, 35s, 40s, 45s, 50s, 55s, or 60s.

[0071] In a specific embodiment of the present application, in step 2), before using the etching technology, it also includes removing the residual photoresist from the photolithography process, and the methods used include but are not limited to plasma stripping, chemical dissolution (including acetone, toluene, propanol), thermal decomposition, mechanical removal, use of a special photoresist remover (such as ACT CMI series), ultrasonic or megasonic cleaning, strong oxidizing acid cleaning (such as aqua regia, piranha, sulfuric acid or nitric acid).

[0072] In a specific embodiment of the present application, oxygen plasma is used to bombard the photoresist surface to remove residual photoresist from the photolithography process, and the bombardment time can be 1 to 1.5 minutes, for example, 1 minute, 1.1 minutes, 1.2 minutes, 1.3 minutes, 1.4 minutes, and 1.5 minutes.

[0073] In a specific embodiment of the present application, in step 2), the dry etching technique is selected from any one or more of reactive ion etching, inductively coupled plasma etching, and ion beam etching. The front pattern on the photoresist is transferred to the thin film layer by dry etching.

[0074] In one embodiment of the present application, in step 2), the dry etching technology uses reactive ion etching.

[0075] In one embodiment of the present application, in step 2), in reactive ion etching, the precursors required for etching are oxygen and trifluoromethane, the oxygen flow rate is 5.0-10.0 sccm, for example, 5.0 sccm, 6.0 sccm, 7.0 sccm, 8.0 sccm, 9.0 sccm, 10.0 sccm, the trifluoromethane flow rate is 50-60 sccm, for example, 50 sccm, 55 sccm, 60 sccm, the reaction chamber temperature is 20-30°C, for example, 20°C, 25°C, 30°C. The etching rate of the present application is 34.5 nm / min. The present application selects the optimal etching conditions through screening, and under the above etching conditions, it can adapt to the finer pattern size of the present application.

[0076] In a specific embodiment of the present application, in step 2), reserving a partial thickness of the thin film layer means that when etching the thin film layer, not completely etching is performed to etch through the thin film layer, but only a partial thickness of the thin film layer is etched, and a partial thickness of the thin film layer is retained to serve as a barrier and support structure for the subsequent wet etching of the silicon substrate, thereby avoiding the thin film layer from breaking during wet etching, which can improve the yield and reduce the pattern size.

[0077] According to the research of the present application, when a part of the thickness of the thin film layer is reserved in the first etching step, it is more conducive to maintaining the integrity of the thin film layer during wet etching.

[0078] In a specific embodiment of the present application, when a thin film layer is etched using a dry etching process, the reserved partial thickness of the thin film layer refers to a thin film layer whose thickness is less than the etched film layer depth. For example, the reserved film layer thickness is the reserved thickness after the first etching of the front silicon nitride in step 4 of embodiment 1 of the present application, and the etched film layer depth is the depth etched at the front silicon nitride pattern in step 4 of embodiment 1 of the present application.

[0079] In a preferred embodiment of the present application, the thickness of the reserved thin film layer is 10-90% of the depth of the etched thin film layer.

[0080] In a specific embodiment of the present application, in step 3), the back surface pattern is a window pattern.

[0081] In a specific embodiment of the present application, in step 3), the back pattern does not include a cross in the middle of the layout junction groove. The present application innovatively designs the layout of the back pattern, removes the cross in the middle of the layout junction groove of the back pattern, and designs a reasonable groove width of 200 to 300 μm. After screening and selection, it was found that if a groove width of 50 to 150 μm is used, the silicon etching depth will be too shallow and it will be difficult to scribing. This ensures that wet etching will not penetrate the silicon substrate, and the cross intersections are designed to be non-intersecting, which is beneficial to the subsequent scribing process operations.

[0082] In a specific implementation of the present application, in step 3), before using the photolithography technology, it also includes removing organic matter on the surface of the hard mask layer, which can be consistent with the above step 2) and will not be repeated here.

[0083] In the specific implementation of the present application, in step 3), the photolithography technique can be consistent with the photolithography process in step 2), which will not be repeated here. The photolithography process also includes the need to align with the cross mark of the front pattern. The back pattern is transferred to the back photoresist by photolithography.

[0084] In a specific embodiment of the present application, in step 3), before using the dry etching technology, the residual photoresist in the photolithography process is removed, which can be consistent with the above step 2).

[0085] In the specific implementation of the present application, in step 3), the dry etching technology can be consistent with the dry etching technology in step 2), or a conventional dry etching technology can be used, and only the back pattern needs to be transferred to the hard mask layer, which will not be described in detail here, but the etching of the back hard mask layer is complete etching. The back pattern on the photoresist is transferred to the back hard mask layer by dry etching technology.

[0086] The complete etching refers to etching through the material, so that the material forms a hollow etching hole.

[0087] In a specific embodiment of the present application, in step 4), a wet etching process is used to completely etch the silicon substrate between the front pattern and the back pattern to form an etching hole. For example, when the hollow area of ​​the front pattern is smaller than the hollow area of ​​the back pattern, the etching hole formed by completely etching the silicon substrate is a trapezoid.

[0088] In a specific embodiment of the present application, in step 4), the solution used for wet etching is selected from any one or more of hydrofluoric acid, a mixture of nitric acid and hydrofluoric acid, potassium hydroxide, and ammonium tetrafluoride; preferably, the solution used for wet etching is potassium hydroxide.

[0089] In one embodiment of the present application, in step 4), the etching holes are formed by continuous immersion in a potassium hydroxide solution for 6 to 8 hours (for example, 6 hours, 7 hours, or 8 hours).

[0090] In a specific implementation manner of the present application, step 4) also includes smoothing the sidewalls of the etched silicon substrate.

[0091] In one embodiment of the present application, in step 4), the smoothing treatment is to etch the silicon substrate and then immerse it in a piranha solution.

[0092] In a specific embodiment of the present application, in step 5), an etching technique is used to completely etch the area where the front pattern of the thin film layer is located, and the direction of the complete etching is from the front to the back of the silicon substrate. This is a secondary etching of the thin film layer to completely etch the thin film layer, thereby obtaining the hollow hard mask.

[0093] In the present application, the method further includes: coating the hollow hard mask.

[0094] In a specific embodiment of the present application, the method for coating the hollow hard mask is to deposit metal on the surface of the hard mask layer and the inner wall of the etched hole to obtain a metal layer; and deposit film layer materials on the surface of the thin film layer and the metal layer respectively.

[0095] In a specific embodiment of the present application, the metal deposition is performed by physical vapor deposition, for example, conventional physical vapor deposition can be used, and its parameters can be adjusted accordingly according to the existing technology or actual conditions. The metal to be deposited can be chromium or gold or a combination of chromium and gold, and the metal layer deposition is to first deposit a layer of 5 to 10 nm of chromium (for example, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm), and then deposit a layer of 25 to 30 nm of gold (for example, 25 nm, 26 nm, 27 nm, 28 nm, 29 nm, 30 nm).

[0096] In a specific embodiment of the present application, the chromium deposition rate is 0.18-0.30 nm / s, for example, it can be 0.18 nm / s, 0.20 nm / s, 0.22 nm / s, 0.24 nm / s, 0.26 nm / s, 0.28 nm / s, 0.30 nm / s; the gold deposition rate is 0.28-0.40 nm / s, for example, it can be 0.28 nm / s, 0.30 nm / s, 0.32 nm / s, 0.34 nm / s, 0.36 nm / s, 0.38 nm / s, 0.40 nm / s.

[0097] In a specific embodiment of the present application, the film layer material is selected from silicon nitride, silicon oxide, aluminum oxide, silicon carbide, or a composite multilayer material thereof.

[0098] In a specific embodiment of the present application, the film material is deposited by atomic layer deposition (ALD). Specifically, the deposition rate in the atomic layer deposition is 0.22-0.35 angstroms / cycle, for example, 0.22, 0.23, 0.24, 0.25, 0.26, 0.27, 0.28, 0.29, 0.30, 0.31, 0.32, 0.33, 0.34, 0.35 angstroms / cycle, and the deposition temperature is 300-350°C, for example, 300°C, 310°C, 320°C, 330°C, 340°C, 350°C.

[0099] In a specific embodiment of the present application, after step 7), a dicing process may be performed on the substrate obtained in 7) to obtain a plurality of independent samples.

[0100] The present application also provides a hard mask, which is prepared by the above-mentioned preparation method. The thin film layer of the hard mask finally has a low thickness of 10nm to 10μm, and the pore size of the front pattern can reach 8nm to 50μm, the pore spacing can reach a density of 10nm to 100μm, and has a density of 0.1 to 10cm 2 The area can reach the square centimeter level and can maintain integrity without deformation, collapse or breakage.

[0101] The present application is further described below by way of examples, but the scope of the present application is not limited thereby. Unless otherwise stated, the experimental methods, detection methods, and preparation methods disclosed in the present application all adopt conventional techniques in the technical field and related fields. These techniques have been fully described in the existing literature. Unless otherwise specified, the instruments, materials, and reagents used in the examples are all obtained by conventional means.

[0102] Example 1

[0103] This embodiment is a preferred embodiment. The main difference between this embodiment and comparative example 1 is the front etching in step 4, wherein the front etching adopts a multi-step dry etching process.

[0104] Step 1: Select a thickness of 500 μm and a crystal orientation of <100> A double-sided polished silicon wafer of the type is used as the silicon substrate and cleaned.

[0105] The cleaning process needs to be completed in a megasonic cleaning machine. First, the substrate is placed in an acetone solution for ultrasonic cleaning for 5 minutes, then placed in an isopropanol solution for ultrasonic cleaning for 5 minutes, and finally placed in deionized water for ultrasonic cleaning for 3 minutes. After taking it out, use a nitrogen gun to blow and dry the surface of the substrate.

[0106] Step 2: Before coating, the substrate needs to be baked at 150°C for more than 8 minutes to completely remove residual moisture and organic matter on the surface. Silicon nitride is deposited on both the front and back sides using a low-pressure chemical vapor deposition process (LPCVD) with a deposition rate of 5nm / min. The reaction precursors are dichlorosilane (SiH2Cl2) and ammonia (NH3). 500nm of low-stress, high-density silicon nitride is deposited on the front and back sides respectively and annealed. Inert gas is filled in the annealing process, the temperature is set at 800°C, the annealing time is 5min, and the silicon wafer is cleaned, such as Figure 3 (a) Schematic diagram of double-sided deposition of silicon nitride.

[0107] Step 3: Before the coating process, the silicon nitride surface needs to be bombarded with oxygen plasma for 1.5 minutes to remove organic matter and change the surface hydrophobicity, which is conducive to the complete coating of photoresist. Then, photoresist is coated on the front of the substrate, and the selected photoresist model is S1805. The coating process is completed by single-step spin coating of a coating machine, and the coating thickness is 400±20nm.

[0108] The soft baking, exposure, post-baking, development, and hardening processes are completed in sequence, wherein the baking time is 60 seconds. It should be emphasized that, unlike the contact lithography in Comparative Example 1, this lithography process does not require the use of a mask plate, the exposure process is completed in a maskless lithography instrument, and the laser light source is 405nm deep ultraviolet light. The development process uses AZ MIF300 developer, and the development time is 60 seconds.

[0109] Front pattern Figure 4 As shown in a, the pore diameter of the front pattern is 1 μm, the pore spacing is 2 μm, and the pore spacing of the array periodic pattern is twice the pore diameter.

[0110] Step 4: Before etching, oxygen plasma needs to be used to bombard the photoresist surface for 1 to 1.5 minutes to remove the residual photoresist at the pattern. Then, the photolithography pattern is transferred to the front silicon nitride by reactive ion etching (RIE). Figure 4As shown in a), the pattern cannot be completely etched, and a 100nm thick silicon nitride needs to be retained as a barrier and support structure for subsequent wet etching of the silicon substrate. The precursors required for etching are oxygen and trifluoromethane (O2, CHF3), with flow rates of 10sccm and 60sccm respectively. The reaction chamber temperature is 30°C, and the etching rate is 38.6nm / min. Finally, SiF4, N2, NO2 and other gas products are produced and discharged. Figure 3 (b) Schematic diagram of the front silicon nitride layer pattern transfer.

[0111] Step 5: Coat photoresist on the back of the substrate. The photoresist model selected is AZ5214, and soft baking, exposure, and development processes are completed in sequence. The exposure process is completed in a contact photolithography machine and needs to be aligned with the cross mark of the front pattern. The laser light source is 405nm deep ultraviolet light, the contact method between the substrate and the mask is non-vacuumed hard contact, and the exposure time is 4.3 seconds. Except for the above-mentioned exposure process, the remaining process parameters are consistent with those in step 3 of this embodiment.

[0112] Step 6: Completely etch the silicon nitride at the back pattern (the back pattern is as follows Figure 4 As shown in FIG. 2 , the groove width of the back pattern is 200 μm, and there is no cross in the middle of the patterned groove. The other process parameters are consistent with those in step 4 of this embodiment. Figure 3 (c) Schematic diagram of the back side silicon nitride layer pattern transfer.

[0113] Step 7: Wet-etch the silicon substrate with potassium hydroxide (KOH) solution to obtain the hollow structure and electrode holes. Soak in potassium hydroxide solution for 6 hours. After etching, the substrate needs to be immersed in piranha solution to remove impurities on the silicon sidewalls, then rinse with deionized water and blow dry with a nitrogen gun. Figure 3 (d) Schematic diagram of wet etching of silicon substrate.

[0114] Step 8: Reactive ion etching (RIE) is used with the same parameters as in step 4 to completely etch the silicon nitride retained in step 4. Finally, after two etchings, the thickness of the silicon nitride on the front side is 240 nm. Figure 3 (e) Schematic diagram of secondary etching of the front silicon nitride thin layer.

[0115] Step 9: Complete the metal electrode coating by physical vapor deposition (PVD), specifically, complete the metal electrode coating by physical vapor deposition (PVD), wherein the chromium deposition rate is 0.18nm / s, and the gold deposition rate is 0.28nm / s, first deposit a 5nm layer of chromium to improve metal adhesion, and then deposit a 25nm layer of gold as an electrode. Figure 3 (f) as shown.

[0116] Step 10: Deposit a layer of silicon nitride on the front side by atomic layer deposition (ALD) to thicken the hollow hard mask, with a deposition rate of 0.3 angstroms / cycle and a deposition temperature of 300°C. Figure 3 (f) as shown.

[0117] Step 11: Deposit a layer of silicon nitride on the back side by atomic layer deposition (ALD) to cover the metal electrode. The coating parameters are the same as those of step 10 in this embodiment. Figure 3 (f) Schematic diagram of electrode gold plating and double-sided silicon nitride coating thickening.

[0118] The hollow pattern layer prepared in this embodiment is as follows Figure 6 As shown, the pore size in the micropore array is 1 μm and the pore spacing is 2 μm ( Figure 6 a), the array structure of the pattern layer is intact and has a good yield ( Figure 6 bc), the angle and smooth morphology of the silicon sidewall after wet etching. The angle of the silicon sidewall after wet etching is about 56°. The sidewall surface has no particles and cracks and has a smooth morphology, which is conducive to improving the coverage of the subsequent thin film material on the sidewall surface; interconnection conduction after depositing metal electrodes ( Figure 6 de).

[0119] Example 2

[0120] Step 1: Select a thickness of 300 μm and a crystal orientation of <100> A double-sided polished silicon wafer of the type is used as the silicon substrate and cleaned.

[0121] The cleaning process needs to be completed in a megasonic cleaning machine. First, the substrate is placed in an acetone solution for ultrasonic cleaning for 5 minutes, then placed in an isopropanol solution for ultrasonic cleaning for 5 minutes, and finally placed in deionized water for ultrasonic cleaning for 3 minutes. After taking it out, use a nitrogen gun to blow and dry the surface of the substrate.

[0122] Step 2: Before coating, the substrate needs to be baked at 150°C for more than 8 minutes to completely remove residual moisture and organic matter on the surface. Silicon nitride is deposited on both the front and back sides using a low-pressure chemical vapor deposition process (LPCVD) with a deposition rate of 5nm / min. The reaction precursors are dichlorosilane (SiH2Cl2) and ammonia (NH3). 300nm of low-stress, high-density silicon nitride is deposited on the front and back sides respectively and annealed. Inert gas is filled in the annealing process, the temperature is set at 900°C, the annealing time is 3min, and the silicon wafer is cleaned, such as Figure 3 (a) Schematic diagram of double-sided deposition of silicon nitride.

[0123] Step 3: Before the coating process, the silicon nitride surface needs to be bombarded with oxygen plasma for 1.5 minutes to remove organic matter and change the surface hydrophobicity, which is conducive to the complete coating of photoresist. Then, photoresist is coated on the front of the substrate. The selected photoresist model is UV-135G. The coating process is completed by spin coating with an automatic coating developer (Track), and the coating thickness is 480±20nm.

[0124] The soft baking, exposure, post-baking, development and hardening processes are completed in sequence, and the baking time is 60 seconds. The exposure process is completed in a stepper lithography machine, and the laser light source is 193nm deep ultraviolet light. The development process uses AZ MIF300 developer, and the development time is 60 seconds.

[0125] The pore diameter of the front pattern is 300 nm, the pore spacing is 330 nm, and the pore spacing of the array periodic pattern is 1.1 times the pore diameter.

[0126] Step 4: Before etching, oxygen plasma needs to be used to bombard the photoresist surface for 1 to 1.5 minutes to remove the residual photoresist at the pattern. Then, the photolithography pattern is transferred to the front silicon nitride by reactive ion etching (RIE). Figure 4 As shown in a), the pattern cannot be completely etched, and a 140nm thick silicon nitride needs to be retained as a barrier and support structure for subsequent wet etching of the silicon substrate. The precursors required for etching are oxygen and trifluoromethane (O2, CHF3), with flow rates of 7sccm and 55sccm respectively. The reaction chamber temperature is 20°C, and the etching rate is 36.5nm / min. Finally, SiF4, N2, NO2 and other gas products are produced and discharged. Figure 3 (b) Schematic diagram of the front silicon nitride layer pattern transfer.

[0127] Step 5: Coat photoresist on the back of the substrate. The photoresist model selected is AZ5214, and soft baking, exposure, and development processes are completed in sequence. The exposure process is completed in a contact photolithography machine and needs to be aligned with the cross mark of the front pattern. The laser light source is 405nm deep ultraviolet light, the contact method between the substrate and the mask is non-vacuumed hard contact, and the exposure time is 4.3 seconds. Except for the above-mentioned exposure process, the remaining process parameters are consistent with those in step 3 of this embodiment.

[0128] Step 6: Completely etch the silicon nitride at the back pattern (the groove width of the back pattern is 200 μm, and there is no cross in the middle of the patterned groove). The remaining process parameters are consistent with those in step 4 of this embodiment, such as Figure 3 (c) Schematic diagram of the back side silicon nitride layer pattern transfer.

[0129] Step 7: Wet-etch the silicon substrate with potassium hydroxide (KOH) solution to obtain the hollow structure and electrode holes. Soak in potassium hydroxide solution for 6 hours. After etching, the substrate needs to be immersed in piranha solution to remove impurities on the silicon sidewalls, then rinse with deionized water and blow dry with a nitrogen gun. Figure 3 (d) Schematic diagram of wet etching of silicon substrate.

[0130] Step 8: Reactive ion etching (RIE) is used with the same parameters as in step 4 to completely etch the silicon nitride retained in step 4. Finally, after two etchings, the thickness of the silicon nitride on the front side is 150 nm. Figure 3 (e) Schematic diagram of secondary etching of the front silicon nitride thin layer.

[0131] Step 9: Complete the metal electrode coating by physical vapor deposition (PVD), specifically, complete the metal electrode coating by physical vapor deposition (PVD), wherein the chromium deposition rate is 0.18nm / s, and the gold deposition rate is 0.28nm / s, first deposit a 5nm layer of chromium to improve metal adhesion, and then deposit a 25nm layer of gold as an electrode. Figure 3 (f) as shown.

[0132] Step 10: A layer of silicon nitride is deposited on the front side by atomic layer deposition (ALD) to thicken the hollow hard mask, with a deposition rate of 0.35 angstroms / cycle and a deposition temperature of 350°C. Figure 3 (f) as shown.

[0133] Step 11: Deposit a layer of silicon nitride on the back side by atomic layer deposition (ALD) to cover the metal electrode. The coating parameters are the same as those of step 10 in this embodiment. Figure 3 (f) Schematic diagram of electrode gold plating and double-sided silicon nitride coating thickening.

[0134] The array structure of the hard mask pattern layer prepared in this embodiment is intact, has a good yield, has no particles or cracks on the side wall surface, and has a smooth morphology.

[0135] Example 3

[0136] Step 1: Select a thickness of 200 μm and a crystal orientation of <100> A double-sided polished silicon wafer of the type is used as the silicon substrate and cleaned.

[0137] The cleaning process needs to be completed in a megasonic cleaning machine. First, the substrate is placed in an acetone solution for ultrasonic cleaning for 5 minutes, then placed in an isopropanol solution for ultrasonic cleaning for 5 minutes, and finally placed in deionized water for ultrasonic cleaning for 3 minutes. After taking it out, use a nitrogen gun to blow and dry the surface of the substrate.

[0138] Step 2: Before coating, the substrate needs to be baked at 150°C for more than 8 minutes to completely remove residual moisture and organic matter on the surface. Silicon nitride is deposited on both the front and back sides using a low-pressure chemical vapor deposition process (LPCVD) with a deposition rate of 5nm / min. The reaction precursors are dichlorosilane (SiH2Cl2) and ammonia (NH3). 100nm of low-stress, high-density silicon nitride is deposited on the front and back sides respectively and annealed. Inert gas is filled in the annealing process, the temperature is set at 1100°C, the annealing time is 0.5min, and the silicon wafer is cleaned, such as Figure 3 (a) Schematic diagram of double-sided deposition of silicon nitride.

[0139] Step 3: Before the coating process, the silicon nitride surface needs to be bombarded with oxygen plasma for 1.5 minutes to remove organic matter and change the surface hydrophobicity, which is conducive to the complete coating of the photoresist. Then, the photoresist is coated on the front of the substrate, and the selected photoresist model is PMMA. The coating process is completed by single-step spin coating of the coating machine, and the coating thickness is 50±5nm.

[0140] The soft baking, exposure, post-baking, development and hardening processes are completed in sequence, wherein the baking time is 60 seconds. The exposure process is completed in an electron beam exposure machine, and the exposure source is an electron beam. The development process uses an alkaline developer containing 2.38% TMAH (tetramethylammonium hydroxide), and the development time is 30 seconds.

[0141] The pore diameter of the front pattern is 8 nm, the pore spacing is 10 nm, and the pore spacing of the array periodic pattern is 1.25 times the pore diameter.

[0142] Step 4: Before etching, oxygen plasma needs to be used to bombard the photoresist surface for 1 to 1.5 minutes to remove the residual photoresist at the pattern. Then, the photolithography pattern is transferred to the front silicon nitride by reactive ion etching (RIE). Figure 4 As shown in a), the pattern cannot be completely etched, and a 45nm thick silicon nitride needs to be retained as a barrier and support structure for subsequent wet etching of the silicon substrate. The precursors required for etching are oxygen and trifluoromethane (O2, CHF3), with flow rates of 5sccm and 50sccm respectively. The reaction chamber temperature is 20°C, and the etching rate is 34.5nm / min. Finally, SiF4, N2, NO2 and other gas products are produced and discharged. Figure 3 (b) Schematic diagram of the front silicon nitride layer pattern transfer.

[0143] Step 5: Coat photoresist on the back of the substrate. The photoresist model selected is AZ5214, and soft baking, exposure, and development processes are completed in sequence. The exposure process is completed in a contact photolithography machine and needs to be aligned with the cross mark of the front pattern. The laser light source is 405nm deep ultraviolet light, the contact method between the substrate and the mask is non-vacuumed hard contact, and the exposure time is 4.3 seconds. Except for the above-mentioned exposure process, the remaining process parameters are consistent with those in step 3 of this embodiment.

[0144] Step 6: Completely etch the silicon nitride at the back pattern (the groove width of the back pattern is 200 μm, and there is no cross in the middle of the patterned groove). The remaining process parameters are consistent with those in step 4 of this embodiment, such as Figure 3 (c) Schematic diagram of the back side silicon nitride layer pattern transfer.

[0145] Step 7: Wet-etch the silicon substrate with potassium hydroxide (KOH) solution to obtain the hollow structure and electrode holes. Soak in potassium hydroxide solution for 6 hours. After etching, the substrate needs to be immersed in piranha solution to remove impurities on the silicon sidewalls, then rinse with deionized water and blow dry with a nitrogen gun. Figure 3 (d) Schematic diagram of wet etching of silicon substrate.

[0146] Step 8: Reactive ion etching (RIE) is used with the same parameters as in step 4 to completely etch the silicon nitride retained in step 4. Finally, after two etchings, the thickness of the silicon nitride on the front side is 50 nm. Figure 3 (e) Schematic diagram of secondary etching of the front silicon nitride thin layer.

[0147] Step 9: Complete the metal electrode coating by physical vapor deposition (PVD), specifically, complete the metal electrode coating by physical vapor deposition (PVD), wherein the chromium deposition rate is 0.18nm / s, and the gold deposition rate is 0.28nm / s, first deposit a 5nm layer of chromium to improve metal adhesion, and then deposit a 25nm layer of gold as an electrode. Figure 3 (f) as shown.

[0148] Step 10: A layer of silicon nitride is deposited on the front side by atomic layer deposition (ALD) to thicken the hollow hard mask, with a deposition rate of 0.22 angstroms / cycle and a deposition temperature of 300°C. Figure 3 (f) as shown.

[0149] Step 11: Deposit a layer of silicon nitride on the back side by atomic layer deposition (ALD) to cover the metal electrode. The coating parameters are the same as those of step 10 in this embodiment. Figure 3 (f) shows the schematic diagram of electrode gold plating and double-sided silicon nitride coating thickening, thereby obtaining a hard mask with a complete array structure.

[0150] Comparative Example 1

[0151] This comparative example adopts a method of etching the front silicon nitride layer in one step.

[0152] Step 1: Select a thickness of 500 μm and a crystal orientation of <100> A double-sided polished silicon wafer of the type is used as the silicon substrate and cleaned.

[0153] The cleaning process needs to be completed in a megasonic cleaning machine. First, the substrate is placed in an acetone solution for ultrasonic cleaning for 5 minutes, then placed in an isopropanol solution for ultrasonic cleaning for 5 minutes, and finally placed in deionized water for ultrasonic cleaning for 3 minutes. After taking it out, use a nitrogen gun to blow and dry the surface of the substrate.

[0154] Step 2: Before coating, the substrate needs to be baked at 150°C for more than 8 minutes to completely remove residual moisture and organic matter on the surface. Then, silicon nitride is deposited on the front and back sides of the silicon substrate using a low-pressure chemical vapor deposition process (LPCVD) double-sided coating process. The deposition rate is 5nm / min. The reaction precursors are dichlorosilane (SiH2Cl2) and ammonia (NH3). 500nm of low-stress, high-density silicon nitride is deposited as a thin film layer and a hard mask layer, respectively. Then the substrate is placed in a rapid annealing furnace (RTA) to complete the annealing process. Inert gas is filled in the annealing process, the temperature is set at 800-1100°C, the annealing time is 30s, and the silicon wafer is cleaned, such as Figure 2 (a) Schematic diagram of double-sided deposition of silicon nitride.

[0155] Step 3: Before the coating process, the silicon nitride surface needs to be bombarded with oxygen plasma for 1.5 minutes to remove organic matter and change the surface hydrophobicity, which is conducive to the complete coating of photoresist. Then, photoresist is coated on the front of the substrate, and the selected photoresist model is AZ5214. The coating process is completed by single-step spin coating of the coating machine, and the coating thickness is 1.3±0.05μm.

[0156] The soft baking, exposure and development processes are completed in sequence. The baking time of the soft baking process is 60 seconds. The exposure process is completed in a contact lithography machine. The pattern of the mask needs to include 4 cross marks for subsequent back alignment. The laser light source is 405nm deep ultraviolet light. The contact method between the substrate and the mask is vacuum hard contact. The development process uses AZMIF300 developer, and the development time is 60 seconds.

[0157] The front pattern is the same as that in Example 1.

[0158] Step 4: Before etching, oxygen plasma is used to bombard the photoresist surface for 1 to 1.5 minutes to remove the residual photoresist at the pattern. Then, the photolithography pattern is transferred to the silicon nitride on the front side by reactive ion etching (RIE). The precursors required for etching are oxygen and trifluoromethane (O2, CHF3), with flow rates of 5.0 sccm and 50 sccm respectively. The temperature of the reaction chamber is 20°C, and the etching rate is 46.7nm / min. Finally, SiF4, N2, NO2 and other gas products are produced by etching and discharged. Figure 2 (b) Schematic diagram of the front silicon nitride layer pattern transfer.

[0159] Step 5: Coat photoresist on the back of the substrate. The selected photoresist model is AZ5214, and complete the soft baking, exposure, and development processes in sequence. The exposure process is completed in a contact photolithography machine and needs to be aligned with the cross mark of the front pattern. The laser light source is 405nm deep ultraviolet light, and the contact method between the substrate and the mask is non-vacuum hard contact. The exposure time is 4.3 seconds. Except for the above exposure process, the other process parameters are the same as those in step 3.

[0160] Step 6: Completely etch the silicon nitride at the back pattern (the back pattern is as follows Figure 4 As shown in step b, the groove width of the back pattern is 200 μm, and the other process parameters are consistent with those in step 4. Figure 2 (c) Schematic diagram of the back side silicon nitride layer pattern transfer.

[0161] Step 7: Wet-etch the silicon substrate with potassium hydroxide (KOH) solution to obtain the hollow structure and electrode holes. Specifically, soak it in potassium hydroxide solution for 6 hours. After etching, the substrate needs to be soaked in piranha solution to remove impurities on the silicon sidewalls, then rinsed with deionized water and blown dry with a nitrogen gun. Figure 2 (d) Schematic diagram of wet etching of silicon substrate.

[0162] Step 8: Complete the metal electrode coating by physical vapor deposition (PVD), where the chromium deposition rate is 0.18nm / s and the gold deposition rate is 0.28nm / s. First, a 5nm layer of chromium is deposited to improve the metal adhesion, and then a 25nm layer of gold is deposited as an electrode. Figure 2 (e) Schematic diagram of electrode gold plating.

[0163] Step 9: Deposit a layer of silicon nitride on the front side by chemical vapor deposition (PECVD) to thicken the hollow hard mask. The RF source uses a high-low frequency mixed method. The precursors required for deposition are monosilane, ammonia and nitrogen (SiH4, NH3, N2), and the deposition rate is 20nm / min. Figure 2 (f) Schematic diagram of double-sided silicon nitride coating thickening.

[0164] Step 10: Deposit a layer of silicon nitride on the back side by chemical vapor deposition (PECVD) to cover the metal electrode, with the same parameters as step 9, such as Figure 2 (f) Schematic diagram of double-sided silicon nitride coating thickening.

[0165] The hollow pattern layer prepared in this comparative example is as follows Figure 5 As shown, the pore size in the micropore array is 3 μm and the pore spacing is 6 μm ( Figure 5 a), some micro-hole array structures are broken, and the final pattern layer is often broken ( Figure 5 bc).

[0166] The above embodiments are merely illustrative of the principles and effects of the present application and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed in the present application shall still be covered by the claims of the present application.

Claims

1. A method for preparing a high-precision large-area ultra-thin hollow hard mask, comprising the following steps: 1) depositing a thin film layer on the front side of the silicon substrate, depositing a hard mask layer on the back side of the silicon substrate, and annealing; 2) using a photolithography process and a dry etching process to transfer the front pattern to the thin film layer; wherein, when etching the thin film layer using the dry etching process, a portion of the thickness of the thin film layer is reserved and the integrity of the thin film layer is maintained; 3) Using photolithography and dry etching processes to transfer the backside pattern to the hard mask layer to form a window for etching the silicon substrate; 4) using a wet etching process to completely etch the silicon substrate between the front pattern and the back pattern to form an etching hole; 5) A dry etching process is used to completely etch the reserved partial thickness of the thin film layer corresponding to the front pattern on the thin film layer, wherein the direction of the complete etching is from the front to the back of the silicon substrate, to form the hollow hard mask.

2. The preparation method according to claim 1, characterized in that: The method further includes: coating the hollow hard mask.

3. The preparation method according to claim 1, characterized in that: In step 1), any one or more of the following features are also included: 11) The materials of the thin film layer and the hard mask layer are selected from silicon nitride, silicon oxide, aluminum oxide, silicon carbide, or a composite multilayer material thereof; 12) The thickness of the silicon substrate is 10 μm to 5000 μm; 13) The thickness of the deposited thin film layer and hard mask layer is 10nm to 10μm; 14) Depositing a thin film layer and a hard mask layer by chemical vapor deposition; preferably, the chemical vapor deposition is low-pressure chemical vapor deposition; 15) The annealing temperature is 800° C. to 1100° C., the annealing time is 0.5 to 5 min, and an inert gas is filled during the annealing.

4. The preparation method according to claim 1, characterized in that: In step 2), any one or more of the following features are also included: 21) The front pattern is an array periodic pattern; preferably, the aperture of the array periodic pattern is 8nm to 50μm, the hole spacing of the array periodic pattern is 10nm to 100μm; the hole spacing of the array periodic pattern is 1.1 to 10 times the aperture; 22) When a thin film layer is etched using a dry etching process, the reserved portion of the thin film layer thickness means that the thickness of the reserved thin film layer is less than the depth of the etched thin film layer; preferably, the thickness of the reserved thin film layer is 10 to 90% of the depth of the etched thin film layer.

5. The preparation method according to claim 1, characterized in that: Step 3) further includes: the back pattern is a window pattern; preferably, the back pattern does not include a cross in the middle of the layout junction groove, and the groove width of the back pattern is 200 to 300 μm.

6. The preparation method according to claim 1, characterized in that: In step 4), any one or more of the following features are also included: 41) The solution used in the wet etching process is selected from any one or more of hydrofluoric acid, potassium hydroxide, ammonium tetrafluoride, nitric acid and a mixture of hydrofluoric acid; 42) also includes smoothing the sidewalls of the etched silicon substrate; preferably, the smoothing is performed by soaking the etched silicon substrate in a piranha solution.

7. The preparation method according to claim 2, characterized in that: The method for coating the hollow hard mask is to deposit metal on the surface of the hard mask layer and the inner wall of the etched hole to obtain a metal layer; and deposit film layer materials on the surfaces of the thin film layer and the metal layer respectively.

8. The preparation method according to claim 7, characterized in that: The method for coating the hollow hard mask has any one or more of the following features: 1) The metal deposition is performed by physical vapor deposition; 2) The film layer material is selected from silicon nitride, silicon oxide, aluminum oxide, silicon carbide, or a composite multilayer material thereof; 3) The film material is deposited by atomic layer deposition; preferably, the deposition rate in the atomic layer deposition is 0.22-0.35 angstroms / cycle, and the deposition temperature is 300-350°C.

9. The preparation method according to claim 1, characterized in that: The photolithography process is selected from any one or more of deep ultraviolet lithography, extreme ultraviolet lithography, maskless laser direct writing, stepper lithography, electron beam lithography, and nanoimprinting; and / or the dry etching process is selected from any one or more of reactive ion etching, inductively coupled plasma etching, and ion beam etching; Preferably, when the dry etching process is reactive ion etching, the precursors used include oxygen and trifluoromethane, the oxygen flow rate is 5.0-10.0 sccm, the trifluoromethane flow rate is 50-60 sccm, and the reaction chamber temperature is 20-30°C.

10. A hard mask prepared by the preparation method according to any one of claims 1 to 9.

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