Dual-mode imbalance calibration circuit applied to comparator of high-speed time domain interleaving ADC (Analog to Digital Converter)

Abstract

The invention discloses a dual-mode offset calibration circuit applied to a comparator of a high-speed time domain interleaving ADC (Analog to Digital Converter). The dual-mode offset calibration circuit comprises a calibration logic, n channels and a configurable resistor string, wherein the calibration logic comprises detection logic and compensation logic; each channel is respectively connected with the calibration logic and the configurable resistor string; any one of the n channels comprises a switch array, a latch array and a comparator. The noise influence in the comparator imbalance detection process is reduced through the detection logic provided by the invention; a calibration logic and a configurable resistor string are multiplexed by a plurality of channels, so that the power consumption and the area of the circuit are greatly reduced; the configurable resistor string correspondingly selects a coarse calibration mode or a fine calibration mode according to the obtained external signal MODESEL, the coarse calibration mode has a larger calibration range and a higher convergence speed compared with the fine calibration mode, and the fine calibration mode has higher calibration precision compared with the coarse calibration mode.

Description

Technical Field

[0001] The present invention belongs to the field of design of mixed-signal integrated circuits, and particularly relates to a dual-mode offset calibration circuit for a comparator applied to a high-speed time-interleaved ADC. Background Art

[0002] A time-interleaved ADC (TIADC) uses multiple sub-channel ADCs to sample and quantize the same input signal in parallel. Each sub-channel ADC separately completes the conversion from an analog signal to a digital signal and alternately outputs the results. This can enable the overall ADC to multiply the conversion rate while maintaining the conversion accuracy of a single channel. However, in our actual production applications, due to various factors such as the process during chip manufacturing, environmental conditions such as temperature and voltage during chip operation, and the incomplete symmetry and matching of each sub-channel in layout design. Each sub-channel ADC cannot be made completely the same and cannot reach exactly the same working state, which will cause a mismatch phenomenon in the time-interleaved ADC. There will be a certain offset in the comparator of a single-channel ADC, and the offset magnitudes of the comparators of each sub-channel in the time-interleaved ADC will not be exactly the same, which causes an offset mismatch phenomenon in the time-interleaved ADC.

[0003] The offset mismatch between channels affects the correctness of the data obtained by sampling and quantizing the time-interleaved ADC, will cause the time-domain waveform obtained by the system to be distorted, and will also generate harmonics and spurs in the output spectrum of the time-interleaved ADC, seriously deteriorating the dynamic performance indicators such as the signal-to-noise ratio and spurious-free dynamic range of the system. In the process of actually designing a time-interleaved ADC, if the comparator offset is not calibrated, the performance of the time-interleaved ADC will be greatly affected. Therefore, calibrating the comparator offset of each channel of the time-interleaved ADC and minimizing the offset mismatch of the time-interleaved ADC as much as possible is an important task.

[0004] In traditional time-interleaved ADC comparator offset calibration circuits, each channel's comparator often requires a separate calibration circuit. When the number of channels is larger, the power consumption and area of the calibration circuit will be larger. And the calibration circuit will be affected by noise when detecting the comparator offset, which will cause calibration errors. In addition, traditional calibration circuits have a single application scenario and often do not have good portability. Summary of the Invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a dual-mode offset calibration circuit for a comparator applied to a high-speed time-interleaved ADC. The technical problems to be solved by the present invention are realized through the following technical solutions:

[0006] A dual-mode offset calibration circuit for a comparator applied to a high-speed time-interleaved ADC, comprising:

[0007] Calibration logic, n channels, and a configurable resistor string; wherein,

[0008] The calibration logic includes detection logic and compensation logic;

[0009] Each channel is respectively connected to the calibration logic and the configurable resistor string;

[0010] Any one of the n channels includes: a switch array, a latch array, and a comparator;

[0011] The detection logic determines the offset polarity of the comparator according to the output result of the comparator, generates an offset polarity selection signal APSEL and ANSEL, and simultaneously generates control signals OPS and ONS;

[0012] The compensation logic generates 64-bit digital codes S0 to S63 according to the control signals OPS and ONS;

[0013] The latch array latches according to the 64-bit digital codes S0 to S63, and correspondingly generates signals S0L to S63L;

[0014] The switch array controls the on / off between itself and the configurable resistor string according to the signals S0L to S63L, and generates a node voltage VCAL;

[0015] The configurable resistor string selects a coarse calibration mode or a fine calibration mode according to the obtained external signal MODESEL;

[0016] The switch array outputs calibration terminal voltages VIPC and VINC according to the offset polarity selection signals APSEL, ANSEL, and the node voltage VCAL, so as to realize the offset calibration of the comparator.

[0017] In an embodiment of the present invention, the circuit structure of the detection logic includes:

[0018] Pulse counter 1, pulse counter 2, D flip-flop 1, D flip-flop 2, and a latch unit; wherein,

[0019] The CLK1 terminal of the pulse counter 1 is connected to the VOP output terminal of the comparator, the Reset1 terminal of the pulse counter 1 is connected to the reset signal RD of the calibration logic, and the OUT1 terminal of the pulse counter 1 is connected to the CLK2 terminal of the D flip-flop 1 and outputs the control signal OPS;

[0020] The D1 input terminal of the D flip-flop 1 is connected to VDD, the Reset2 terminal of the D flip-flop 1 is connected to the reset signal RD of the calibration logic, and the QB1 output terminal of the D flip-flop 1 is connected to the AP input terminal of the latch unit;

[0021] The CLK3 terminal of the pulse counter 2 is connected to the VON output terminal of the comparator. The Reset3 terminal of the pulse counter 2 is connected to the reset signal RD of the calibration logic. The OUT2 terminal of the pulse counter 2 is connected to the CLK4 terminal of the D flip-flop 2 and outputs the control signal ONS.

[0022] The D2 input terminal of the D flip-flop 2 is connected to the VDD. The Reset4 terminal of the D flip-flop 2 is connected to the reset signal RD of the calibration logic. The QB2 output terminal of the D flip-flop 2 is connected to the AN input terminal of the latch unit.

[0023] The RD1 terminal of the latch unit is connected to the reset signal RD of the calibration logic. The APL output terminal of the latch unit outputs the offset polarity selection signal APSEL. The ANL output terminal of the latch unit outputs the offset polarity selection signal ANSEL.

[0024] In an embodiment of the present invention, the pulse counter 1 and the pulse counter 2 have the same structure. The circuit structure of any one of them includes:

[0025] A D flip-flop 3, a D flip-flop 4, a first AND gate, a second AND gate, a first OR gate, and a third AND gate; wherein,

[0026] The CLK5 terminal of the D flip-flop 3 is connected to the first input terminal of the third AND gate and serves as the CLK terminal of the pulse flip-flop. The D3 input terminal of the D flip-flop 3 is connected to the first input terminal of the first AND gate. The Reset5 terminal of the D flip-flop 3 is connected to the Reset6 terminal of the D flip-flop 4 and serves as the Reset terminal of the pulse flip-flop for connecting to the reset signal RD of the calibration logic. The Q3 output terminal of the D flip-flop 3 is connected to the second input terminal of the second AND gate. The QB3 output terminal of the D flip-flop 3 is connected to the D3 input terminal of the D flip-flop 3.

[0027] The CLK6 terminal of the D flip-flop 4 is connected to the first input terminal of the third AND gate. The D4 input terminal of the D flip-flop 4 is connected to the output terminal of the first OR gate. The Q4 output terminal of the D flip-flop 4 is connected to the second input terminal of the first AND gate. The QB4 output terminal of the D flip-flop 4 is connected to the first input terminal of the second AND gate.

[0028] The output terminal of the first AND gate is connected to the first input terminal of the first OR gate. The output terminal of the second AND gate is connected to the second input terminal of the first OR gate.

[0029] The second input terminal of the third AND gate is connected to the Q4 output terminal of the D flip-flop 4. The third input terminal of the third AND gate is connected to the second input terminal of the second AND gate. The output terminal of the third AND gate serves as the OUT terminal of the pulse counter.

[0030] In an embodiment of the present invention, the circuit structure of the latch unit includes:

[0031] MOS transistors M1, M2, M3, M4, M5, M6, M7, M8, a first NOT gate, and a second NOT gate; wherein,

[0032] The source electrode of the MOS transistor M1 is grounded. The gate electrode of the MOS transistor M1 is connected to the output terminal of the first NOT gate. The drain electrode of the MOS transistor M1 is connected to the gate electrode of the MOS transistor M5, serving as the APL output terminal of the latch unit;

[0033] The source electrode of the MOS transistor M2 is grounded. The gate electrode of the MOS transistor M2 is connected to the drain electrode of the MOS transistor M6, serving as the ANL output terminal of the latch unit. The drain electrode of the MOS transistor M2 is connected to the drain electrode of the MOS transistor M5, serving as the APL output terminal of the latch unit;

[0034] The source electrode of the MOS transistor M3 is grounded. The gate electrode of the MOS transistor M3 is connected to the drain electrode of the MOS transistor M5. The drain electrode of the MOS transistor M3 is connected to the drain electrode of the MOS transistor M6;

[0035] The source electrode of the MOS transistor M4 is grounded. The gate electrode of the MOS transistor M4 is connected to the output terminal of the second NOT gate. The drain electrode of the MOS transistor M4 is connected to the drain electrode of the MOS transistor M6;

[0036] The source electrode of the MOS transistor M5 is connected to the drain electrode of the MOS transistor M7. The gate electrode of the MOS transistor M5 serves as the AP input terminal of the latch unit;

[0037] The source electrode of the MOS transistor M6 is connected to the drain electrode of the MOS transistor M8. The gate electrode of the MOS transistor M6 serves as the AN input terminal of the latch unit;

[0038] The source electrode of the MOS transistor M7 is connected to VDD. The gate electrode of the MOS transistor M7 is connected to the gate electrode of the MOS transistor M2;

[0039] The source electrode of the MOS transistor M8 is connected to VDD. The gate electrode of the MOS transistor M8 is connected to the drain electrode of the MOS transistor M2;

[0040] The input terminals of the first NOT gate and the second NOT gate are connected to the RD1 terminal of the latch unit and the reset signal RD of the calibration logic.

[0041] In an embodiment of the present invention, the circuit structure of the compensation logic includes:

[0042] A first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a D flip-flop 5, a D flip-flop 6, a second OR gate, a 6-bit counter, and a 6-64 decoder; wherein,

[0043] The first terminal of the first switch S1 is connected to the control signal ONS, and the second terminal of the first switch S1 is connected to the CLK7 terminal of the D flip-flop 5;

[0044] The first terminal of the second switch S2 is connected to the control signal OPS, and the second terminal of the second switch S2 is connected to the CLK7 terminal of the D flip-flop 5;

[0045] The D5 input terminal of the D flip-flop 5 is connected to VDD, the Reset7 terminal of the D flip-flop 5 is connected to the reset signal RD of the calibration logic, and the Q5 output terminal of the D flip-flop 5 is connected to the first input terminal of the second OR gate;

[0046] The D6 input terminal of the D flip-flop 6 is connected to VDD, the CLK8 terminal of the D flip-flop 6 is connected to the Z output terminal of the 6-bit counter, the Reset8 terminal of the D flip-flop 6 is connected to the reset signal RD of the calibration logic, and the Q6 output terminal of the D flip-flop 6 is connected to the second input terminal of the second OR gate;

[0047] The first terminal of the third switch S3 is connected to the control signal OPS, and the second terminal of the third switch S3 is connected to the CLK9 terminal of the 6-bit counter;

[0048] The first terminal of the fourth switch S4 is connected to the control signal ONS, and the second terminal of the fourth switch S4 is connected to the CLK9 terminal of the 6-bit counter;

[0049] The H input terminal of the 6-bit counter is connected to the output terminal of the second OR gate, the Reset9 terminal of the 6-bit counter is connected to the reset signal RD of the calibration logic, and the Q0-Q5 output terminals of the 6-bit counter are respectively connected to the H0-H5 input terminals of the 6-64 decoder in correspondence;

[0050] The S0-S63 output terminals of the 6-64 decoder are connected to the input terminals of the latch array.

[0051] In an embodiment of the present invention, the circuit structure of the 6-bit counter includes:

[0052] A 3-bit counter 1, a 3-bit counter 2, a third NOT gate, and a fourth AND gate; wherein,

[0053] The H1 terminal of the 3-bit counter 1 serves as the H terminal of the 6-bit counter, the Reset10 terminal of the 3-bit counter 1 and the Reset11 terminal of the 3-bit counter 2 serve as the Reset9 terminal of the 6-bit counter, the CLK10 terminal of the 3-bit counter 1 and the CLK11 terminal of the 3-bit counter 2 serve as the CLK9 terminal of the 6-bit counter, the Qa output terminal of the 3-bit counter 1 is connected to the first input terminal of the fourth AND gate and serves as the Q0 output terminal of the 6-bit counter, the Qb output terminal of the 3-bit counter 1 is connected to the second input terminal of the fourth AND gate and serves as the Q1 output terminal of the 6-bit counter, the Qc output terminal of the 3-bit counter 1 is connected to the third input terminal of the fourth AND gate and serves as the Q2 output terminal of the 6-bit counter, and the Z1 output terminal of the 3-bit counter 1 is connected to the input terminal of the third NOT gate;

[0054] The output terminal of the third NOT gate is connected to the H2 terminal of the 3-bit counter 2;

[0055] The Qd output terminal of the 3-bit counter 2 serves as the Q3 output terminal of the 6-bit counter, the Qe output terminal of the 3-bit counter 2 serves as the Q4 output terminal of the 6-bit counter, the Qf output terminal of the 3-bit counter 1 serves as the Q5 output terminal of the 6-bit counter, the Z2 output terminal of the 3-bit counter 2 is connected to the fourth input terminal of the fourth AND gate, and the output terminal of the fourth AND gate serves as the Z output terminal of the 6-bit counter.

[0056] In an embodiment of the present invention, the circuit structure of the latch array includes:

[0057] 64 groups of identical latch modules; the input terminals of each group of latch modules are respectively connected to the S0 to S63 output terminals of the 6-64 decoder in a corresponding manner, and the output terminals of each group of latch modules output signals S0L to S63L, wherein,

[0058] Any one of the 64 groups of identical latch modules includes:

[0059] A switch 1, a switch 2, an inverter 1, and an inverter 2;

[0060] The first terminal of the switch 1 is correspondingly connected to one end of the S0 to S63 output terminals of the 6-64 decoder, and the second terminal of the switch 1 is connected to the input terminal of the inverter 1;

[0061] The first terminal of the switch 2 is connected to the second terminal of the switch 1, and the second terminal of the switch 2 is connected to the output terminal of the inverter 2;

[0062] The output terminal of the inverter 1 is connected to the input terminal of the inverter 2;

[0063] The output terminal of the inverter 2 correspondingly outputs one of the output signals S0L to S63L.

[0064] In an embodiment of the present invention, the circuit structure of the configurable resistor string includes:

[0065] MOS transistor M9, MOS transistor M10, first resistor, second resistor, third resistor, fourth resistor, switch 3, switch 4, fourth NOT gate, and resistor string; wherein,

[0066] The source of the MOS transistor M9 is grounded, the gate of the MOS transistor M9 is connected to the enable signal SEL, and the drain of the MOS transistor M9 is connected to the first end of the first resistor;

[0067] The second end of the first resistor is connected to the first end of the resistor string;

[0068] The first end of the second resistor is connected to the drain of the MOS transistor M9, and the second end of the second resistor is connected to the first end of the switch 3;

[0069] The second end of the switch 3 is connected to the second end of the first resistor;

[0070] The resistor string is composed of 64 resistors connected in series. Among them, voltages V1 to V63 are respectively led out between adjacent resistors in sequence, voltage VL is led out from the first end of the resistor string, and voltage VH is led out from the second end of the resistor string;

[0071] The first end of the third resistor is connected to the drain of the MOS transistor M10, and the second end of the third resistor is connected to the second end of the resistor string;

[0072] The first end of the fourth resistor is connected to the first end of the third resistor;

[0073] The first end of the switch 4 is connected to the second end of the resistor string, and the second end of the switch 4 is connected to the second end of the fourth resistor;

[0074] The source of the MOS transistor M10 is connected to VDD, and the gate of the MOS transistor M10 is connected to the output terminal of the fourth NOT gate;

[0075] The input terminal of the fourth NOT gate is connected to the enable signal SEL.

[0076] In an embodiment of the present invention, the circuit structure of the switch array includes:

[0077] 64 switches, switch 5, switch 6, switch 7, and switch 8; wherein,

[0078] The first ends of the 64 switches are respectively connected to the voltages VL to V63 in correspondence, and the second ends of the 64 switches are joined at a first node;

[0079] The first end of switch 5 is connected to the voltage VCAL of the first node, and the second end of switch 5 is joined to the second end of switch 6 at a second node;

[0080] The first end of switch 6 is connected to the voltage VL led out from the first end of the resistor string;

[0081] The first end of switch 7 is connected to the voltage VCAL of the first node, and the second end of switch 7 is joined to the second end of switch 8 at a third node;

[0082] The first end of switch 8 is connected to the voltage VL led out from the first end of the resistor string;

[0083] The voltage of the second node is used as the calibration terminal voltage VIPC;

[0084] The voltage of the third node is used as the calibration terminal voltage VINC.

[0085] Advantages of the present invention:

[0086] In the solution provided by the embodiments of the present invention, the detection logic is proposed to reduce the noise influence in the comparator offset detection process; a plurality of channels share one calibration logic and a configurable resistor string, greatly reducing the power consumption and area of the circuit; the configurable resistor string correspondingly selects a coarse calibration mode or a fine calibration mode according to the obtained external signal MODESEL. The coarse calibration mode has a larger calibration range and a faster convergence speed compared with the fine calibration mode, while the fine calibration mode has a higher calibration accuracy compared with the coarse calibration mode. The embodiments of the present invention have two working modes, which can better adapt to comparators with different structures and performances and have a wider application scenario. Description of the Drawings

[0087] Figure 1 It is a schematic structural diagram of a dual-mode offset calibration circuit for a comparator applied to a high-speed time-interleaved ADC provided by an embodiment of the present invention;

[0088] Figure 2 It is a schematic structural diagram of a single-channel offset calibration circuit in a dual-mode offset calibration circuit for a comparator applied to a high-speed time-interleaved ADC provided by an embodiment of the present invention;

[0089] Figure 3 It is a schematic structural diagram of a detection logic in a dual-mode offset calibration circuit for a comparator applied to a high-speed time-interleaved ADC provided by an embodiment of the present invention;

[0090] Figure 4 Schematic diagram of a pulse counter in a dual - mode offset calibration circuit for a comparator applied to a high - speed time - interleaved ADC provided by an embodiment of the present invention;

[0091] Figure 5 Schematic diagram of a latch unit in a dual - mode offset calibration circuit for a comparator applied to a high - speed time - interleaved ADC provided by an embodiment of the present invention;

[0092] Figure 6 Schematic diagram of a compensation logic in a dual - mode offset calibration circuit for a comparator applied to a high - speed time - interleaved ADC provided by an embodiment of the present invention;

[0093] Figure 7 Schematic diagram of a 6 - bit counter in a dual - mode offset calibration circuit for a comparator applied to a high - speed time - interleaved ADC provided by an embodiment of the present invention;

[0094] Figure 8 Schematic diagram of a latch array in a dual - mode offset calibration circuit for a comparator applied to a high - speed time - interleaved ADC provided by an embodiment of the present invention;

[0095] Figure 9 Schematic diagram of a configurable resistor string in a dual - mode offset calibration circuit for a comparator applied to a high - speed time - interleaved ADC provided by an embodiment of the present invention;

[0096] Figure 10 Schematic diagram of a switch array in a dual - mode offset calibration circuit for a comparator applied to a high - speed time - interleaved ADC provided by an embodiment of the present invention. Detailed implementation manners

[0097] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0098] An embodiment of the present invention proposes a dual - mode offset calibration circuit for a comparator applied to a high - speed time - interleaved ADC. Refer to Figure 1 , including:

[0099] Calibration logic, n channels, and a configurable resistor string; wherein,

[0100] The calibration logic includes detection logic and compensation logic;

[0101] Each channel is respectively connected to calibration logic and a configurable resistor string;

[0102] Any one of the n channels includes: a switch array, a latch array, and a comparator;

[0103] The detection logic determines the offset polarity of the comparator according to the output result of the comparator, generates offset polarity selection signals APSEL and ANSEL, and simultaneously generates control signals OPS and ONS;

[0104] The compensation logic generates 64-bit digital codes S0 to S63 according to the control signals OPS and ONS;

[0105] The latch array latches according to the 64-bit digital codes S0 to S63, and correspondingly generates signals S0L to S63L;

[0106] The switch array controls the on / off between itself and the configurable resistor string according to the signals S0L to S63L, generating a node voltage VCAL;

[0107] The configurable resistor string selects a coarse calibration mode or a fine calibration mode according to the obtained external signal MODESEL;

[0108] The switch array outputs calibration terminal voltages VIPC and VINC according to the offset polarity selection signals APSEL, ANSEL, and the node voltage VCAL, realizing offset calibration of the comparator.

[0109] The embodiment of the present invention mainly designs a comparator offset calibration circuit applied to a time-interleaved ADC. The circuit is mainly composed of calibration logic, a switch array, a latch array, and a configurable resistor string. In a multi-channel time-interleaved ADC, multiple channels can share one calibration logic and one configurable resistor string. Among them, the calibration logic is specifically composed of detection logic and compensation logic; the detection logic is composed of D flip-flops, pulse counters, and latch units; the compensation logic is composed of D flip-flops, 6-bit counters with hold and asynchronous clear functions, 6-64 decoders, switches, and logic gates.

[0110] Select a suitable calibration circuit operating mode according to the offset voltage range of the comparator in the time-interleaved ADC and the accuracy required by the ADC. When the mode selection signal MODESEL is at a high level, the offset calibration circuit can perform coarse calibration on the comparator offset voltage. When the mode selection signal MODESEL is at a low level, the offset calibration circuit can perform fine calibration on the comparator offset voltage. The coarse calibration mode of the calibration circuit has a larger calibration range and a faster convergence speed compared with the fine calibration mode, while the fine calibration mode has a higher calibration accuracy compared with the coarse calibration mode.

[0111] The comparator offset calibration process for all channels of the time-interleaved ADC is the same. Refer toFigure 2 , taking the calibration process of a single channel as an example, the comparator offset calibration process is introduced as follows:

[0112] 1) Before the calibration starts, connect the input terminals VIN and VIP of the comparator to the common-mode level Vcm (Vcm is half of the power supply voltage). Subsequently, the comparator starts to compare and outputs the comparison results VOP and VON.

[0113] 2) The detection logic determines the offset polarity of the comparator according to the comparison result of the comparator, generates the offset polarity selection signals APSEL and ANSEL, and generates the control signals OPS and ONS for the compensation logic.

[0114] 3) The compensation logic generates 64-bit digital codes S0 - S63 under the control of the detection logic.

[0115] 4) The 64-bit digital codes S0 - S63 are latched by the latch array to generate signals S0L - S63L. S0L - S63L generate the calibration terminal voltages VIPC and VINC by controlling the connection relationship between the switch array and the configurable resistor string.

[0116] In specific applications, the appropriate calibration circuit operating mode can be selected according to the offset voltage range of the comparator in the time-interleaved ADC and the accuracy required by the ADC: one operating mode can perform coarse calibration on the comparator offset voltage, and the other operating mode can perform fine calibration on the comparator offset voltage. The calibration circuit with two operating modes can better adapt to comparators with different structures and performances. In a multi-channel time-interleaved ADC, multiple channels can share a calibration logic and a configurable resistor string, greatly reducing the power consumption and area of the offset calibration circuit compared with the traditional structure.

[0117] For ease of understanding, each module in the following embodiments of the present invention will be introduced separately.

[0118] Calibration Logic

[0119] The calibration logic includes: detection logic and compensation logic.

[0120] The circuit structure of the detection logic is as Figure 3 shown and includes:

[0121] Pulse counter 1, pulse counter 2, D flip-flop 1, D flip-flop 2, and latch unit; among them,

[0122] The CLK1 terminal of pulse counter 1 is connected to the VOP output terminal of the comparator, the Reset1 terminal of pulse counter 1 is connected to the reset signal RD of the calibration logic, and the OUT1 terminal of pulse counter 1 is connected to the CLK2 terminal of D flip-flop 1 and outputs the control signal OPS;

[0123] The D1 input terminal of D flip-flop 1 is connected to VDD, the Reset2 terminal of D flip-flop 1 is connected to the reset signal RD of the calibration logic, and the QB1 output terminal of D flip-flop 1 is connected to the AP input terminal of the latch unit;

[0124] The CLK3 terminal of pulse counter 2 is connected to the VON output terminal of the comparator, the Reset3 terminal of pulse counter 2 is connected to the reset signal RD of the calibration logic, and the OUT2 terminal of pulse counter 2 is connected to the CLK4 terminal of D flip-flop 2 and outputs the control signal ONS;

[0125] The D2 input terminal of D flip-flop 2 is connected to VDD, the Reset4 terminal of D flip-flop 2 is connected to the reset signal RD of the calibration logic, and the QB2 output terminal of D flip-flop 2 is connected to the AN input terminal of the latch unit;

[0126] The RD1 terminal of the latch unit is connected to the reset signal RD of the calibration logic, the APL output terminal of the latch unit outputs the offset polarity selection signal APSEL, and the ANL output terminal of the latch unit outputs the offset polarity selection signal ANSEL.

[0127] The detection logic determines the offset polarity of the comparator according to the output result of the comparator, generates the offset polarity selection signals APSEL and ANSEL, and simultaneously generates the control signals OPS and ONS.

[0128] Specifically, pulse counter 1 and pulse counter 2 have the same structure, and the circuit structure of any one of them is as Figure 4 shown, including:

[0129] D flip-flop 3, D flip-flop 4, the first AND gate, the second AND gate, the first OR gate, and the third AND gate; among them,

[0130] The CLK5 terminal of D flip-flop 3 is connected to the first input terminal of the third AND gate as the CLK terminal of the pulse flip-flop, the D3 input terminal of D flip-flop 3 is connected to the first input terminal of the first AND gate, the Reset5 terminal of D flip-flop 3 is connected to the Reset6 terminal of D flip-flop 4 as the Reset terminal of the pulse flip-flop for connecting the reset signal RD of the calibration logic, the Q3 output terminal of D flip-flop 3 is connected to the second input terminal of the second AND gate, and the QB3 output terminal of D flip-flop 3 is connected to the D3 input terminal of D flip-flop 3;

[0131] The CLK6 terminal of D flip-flop 4 is connected to the first input terminal of the third AND gate, the D4 input terminal of D flip-flop 4 is connected to the output terminal of the first OR gate, the Q4 output terminal of D flip-flop 4 is connected to the second input terminal of the first AND gate, and the QB4 output terminal of D flip-flop 4 is connected to the first input terminal of the second AND gate;

[0132] The output terminal of the first AND gate is connected to the first input terminal of the first OR gate, and the output terminal of the second AND gate is connected to the second input terminal of the first OR gate;

[0133] The second input terminal of the third AND gate is connected to the Q4 output terminal of the D flip-flop 4, the third input terminal of the third AND gate is connected to the second input terminal of the second AND gate, and the output terminal of the third AND gate serves as the OUT terminal of the pulse counter.

[0134] RD is the reset signal RD of the calibration logic. When RD is at a low level, the reset operation is performed; when RD is at a high level, the circuit operates normally.

[0135] The pulse counters 1 and 2 respectively detect the number of pulses at the two output terminals VOP and VON of the comparator. For every four pulses generated at the output terminals of the comparator, the pulse counter outputs one pulse. If the pulse counter at the VOP terminal outputs the first pulse first, it is determined that the P terminal of the comparator needs compensation, that is, the voltage at the calibration terminal VIPC needs to be raised; otherwise, it is determined that the N terminal of the comparator needs compensation, that is, the voltage at the calibration terminal VINC needs to be raised. The pulse counters 1 and 2 output control signals OPS and ONS.

[0136] Specifically, the circuit structure of the latch unit is as Figure 5 shown, including:

[0137] MOS transistors M1, M2, M3, M4, M5, M6, M7, M8, the first NOT gate, and the second NOT gate; among them,

[0138] The source of the MOS transistor M1 is grounded, the gate of the MOS transistor M1 is connected to the output terminal of the first NOT gate, and the drain of the MOS transistor M1 is connected to the gate of the MOS transistor M5, serving as the APL output terminal of the latch unit;

[0139] The source of the MOS transistor M2 is grounded, the gate of the MOS transistor M2 is connected to the drain of the MOS transistor M6, serving as the ANL output terminal of the latch unit, and the drain of the MOS transistor M2 is connected to the drain of the MOS transistor M5, serving as the APL output terminal of the latch unit;

[0140] The source of the MOS transistor M3 is grounded, the gate of the MOS transistor M3 is connected to the drain of the MOS transistor M5, and the drain of the MOS transistor M3 is connected to the drain of the MOS transistor M6;

[0141] The source of the MOS transistor M4 is grounded, the gate of the MOS transistor M4 is connected to the output terminal of the second NOT gate, and the drain of the MOS transistor M4 is connected to the drain of the MOS transistor M6;

[0142] The source of MOS transistor M5 is connected to the drain of MOS transistor M7, and the gate of MOS transistor M5 serves as the AP input terminal of the latch unit;

[0143] The source of MOS transistor M6 is connected to the drain of MOS transistor M8, and the gate of MOS transistor M6 serves as the AN input terminal of the latch unit;

[0144] The source of MOS transistor M7 is connected to VDD, and the gate of MOS transistor M7 is connected to the gate of MOS transistor M2;

[0145] The source of MOS transistor M8 is connected to VDD, and the gate of MOS transistor M8 is connected to the drain of MOS transistor M2;

[0146] The input terminals of the first NOT gate and the second NOT gate serve as the RD1 terminal of the latch unit and are connected to the reset signal RD of the calibration logic.

[0147] The outputs OPS and ONS of the two pulse counters pass through D flip - flops and a latch unit to generate the offset polarity selection signals APSEL and ANSEL. When the offset polarity selection signal APSEL is high and ANSEL is low, the calibration terminal VIPC is defined as the lift terminal and the calibration terminal VINC is defined as the hold terminal; when the offset polarity selection signal APSEL is low and ANSEL is high, the calibration terminal VIPC is defined as the hold terminal and the calibration terminal VINC is defined as the lift terminal.

[0148] The specific working process of the detection logic is as follows: The comparator outputs VOP and VON respectively pass through pulse counter 1 and pulse counter 2 to generate control signals OPS and ONS. OPS and ONS serve as the clock signals of two D flip - flops respectively. The input signals of the two D flip - flops are both connected to the high - level VDD. The inverted output terminals QB of the two D flip - flops are respectively connected to the latch inputs AP and AN. At the initial moment, AP and AN are high - level, and APL and ANL are low - level. Subsequently, if OPS becomes high level first, then AP becomes low level before AN, and the latch unit outputs APL latched as high level and ANL latched as low level; if ONS becomes high level first, then AN becomes low level before AP, and the latch unit outputs APL latched as low level and ANL latched as high level. The latch unit outputs APL and ANL as the offset polarity selection signals APSEL and ANSEL of the calibration circuit respectively. When the offset polarity selection signal APSEL is high and ANSEL is low, the calibration terminal VIPC is defined as the lift terminal and the calibration terminal VINC is defined as the hold terminal; when the offset polarity selection signal APSEL is low and ANSEL is high, the calibration terminal VIPC is defined as the hold terminal and the calibration terminal VINC is defined as the lift terminal.

[0149] The circuit structure of the compensation logic is as Figure 6As shown, it includes:

[0150] The first switch S1, the second switch S2, the third switch S3, the fourth switch S4, D flip-flop 5, D flip-flop 6, the second OR gate, a 6-bit counter, and a 6-64 decoder; where

[0151] The first end of the first switch S1 is connected to the control signal ONS, and the second end of the first switch S1 is connected to the CLK7 terminal of D flip-flop 5;

[0152] The first end of the second switch S2 is connected to the control signal OPS, and the second end of the second switch S2 is connected to the CLK7 terminal of D flip-flop 5;

[0153] The D5 input terminal of D flip-flop 5 is connected to VDD, the Reset7 terminal of D flip-flop 5 is connected to the reset signal RD of the calibration logic, and the Q5 output terminal of D flip-flop 5 is connected to the first input terminal of the second OR gate;

[0154] The D6 input terminal of D flip-flop 6 is connected to VDD, the CLK8 terminal of D flip-flop 6 is connected to the Z output terminal of the 6-bit counter, the Reset8 terminal of D flip-flop 6 is connected to the reset signal RD of the calibration logic, and the Q6 output terminal of D flip-flop 6 is connected to the second input terminal of the second OR gate;

[0155] The first end of the third switch S3 is connected to the control signal OPS, and the second end of the third switch S3 is connected to the CLK9 terminal of the 6-bit counter;

[0156] The first end of the fourth switch S4 is connected to the control signal ONS, and the second end of the fourth switch S4 is connected to the CLK9 terminal of the 6-bit counter;

[0157] The H input terminal of the 6-bit counter is connected to the output terminal of the second OR gate, the Reset9 terminal of the 6-bit counter is connected to the reset signal RD of the calibration logic, and the Q0 - Q5 output terminals of the 6-bit counter are respectively connected to the H0 - H5 input terminals of the 6-64 decoder in correspondence;

[0158] The S0 - S63 output terminals of the 6-64 decoder are connected to the input terminals of the latch array.

[0159] The compensation logic generates 64-bit digital codes S0 - S63 according to the control signals OPS and ONS.

[0160] Specifically, the circuit structure of the 6-bit counter is as Figure 7 shown, and it includes:

[0161] A 3-bit counter 1, a 3-bit counter 2, a third NOT gate, and a fourth AND gate; where

[0162] The H1 terminal of the 3-bit counter 1 serves as the H terminal of the 6-bit counter. The Reset10 terminal of the 3-bit counter 1 and the Reset11 terminal of the 3-bit counter 2 serve as the Reset9 terminal of the 6-bit counter. The CLK10 terminal of the 3-bit counter 1 and the CLK11 terminal of the 3-bit counter 2 serve as the CLK9 terminal of the 6-bit counter. The Qa output terminal of the 3-bit counter 1 is connected to the first input terminal of the fourth AND gate and serves as the Q0 output terminal of the 6-bit counter. The Qb output terminal of the 3-bit counter 1 is connected to the second input terminal of the fourth AND gate and serves as the Q1 output terminal of the 6-bit counter. The Qc output terminal of the 3-bit counter 1 is connected to the third input terminal of the fourth AND gate and serves as the Q2 output terminal of the 6-bit counter. The Z1 output terminal of the 3-bit counter 1 is connected to the input terminal of the third NOT gate;

[0163] The output terminal of the third NOT gate is connected to the H2 terminal of the 3-bit counter 2;

[0164] The Qd output terminal of the 3-bit counter 2 serves as the Q3 output terminal of the 6-bit counter. The Qe output terminal of the 3-bit counter 2 serves as the Q4 output terminal of the 6-bit counter. The Qf output terminal of the 3-bit counter 1 serves as the Q5 output terminal of the 6-bit counter. The Z2 output terminal of the 3-bit counter 2 is connected to the fourth input terminal of the fourth AND gate. The output terminal of the fourth AND gate serves as the Z output terminal of the 6-bit counter.

[0165] When the reset signal RD of the calibration logic is at a low level, the 6-bit counter is reset; when the reset signal RD of the calibration logic is at a high level, the 6-bit counter operates normally.

[0166] According to the offset polarity selection signals APSEL and ANSEL, one of the two pulse counter outputs OPS and ONS is selected as the pulse input signal of the 6-bit counter. The 6-bit counter starts counting the number of pulses of OPS or ONS from zero. The output of the counter is a 6-bit binary number Q 5 Q 4 Q 3 Q 2 Q 1 Q 0 and the carry signal Z. When one of the two pulse counter outputs OPS and ONS is used as the pulse input signal of the 6-bit counter, the other signal serves as the stop signal HCLK of the compensation logic. The carry signal Z of the counter serves as another stop signal ZCLK of the compensation logic.

[0167] The specific working process of the compensation logic is as follows: when the offset polarity selection signal APSEL is at a high level and ANSEL is at a low level, the calibration terminal VIPC is defined as the lifting terminal, the calibration terminal VINC is defined as the holding terminal, and OPS serves as the pulse input signal of a 6-bit counter; when the offset polarity selection signal APSEL is at a low level and ANSEL is at a high level, the calibration terminal VIPC is defined as the holding terminal, the calibration terminal VINC is defined as the lifting terminal, and ONS serves as the pulse input signal of a 6-bit counter. The 6-bit counter starts from zero to count the number of pulses of OPS or ONS, and the output of the counter is a 6-bit binary number and a carry signal Z. When OPS serves as the pulse input signal of the 6-bit counter, ONS serves as the stop signal HCLK of the compensation logic. When ONS serves as the pulse input signal of the 6-bit counter, OPS serves as the stop signal HCLK of the compensation logic. The carry signal Z of the counter serves as another stop signal ZCLK of the compensation logic. HCLK and ZCLK generate the holding signal H of the counter through a D flip-flop and a two-input OR gate. When HCLK or ZCLK changes from a low level to a high level, the holding signal H also changes from a low level to a high level. At this time, the counter stops counting and keeps the 6-bit binary number output by the counter unchanged. The 6-bit binary number generates 64-bit digital codes S0 - S63 through a 6-64 decoder.

[0168] Latch array

[0169] Specifically, the circuit structure of the latch array is as Figure 8 shown, including:

[0170] 64 groups of identical latch modules; the input ends of each group of latch modules are respectively connected to the S0 - S63 output ends of the 6-64 decoder in a corresponding manner, and the output ends of each group of latch modules output signals S0L - S63L respectively, where

[0171] Any one of the 64 groups of identical latch modules includes:

[0172] Switch 1, Switch 2, Inverter 1, and Inverter 2;

[0173] The first end of Switch 1 is correspondingly connected to one end of the S0 - S63 output ends of the 6-64 decoder, and the second end of Switch 1 is connected to the input end of Inverter 1;

[0174] The first end of Switch 2 is connected to the second end of Switch 1, and the second end of Switch 2 is connected to the output end of Inverter 2;

[0175] The output end of Inverter 1 is connected to the input end of Inverter 2;

[0176] The output end of Inverter 2 correspondingly outputs one of the output signals S0L - S63L.

[0177] The latch array is composed of 64 identical latch modules. For the sake of easy understanding, any one of the 64 identical latch modules will be described. Among them, switch 1 is a switch connected to the S0 to S63 output terminals of the 6-64 decoder, switch 2 is a switch connected to the S0L to S63L output terminals of the latch array, inverter 1 is an inverter close to the S0 to S63 output terminals of the 6-64 decoder, and inverter 2 is an inverter close to the S0L to S63L output terminals of the latch array.

[0178] The latch array latches according to the 64-bit digital code S0 to S63 and correspondingly generates signals S0L to S63L. The latch array is composed of inverters and switches. When the signal EN is at a high level, the latch writes. When the signal EN is at a low level, the latch latches.

[0179] Configurable resistor string

[0180] Specifically, the circuit structure of the configurable resistor string is as Figure 9 shown, including:

[0181] MOS transistor M9, MOS transistor M10, first resistor, second resistor, third resistor, fourth resistor, switch 3, switch 4, fourth NOT gate, and resistor string; among them,

[0182] The source of MOS transistor M9 is grounded, the gate of MOS transistor M9 is connected to the enable signal SEL, and the drain of MOS transistor M9 is connected to the first end of the first resistor;

[0183] The second end of the first resistor is connected to the first end of the resistor string;

[0184] The first end of the second resistor is connected to the drain of MOS transistor M9, and the second end of the second resistor is connected to the first end of switch 3;

[0185] The second end of switch 3 is connected to the second end of the first resistor;

[0186] The resistor string is composed of 64 resistors connected in series. Among them, voltages V1 to V63 are sequentially led out between adjacent resistors, voltage VL is led out from the first end of the resistor string, and voltage VH is led out from the second end of the resistor string;

[0187] The first end of the third resistor is connected to the drain of MOS transistor M10, and the second end of the third resistor is connected to the second end of the resistor string;

[0188] The first end of the fourth resistor is connected to the first end of the third resistor;

[0189] The first end of switch 4 is connected to the second end of the resistor string, and the second end of switch 4 is connected to the second end of the fourth resistor;

[0190] The source of MOS transistor M10 is connected to VDD, and the gate of MOS transistor M10 is connected to the output terminal of the fourth NOT gate;

[0191] The input terminal of the fourth NOT gate is connected to the enable signal SEL.

[0192] The configurable resistor string selects the coarse calibration mode or the fine calibration mode according to the obtained external signal MODESEL.

[0193] The configurable resistor string is generated by connecting 64 resistors in series to produce a voltage division. SEL is the enable signal of the resistor string. When SEL is at a high level, the circuit works normally. When SEL is at a low level, the resistor string is disconnected from the power supply, there is no static current, and power consumption is saved. The MODESEL signal is the mode selection signal of the resistor string. When the mode selection signal MODESEL is at a high level, the offset calibration circuit can perform coarse calibration on the comparator offset voltage. When the mode selection signal MODESEL is at a low level, the offset calibration circuit can perform fine calibration on the comparator offset voltage.

[0194] Switch array

[0195] Specifically, the circuit structure of the switch array is as Figure 10 shown, including:

[0196] 64 switches, switch 5, switch 6, switch 7 and switch 8; among them,

[0197] The first ends of the 64 switches are respectively connected to voltages VL to V63 correspondingly, and the second ends of the 64 switches are joined at a first node;

[0198] The first end of switch 5 accesses the voltage VCAL of the first node, and the second end of switch 5 is joined with the second end of switch 6 at a second node;

[0199] The first end of switch 6 accesses the voltage VL led out from the first end of the resistor string;

[0200] The first end of switch 7 accesses the voltage VCAL of the first node, and the second end of switch 7 is joined with the second end of switch 8 at a third node;

[0201] The first end of switch 8 accesses the voltage VL led out from the first end of the resistor string;

[0202] The voltage of the second node is used as the calibration terminal voltage VIPC;

[0203] The voltage of the third node is used as the calibration terminal voltage VINC.

[0204] The switches in the switch array are turned on when at a high level and turned off when at a low level. The 64 switches on the left are controlled by signals S0L - S63L, whose inputs are the 64 voltage divisions VL - V63 of the resistor string, and the output is node VCAL. The switches 5, 6, 7, and 8 on the right are controlled by selection signals APSEL and ANSEL, making VCAL the voltage of the lifting end in the calibration terminal and VL the voltage of the holding end in the calibration terminal.

[0205] S0L - S63L generate the voltage VCAL by controlling the connection relationship between the switch array and the configurable resistor string. Through the selection of the offset polarity selection signals APSEL and ANSEL, VCAL is the voltage of the lifting end in the calibration terminal, and VL is the voltage of the holding end in the calibration terminal. The switch array controls the on - off between itself and the configurable resistor string according to signals S0L~S63L to generate the node voltage VCAL; and outputs the calibration terminal voltages VIPC and VINC according to the offset polarity selection signals APSEL, ANSEL, and the node voltage VCAL to achieve the offset calibration of the comparator.

[0206] In the solution provided by the embodiments of the present invention, the proposed detection logic is used to reduce the noise influence in the comparator offset detection process; multiple channels share one calibration logic and a configurable resistor string, greatly reducing the power consumption and area of the circuit; the configurable resistor string selects the coarse calibration mode or the fine calibration mode according to the obtained external signal MODESEL. The coarse calibration mode has a larger calibration range and a faster convergence speed compared with the fine calibration mode, while the fine calibration mode has a higher calibration accuracy compared with the coarse calibration mode. The embodiments of the present invention have two working modes, which can better adapt to comparators with different structures and performances and have a wider application scenario.

[0207] The above are only the preferred embodiments of the present invention and are not intended to limit the protection scope of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims

1. A dual-mode offset calibration circuit for a comparator of a high-speed time-domain interleaved ADC, characterized in that: include: calibration logic, n channels, and configurable resistor strings; where The calibration logic includes detection logic and compensation logic; Each channel is respectively connected to the calibration logic and the configurable resistor string; Any one of the n channels includes: a switch array, a latch array and a comparator; The detection logic determines the offset polarity of the comparator according to the output result of the comparator, generates offset polarity selection signals APSEL and ANSEL, and generates control signals OPS and ONS; The compensation logic generates 64-bit digital codes S0-S63 according to the control signals OPS and ONS; The latch array performs latching according to the 64-bit digital code S0-S63, and correspondingly generates signals S0L-S63L; The switch array controls the connection and disconnection between itself and the configurable resistor string according to the signals S0L-S63L to generate a node voltage VCAL; The configurable resistor string selects a coarse calibration mode or a fine calibration mode according to the obtained external signal MODESEL; The switch array outputs calibration terminal voltages VIPC and VINC according to the offset polarity selection signals APSEL, ANSEL and the node voltage VCAL to achieve offset calibration of the comparator.

2. The dual-mode offset calibration circuit for a comparator applied to a high-speed time-domain interleaved ADC according to claim 1, characterized in that: The circuit structure of the detection logic includes: Pulse counter 1, pulse counter 2, D flip-flop 1, D flip-flop 2 and latch unit; wherein, The CLK1 terminal of the pulse counter 1 is connected to the VOP output terminal of the comparator, the Reset1 terminal of the pulse counter 1 is connected to the reset signal RD of the calibration logic, the OUT1 terminal of the pulse counter 1 is connected to the CLK2 terminal of the D flip-flop 1, and outputs the control signal OPS; The D1 input terminal of the D flip-flop 1 is connected to VDD, the Reset2 terminal of the D flip-flop 1 is connected to the reset signal RD of the calibration logic, and the QB1 output terminal of the D flip-flop 1 is connected to the AP input terminal of the latch unit; The CLK3 terminal of the pulse counter 2 is connected to the VON output terminal of the comparator, the Reset3 terminal of the pulse counter 2 is connected to the reset signal RD of the calibration logic, the OUT2 terminal of the pulse counter 2 is connected to the CLK4 terminal of the D flip-flop 2, and outputs the control signal ONS; The D2 input terminal of the D flip-flop 2 is connected to the VDD, the Reset4 terminal of the D flip-flop 2 is connected to the reset signal RD of the calibration logic, and the QB2 output terminal of the D flip-flop 2 is connected to the AN input terminal of the latch unit; The RD1 terminal of the latch unit is connected to the reset signal RD of the calibration logic, the APL output terminal of the latch unit outputs the offset polarity selection signal APSEL, and the ANL output terminal of the latch unit outputs the offset polarity selection signal ANSEL.

3. The dual-mode offset calibration circuit for a comparator applied to a high-speed time-domain interleaved ADC according to claim 2, characterized in that: The pulse counter 1 and the pulse counter 2 have the same structure, and the circuit structure of either of them includes: D flip-flop 3, D flip-flop 4, a first AND gate, a second AND gate, a first OR gate and a third AND gate; wherein, The CLK5 terminal of the D flip-flop 3 is connected to the first input terminal of the third AND gate as the CLK terminal of the pulse flip-flop, the D3 input terminal of the D flip-flop 3 is connected to the first input terminal of the first AND gate, the Reset5 terminal of the D flip-flop 3 is connected to the Reset6 terminal of the D flip-flop 4 as the Reset terminal of the pulse flip-flop, which is used to connect the reset signal RD of the calibration logic, the Q3 output terminal of the D flip-flop 3 is connected to the second input terminal of the second AND gate, and the QB3 output terminal of the D flip-flop 3 is connected to the D3 input terminal of the D flip-flop 3; The CLK6 terminal of the D flip-flop 4 is connected to the first input terminal of the third AND gate, the D4 input terminal of the D flip-flop 4 is connected to the output terminal of the first OR gate, the Q4 output terminal of the D flip-flop 4 is connected to the second input terminal of the first AND gate, and the QB4 output terminal of the D flip-flop 4 is connected to the first input terminal of the second AND gate; The output end of the first AND gate is connected to the first input end of the first OR gate, and the output end of the second AND gate is connected to the second input end of the first OR gate; The second input terminal of the third AND gate is connected to the Q4 output terminal of the D flip-flop 4, the third input terminal of the third AND gate is connected to the second input terminal of the second AND gate, and the output terminal of the third AND gate serves as the OUT terminal of the pulse counter.

4. The dual-mode offset calibration circuit for a comparator applied to a high-speed time-domain interleaved ADC according to claim 3, characterized in that: The circuit structure of the latch unit includes: MOS tube M1, MOS tube M2, MOS tube M3, MOS tube M4, MOS tube M5, MOS tube M6, MOS tube M7, MOS tube M8, a first NOT gate and a second NOT gate; wherein, The source of the MOS transistor M1 is grounded, the gate of the MOS transistor M1 is connected to the output end of the first NOT gate, and the drain of the MOS transistor M1 is connected to the gate of the MOS transistor M5, serving as the APL output end of the latch unit; The source of the MOS tube M2 is grounded, the gate of the MOS tube M2 is connected to the drain of the MOS tube M6 as the ANL output end of the latch unit, and the drain of the MOS tube M2 is connected to the drain of the MOS tube M5 as the APL output end of the latch unit; The source of the MOS tube M3 is grounded, the gate of the MOS tube M3 is connected to the drain of the MOS tube M5, and the drain of the MOS tube M3 is connected to the drain of the MOS tube M6; The source of the MOS tube M4 is grounded, the gate of the MOS tube M4 is connected to the output end of the second NOT gate, and the drain of the MOS tube M4 is connected to the drain of the MOS tube M6; The source of the MOS tube M5 is connected to the drain of the MOS tube M7, and the gate of the MOS tube M5 serves as the AP input terminal of the latch unit; The source of the MOS tube M6 is connected to the drain of the MOS tube M8, and the gate of the MOS tube M6 serves as the AN input terminal of the latch unit; The source of the MOS tube M7 is connected to VDD, and the gate of the MOS tube M7 is connected to the gate of the MOS tube M2; The source of the MOS tube M8 is connected to VDD, and the gate of the MOS tube M8 is connected to the drain of the MOS tube M2; The input end of the first NOT gate and the input end of the second NOT gate are connected to the reset signal RD of the calibration logic as the RD1 end of the latch unit.

5. The dual-mode offset calibration circuit for a comparator applied to a high-speed time-domain interleaved ADC according to claim 4, characterized in that: The circuit structure of the compensation logic includes: A first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a D flip-flop 5, a D flip-flop 6, a second OR gate, a 6-bit counter and a 6-64 decoder; wherein, The first end of the first switch S1 is connected to the control signal ONS, and the second end of the first switch S1 is connected to the CLK7 end of the D flip-flop 5; A first end of the second switch S2 is connected to the control signal OPS, and a second end of the second switch S2 is connected to the CLK7 end of the D flip-flop 5; The D5 input terminal of the D flip-flop 5 is connected to VDD, the Reset7 terminal of the D flip-flop 5 is connected to the reset signal RD of the calibration logic, and the Q5 output terminal of the D flip-flop 5 is connected to the first input terminal of the second OR gate; The D6 input terminal of the D flip-flop 6 is connected to VDD, the CLK8 terminal of the D flip-flop 6 is connected to the Z output terminal of the 6-bit counter, the Reset8 terminal of the D flip-flop 6 is connected to the reset signal RD of the calibration logic, and the Q6 output terminal of the D flip-flop 6 is connected to the second input terminal of the second OR gate; A first end of the third switch S3 is connected to the control signal OPS, and a second end of the third switch S3 is connected to the CLK9 end of the 6-bit counter; A first end of the fourth switch S4 is connected to the control signal ONS, and a second end of the fourth switch S4 is connected to the CLK9 end of the 6-bit counter; The H input terminal of the 6-bit counter is connected to the output terminal of the second OR gate, the Reset9 terminal of the 6-bit counter is connected to the reset signal RD of the calibration logic, and the Q0-Q5 output terminals of the 6-bit counter are respectively connected to the H0-H5 input terminals of the 6-64 decoder; The output terminals S0-S63 of the 6-64 decoder are connected to the input terminals of the latch array.

6. The dual-mode offset calibration circuit for a comparator applied to a high-speed time-domain interleaved ADC according to claim 5, characterized in that: The circuit structure of the 6-bit counter includes: 3-bit counter 1, 3-bit counter 2, a third NOT gate and a fourth AND gate; wherein, The H1 terminal of the 3-bit counter 1 serves as the H terminal of the 6-bit counter, the Reset10 terminal of the 3-bit counter 1 and the Reset11 terminal of the 3-bit counter 2 serve as the Reset9 terminal of the 6-bit counter, the CLK10 terminal of the 3-bit counter 1 and the CLK11 terminal of the 3-bit counter 2 serve as the CLK9 terminal of the 6-bit counter, the Qa output terminal of the 3-bit counter 1 is connected to the first input terminal of the fourth AND gate and serves as the Q0 output terminal of the 6-bit counter, the Qb output terminal of the 3-bit counter 1 is connected to the second input terminal of the fourth AND gate and serves as the Q1 output terminal of the 6-bit counter, the Qc output terminal of the 3-bit counter 1 is connected to the third input terminal of the fourth AND gate and serves as the Q2 output terminal of the 6-bit counter, and the Z1 output terminal of the 3-bit counter 1 is connected to the input terminal of the third NOT gate; The output end of the third NOT gate is connected to the H2 end of the 3-bit counter 2; The Qd output terminal of the 3-bit counter 2 serves as the Q3 output terminal of the 6-bit counter, the Qe output terminal of the 3-bit counter 2 serves as the Q4 output terminal of the 6-bit counter, the Qf output terminal of the 3-bit counter 1 serves as the Q5 output terminal of the 6-bit counter, the Z2 output terminal of the 3-bit counter 2 is connected to the fourth input terminal of the fourth AND gate, and the output terminal of the fourth AND gate serves as the Z output terminal of the 6-bit counter.

7. The dual-mode offset calibration circuit for a comparator applied to a high-speed time-domain interleaved ADC according to claim 5, characterized in that: The circuit structure of the latch array includes: 64 groups of identical latch modules; the input end of each group of latch modules is respectively connected to the S0~S63 output ends of the 6-64 decoders, and the output end of each group of latch modules corresponds to the output signal S0L~S63L, wherein, Any one of the 64 groups of identical latch modules includes: Switch 1, switch 2, inverter 1 and inverter 2; The first end of the switch 1 is connected to one of the output ends S0 to S63 of the 6-64 decoder, and the second end of the switch 1 is connected to the input end of the inverter 1; The first end of the switch 2 is connected to the second end of the switch 1, and the second end of the switch 2 is connected to the output end of the inverter 2; The output end of the inverter 1 is connected to the input end of the inverter 2; The output terminal of the inverter 2 outputs one of the output signals S0L-S63L correspondingly.

8. The dual-mode offset calibration circuit for a comparator applied to a high-speed time-domain interleaved ADC according to claim 7, characterized in that: The circuit structure of the configurable resistor string includes: MOS tube M9, MOS tube M10, a first resistor, a second resistor, a third resistor, a fourth resistor, a switch 3, a switch 4, a fourth NOT gate and a resistor string; wherein, The source of the MOS tube M9 is grounded, the gate of the MOS tube M9 is connected to the enable signal SEL, and the drain of the MOS tube M9 is connected to the first end of the first resistor; The second end of the first resistor is connected to the first end of the resistor string; A first end of the second resistor is connected to the drain of the MOS tube M9, and a second end of the second resistor is connected to the first end of the switch 3; The second end of the switch 3 is connected to the second end of the first resistor; The resistor string is composed of 64 resistors connected in series, wherein voltages V1 to V63 are sequentially drawn between adjacent resistors, a voltage VL is drawn at the first end of the resistor string, and a voltage VH is drawn at the second end of the resistor string; A first end of the third resistor is connected to the drain of the MOS tube M10, and a second end of the third resistor is connected to the second end of the resistor string; The first end of the fourth resistor is connected to the first end of the third resistor; The first end of the switch 4 is connected to the second end of the resistor string, and the second end of the switch 4 is connected to the second end of the fourth resistor; The source of the MOS tube M10 is connected to VDD, and the gate of the MOS tube M10 is connected to the output end of the fourth NOT gate; An input terminal of the fourth NOT gate is connected to the enable signal SEL.

9. The dual-mode offset calibration circuit for a comparator applied to a high-speed time-domain interleaved ADC according to claim 8, characterized in that: The circuit structure of the switch array includes: 64 switches, switch 5, switch 6, switch 7 and switch 8; among them, The first ends of the 64 switches are respectively connected to the voltages VL-V63, and the second ends of the 64 switches are connected to the first node; The first end of the switch 5 is connected to the voltage VCAL of the first node, and the second end of the switch 5 and the second end of the switch 6 are connected to a second node; The first end of the switch 6 is connected to the voltage VL derived from the first end of the resistor string; The first end of the switch 7 is connected to the voltage VCAL of the first node, and the second end of the switch 7 and the second end of the switch 8 are connected to a third node; The first end of the switch 8 is connected to the voltage VL derived from the first end of the resistor string; The voltage of the second node is used as a calibration terminal voltage VIPC; The voltage of the third node is used as the calibration terminal voltage VINC.

Images