Test vector generation method and device in circuit design

Abstract

The invention provides a test vector generation method and device in circuit design, and the method comprises the steps: obtaining a scanning chain group in the circuit design, the scanning chain group comprises N scanning chains, and each scanning chain in the N scanning chains comprises at least one register; value constraint is carried out on at least one register of each scanning chain in the N scanning chains according to a preset code pattern, the value constraint is used for limiting the value of the at least one register to be 0 or 1, the length of continuous 0 or the length of continuous 1 in the preset code pattern does not exceed Q, and Q is larger than or equal to 1; and according to the register subjected to value constraint, solving to obtain a test vector corresponding to the scan chain group. The method provided by the invention can realize high-precision diagnosis.

Description

Technical Field

[0001] This application relates to the field of integrated circuit testing technology, and particularly relates to a method and device for generating test vectors in circuit design. Background Art

[0002] Chip fault diagnosis tools based on software analysis can utilize test vectors generated by an automatic test pattern generation (ATPG) tool and test results generated by an automatic test equipment (ATE), and with the aid of software algorithms, analyze the failure responses generated during the testing of failed chips, locate the possible positions of faults in the failed chips, and identify fault behaviors.

[0003] Currently, diagnostic tools mainly include two major functions, namely scan chain diagnosis and logic diagnosis, corresponding to the diagnosis when scan chain testing fails and the diagnosis when scan chain testing passes but logic testing fails respectively. In the early stage of chip risk trial production when the yield is relatively low, the proportion of scan chain testing failures among all failed chips exceeds half, and multiple scan chains fail simultaneously mainly. In this case, it is difficult to analyze the specific failure positions of the scan chains. Summary of the Invention

[0004] This application provides a method and device for generating test vectors in circuit design, which can achieve high-precision diagnosis.

[0005] In a first aspect, a method for generating test vectors in circuit design is provided. The method includes: obtaining a scan chain group in the circuit design, where the scan chain group includes N scan chains, each of the N scan chains includes at least one register, and N is an integer greater than or equal to 1; performing value constraints on at least one register of each of the N scan chains according to a preset code pattern, where the value constraints are used to limit the value of the at least one register to 0 or 1, and the length of consecutive 0s or consecutive 1s in the preset code pattern does not exceed Q, and Q≥1; solving to obtain a test vector corresponding to the scan chain group according to the registers after the value constraints.

[0006] This application provides a method for generating test vectors in circuit design, which can generate test vectors according to the preset code pattern of registers, enabling the diagnostic tool to achieve high-precision diagnosis on chips where the original vectors cannot diagnose or the diagnosis does not converge.

[0007] In some possible implementation manners, the multiple at least one register included in the scan chain may be scan units.

[0008] The test vectors generated according to the method provided by this application are expected to diagnose no more than 3 suspicious registers per scan chain on average in the scan chain failure diagnosis scenario, improving the efficiency of chip fault diagnosis.

[0009] It should be understood that the preset pattern can be referred to as an unload pattern, and this unload pattern is composed of 0s and 1s. When Q = 1, the unload pattern can be "01..." or "10...", and "..." represents the cycle of the previous numbers. For example, "01..." is "010101010101......". When Q = 2, the unload pattern can be "01...", "10...", "0011...", "1100...", "1001...", or "0110...". When Q = 3, the unload pattern can be "01...", "10...", "0011...", "1100...", "1001...", "0110...", "000111...", "111000...", "10001...", "01110...", etc.

[0010] It should be understood that the more unload patterns are used, the more test vectors are obtained, and the user can set the number of required unload patterns according to the needs.

[0011] The circuit design includes M test channels, and each test channel corresponds to at least one scan chain. The N scan chains included in the scan chain group can correspond to the same test channel or different test channels. Exemplarily, at least two of the N scan chains correspond to different test channels.

[0012] It should be understood that value constraints are imposed on at least one register of each of the N scan chains according to the preset pattern, including imposing value constraints on at least one register according to the corresponding values in the preset pattern. Exemplarily, N = 3 and the preset pattern is "0011...", the value of the first register in the 3 scan chains can be constrained to 0, or the value of the first register in the 3 scan chains can be constrained to 0, and the value of the fourth register in the 3 scan chains can be constrained to 1.

[0013] In combination with the first aspect, in some implementation manners of the first aspect, the circuit design includes M test channels and the scan chain group, the N scan chains correspond to different test channels among the M test channels, and 1 < N ≤ M.

[0014] In a possible implementation manner, N = M, and the M scan chains correspond one-to-one to the M test channels.

[0015] It should be understood that multiple scan chains corresponding to each channel are interconnected through various combinational logics and sequential logics, and there is little association between scan chains corresponding to different channels. Since the N scan chains in the same scan chain group correspond to different test channels respectively, there is little association between these N scan chains.

[0016] This application provides a method for generating test vectors in circuit design. The N scan chains in the same scan chain group correspond to different test channels respectively, so the generated signals will not be coupled and superimposed on each other, avoiding the problem that it is difficult to locate the failure position of a specific scan chain when multiple scan chains fail simultaneously.

[0017] Combined with the first aspect, in some implementation manners of the first aspect, one or more capture clocks corresponding to the N scan chains can drive the N scan chains to work in parallel.

[0018] It should be understood that one or more capture clocks corresponding to the N scan chains can drive the N scan chains to work in parallel, indicating that the capture clocks corresponding to the N scan chains are compatible with each other, that is, there is no situation where a certain capture clock A is turned on, but the capture clock B cannot be turned on.

[0019] Exemplarily, the scan chains in each test channel among the M test channels of the circuit design can be sorted according to the compatibility of the first capture clock from high to low. The first capture clock is the capture clock with the lowest compatibility among one or more capture clocks corresponding to each scan chain. This compatibility is used to indicate the number of other capture clocks that can be turned on in the circuit design when a certain capture clock is turned on. Then, according to the sorting numbers of the scan chains in the corresponding channels, those with the same sorting number are grouped together. For example, the scan chains with the highest compatibility in the N channels are grouped together. In this way, the capture clocks corresponding to the scan chains in this group have relatively high compatibility, so it is more likely to simultaneously turn on the capture clocks of multiple scan chains in the group, reduce the number of generated test vectors, and improve the efficiency of generating production test vectors.

[0020] This application provides a method for generating test vectors in circuit design. One or more capture clocks corresponding to the N scan chains can drive the N scan chains to work in parallel, improving the efficiency of generating production test vectors.

[0021] Combined with the first aspect, in some implementation manners of the first aspect, Q = 3.

[0022] When Q = 3, the shifted patterns can be "01…", "10…", "0011…", "1100…", "1001…", "0110…", "000111…", "111000…", "10001…", "01110…", etc.

[0023] The present application provides a method for generating test vectors in circuit design. In the preset code pattern, the length of consecutive 0s or consecutive 1s does not exceed 3, which can improve the diagnostic efficiency of chip scan chain faults. For example, for stuck-at faults such as stuck-at 1 and stuck-at 0, the location of the fault can be quickly located.

[0024] In combination with the first aspect, in some implementation manners of the first aspect, the value constraint on at least one register of each scan chain among the N scan chains according to the preset code pattern includes: performing a value constraint on the Kth register of each scan chain among the N scan chains, where the value of the Kth register constraint is the Kth value in the preset code pattern, and K is a positive integer.

[0025] It should be understood that for a specific shift-out code pattern, the value constraints corresponding to the registers on the scan chain are fixed, but the order of adding value constraints is random. K is greater than or equal to 1 and less than or equal to the number of registers included in the corresponding scan chain.

[0026] Exemplarily, the scan chain group is Group 1, and the N scan chains included in Group 1 are chain1, chain4, and chain7. Use the preset code pattern "0011..." to add value constraints to the scan chains chain1, chain4, and chain7 in Group 1. For example, chain1 includes 30 registers, chain4 includes 28 registers, and chain7 includes 25 registers. The value constraints for the first registers of the scan chains chain1, chain4, and chain7 are 0, the value constraints for the second registers are 0, the value constraints for the third registers are 1, the value constraints for the fourth registers are 1, the value constraints for the fifth registers are 0, and so on. During the process of solving the value constraints added to the scan chains chain1, chain4, and chain7, the order of adding value constraints to the registers on the scan chain is random. For example, the constraint with a value of 1 can be first added to the third register of the scan chains chain1, chain4, and chain7, and then the constraint with a value of 0 can be added to the fifth register of the scan chains chain1, chain4, and chain7.

[0027] The present application provides a method for generating test vectors in circuit design, which can randomly select the Kth register in the scan chain group to add value constraints. Compared with the method of solving by adding constraint values to the registers in the group in order, it can achieve a greater range of register matching between the generated test vector code pattern and the preset code pattern, which is beneficial to improving the accuracy of fault location on the scan chain.

[0028] Combined with the first aspect, in some implementations of the first aspect, obtaining the test vector corresponding to the scan chain group by solving the register after value constraint includes: in the case of solving failure, deleting the value constraint on the Kth register; performing value constraint on the Pth register of each of the N scan chains, where the value constrained by the Pth register is the Pth value in the preset code pattern, P is a positive integer and not equal to K; and obtaining the test vector corresponding to the scan chain group by solving.

[0029] P is greater than or equal to 1 and less than or equal to the number of registers included in the corresponding scan chain.

[0030] If the solution is successful, it means that the obtained test vector can make the values of the registers on the scan chains within the group that have been added with value constraints meet the requirements of the preset code pattern. Exemplarily, when the solution is successful for Group 1 with 3 registers (the 1st register, the 4th register, and the 5th register) on each of the scan chains chain1, chain4, and chain7 added with value constraints, the test vector can make the values corresponding to the 1st register, the 5th register, and the 6th register on the scan chains chain1, chain4, and chain7 within Group 1 meet the requirements of the shift-out code pattern "0011...". For example, the code pattern formed by multiple registers on scan chain chain1 is "0XX10XXXXXXXXXXXXXXXXXXXXXXXXX", the code pattern formed by multiple registers on scan chain chain4 is "0XX10XXXXXXXXXXXXXXXXXXXXXXX", and the code pattern formed by multiple registers on scan chain chain7 is "0XX10XXXXXXXXXXXXXXXXXXXX". Where X may be 0 or 1.

[0031] If the solution fails, it means that a set of test vectors cannot be found to make the values of the registers on the scan chains within the group that have been added with value constraints meet the requirements of the preset code pattern. Exemplarily, for the test vector T2 corresponding to Group 1, the shift-out code pattern formed by multiple registers on scan chain chain1 within Group 1 may be "001X0011X0110011X01X0011001100", the shift-out code pattern formed by multiple registers on scan chain chain4 may be "001X0011001X00110X1100X1001X", and the shift-out code pattern formed by multiple registers on scan chain chain7 may be "0X11001X001100X100110011001X", where X represents the bit that does not conform to the preset code pattern value. Then delete the previously added register value constraint and select another register to add value constraint and continue to solve.

[0032] The present application provides a method for generating test vectors in circuit design. In the case of failure in solving, other registers can be selected for value constraint. Compared with the method of adding constraint values to registers in the group in sequence for solving, the code pattern of the generated test vectors can match the preset code pattern in a larger range of registers, which is beneficial to improving the accuracy of fault location on the scan chain.

[0033] In combination with the first aspect, in some implementation manners of the first aspect, obtaining the test vectors corresponding to the scan chain group includes: using an automatic test pattern generation (ATPG) method or a boolean satisfactory (SAT) method to solve and obtain the test vectors corresponding to the scan chain group.

[0034] In a second aspect, a computer device is provided. The device includes: an acquisition module, configured to acquire a scan chain group in circuit design, where the scan chain group includes N scan chains, each of the N scan chains includes at least one register, and N is an integer greater than or equal to 1; a processing module, configured to perform value constraint on at least one register of each of the N scan chains according to a preset code pattern, where the value constraint is used to limit the value of the at least one register to 0 or 1, and the length of consecutive 0s or consecutive 1s in the preset code pattern does not exceed Q, and Q≥1; the processing module is further configured to solve and obtain the test vectors corresponding to the scan chain group according to the registers after the value constraint.

[0035] In combination with the second aspect, in some implementation manners of the second aspect, the circuit design includes M test channels and the scan chain group, the N scan chains correspond to different test channels among the M test channels, and 1<N≤M.

[0036] In combination with the second aspect, in some implementation manners of the second aspect, one or more capture clocks corresponding to the N scan chains can drive the N scan chains to work in parallel.

[0037] In combination with the second aspect, in some implementation manners of the second aspect, Q = 3.

[0038] In combination with the second aspect, in some implementation manners of the second aspect, the processing module is specifically configured to: perform value constraint on the Kth register of each of the N scan chains, and the value of the Kth register after constraint is the Kth value in the preset code pattern, where K is a positive integer.

[0039] In combination with the second aspect, in some implementations of the second aspect, the processing module is specifically configured to: in the case of a solution failure, delete the value constraint on the Kth register; perform value constraint on the Pth register of each of the N scan chains, where the value constrained by the Pth register is the Pth value in the preset code pattern, and P is a positive integer and not equal to K; and solve to obtain the test vector corresponding to the scan chain group.

[0040] In combination with the second aspect, in some implementations of the second aspect, the processing module is specifically configured to solve to obtain the test vector corresponding to the scan chain group by using the ATPG method or the SAT method.

[0041] The beneficial effects of the second aspect and any possible implementation of the second aspect correspond to those of the first aspect and any possible implementation of the first aspect, and thus will not be elaborated herein.

[0042] In a third aspect, an embodiment of the present application provides a computer device, which includes a processor for coupling with a memory, reading and executing instructions and / or program codes in the memory to execute the first aspect or any possible implementation of the first aspect.

[0043] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium storing program codes, which, when the computer-readable storage medium runs on a computer, cause the computer to execute the first aspect or any possible implementation of the first aspect.

[0044] In a fifth aspect, an embodiment of the present application provides a computer program product, which includes computer program codes, which, when the computer program codes run on a computer, cause the computer to execute the first aspect or any possible implementation of the first aspect. Description of the Drawings

[0045] Figure 1 It is a schematic diagram of the proportion of scan chain test failures and logic test failures in samples.

[0046] Figure 2 It is a schematic diagram of the number of problematic scan chains in scan chain test failure samples.

[0047] Figure 3 It is a schematic structural diagram of a circuit design provided by an embodiment of the present application.

[0048] Figure 4 It is an exemplary flowchart of a test vector generation method in a circuit design provided by an embodiment of the present application.

[0049] Figure 5It is an exemplary flowchart of another test vector generation method in the circuit design provided by the embodiments of the present application.

[0050] Figure 6 It is a structural example diagram of a computer device provided by the embodiments of the present application.

[0051] Figure 7 It is a structural example diagram of another computer device provided by the embodiments of the present application.

[0052] Figure 8 It is an example diagram of a computer program product provided by the embodiments of the present application. Detailed implementation manners

[0053] Next, the technical solutions in the embodiments of the present application will be described in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts shall fall within the scope of protection of the present application.

[0054] In the embodiments of the present application, words such as "exemplary" and "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design solution described as "exemplary" in the present application should not be construed as being more preferred or having more advantages than other embodiments or design solutions. Exactly speaking, the use of the word "exemplary" is intended to present concepts in a specific way.

[0055] The business scenarios described in the embodiments of the present application are for more clearly illustrating the technical solutions in the embodiments of the present application, and do not constitute a limitation to the technical solutions provided by the embodiments of the present application. Those of ordinary skill in the art know that with the emergence of new business scenarios, the technical solutions provided by the embodiments of the present application are equally applicable to similar technical problems.

[0056] The reference to "one embodiment" or "some embodiments" etc. described in this specification means that specific features, structures or characteristics described in combination with the embodiment are included in one or more embodiments of the present application. Thus, the statements "in one embodiment", "in some embodiments", "in other some embodiments", "in still other embodiments" etc. appearing in different places in this specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variants all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0057] In this application, "at least one" means one or more, and "a plurality" means two or more. "And / or" describes the relationship between associated objects and indicates that there can be three relationships. For example, A and / or B can mean: including the case where A exists alone, A and B exist simultaneously, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one (item)" or a similar expression refers to any combination of these items, including any combination of a single item or multiple items. For example, at least one of a, b, or c can mean: a, b, c, a - b, a - c, b - c, or a - b - c, where a, b, and c can be single or multiple.

[0058] To facilitate the understanding of the embodiments of this application, some definitions involved in this application are briefly described first.

[0059] 1. Electronic Design Automation (EDA): It refers to a design method that uses computer-aided design software to complete the functional design, synthesis, verification, physical design (including layout, wiring, layout, design rule checking, etc.) of very large-scale integrated circuit chips.

[0060] 2. Automatic Test Pattern Generation (ATPG): ATPG is an important part of the EDA process. Its main function is to generate test vectors that can distinguish the behavior of a correct circuit and a faulty circuit (a circuit with defects) for the input sequence during the test of a digital circuit. The generated vectors can be used to assist in the production test of semiconductor devices or help locate the cause of faults.

[0061] 3. Boolean Satisfiability (SAT): It is used to solve whether there is a set of variable assignments in a given truth equation to make the problem satisfiable. If such an assignment exists, this formula is satisfiable; otherwise, it is unsatisfiable. The Boolean satisfiability problem belongs to the decision problem and is also the first problem proven to be non-deterministic polynomial (NP) complete in polynomial complexity.

[0062] 4. Testable fault: It means that a set of test vectors can be found such that the outputs of a correct circuit and a faulty circuit (a circuit with a fault) are not equal, so that the fault can be identified. Corresponding to SAT, it is the SAT problem, that is, the constructed mathematical model has one or more solutions.

[0063] 5. Unmeasurable Fault: No input can distinguish between the correct and incorrect circuits. Corresponding to SAT, it is an UNSAT problem, that is, the constructed mathematical model has no solution. It should be understood that an unmeasurable fault does not mean that there is no fault.

[0064] 6. Automatic Test Equipment (ATE): A special device used for the automated testing and fault diagnosis of electronic devices. It is widely used in fields such as electronic manufacturing, semiconductor production, circuit board testing and repair. ATE usually consists of hardware and software and is used to perform various test tasks, such as signal measurement, electrical parameter testing, function verification, fault diagnosis, and reliability testing. ATE can conduct comprehensive testing and evaluation on electronic devices, integrated circuits, circuit boards, or other electronic components.

[0065] 7. Test Pattern: A set of input signals used in the testing of chips or electronic devices to detect the functions, performance, and faults of the devices. Test patterns usually consist of a series of logical values, such as 0 and 1. These logical values are applied to the input pins or input interfaces of the device under test in a specific timing and order. The generation of test patterns is based on the test objectives and can cover different test requirements, including functional testing, timing testing, boundary testing, fault mode testing, etc.

[0066] 8. Scan Chain: A technique used for testing and fault diagnosis. It is a data path composed of a series of consecutive registers, forming a ring-shaped or linear chain structure inside the chip. In scan chain testing, the test pattern is loaded into the registers of the scan chain and then transmitted through the scan chain. This way of scan chain transmission can transfer test data between the registers throughout the chip and output the test response data from the scan chain to the output pins of the chip.

[0067] 9. Scan Cell: The basic building block for implementing a scan chain. It is a specially designed register cell used to support chip testing and fault diagnosis. In the normal operation mode, the input and output of the scan cell are connected to the various logic function units of the chip to support the normal functions of the chip. However, in the test mode, through the control signal of the capture clock, the scan cell can switch the connection of the input and output when transmitting the test mode and test response data, guiding the data into the scan chain.

[0068] 10. Capture Clock: A clock signal used to synchronize data capture operations. During data capture, the value of the signal is captured only at the rising or falling edge of a specific moment and stored in a register. This specific moment is controlled by the "capture clock". When the "capture clock" triggers, the value of the input signal is read and transferred to the relevant register.

[0069] 11. Conjunctive Normal Form (CNF): In Boolean logic, if a formula is a conjunction of one or more clauses, which is the sum or "product" of "ands", it is called a conjunctive expression. The propositional connectives that a formula in CNF can contain include "and", "or", and "not". The expressions processed by contemporary SAT solvers are all in CNF form.

[0070] Chip fault diagnosis tools based on software analysis can utilize the test vectors generated by ATPG tools and the test results generated by ATE, and with the help of software algorithms, analyze the failure responses generated by the failing chips during the test process, locate the possible positions where faults may occur in the failing chips, and identify the fault behaviors.

[0071] Accurate fault diagnosis helps to locate the root cause of the fault and improve the production process, which plays a crucial role in quickly increasing the chip yield.

[0072] Currently, diagnostic tools mainly include two major functions, namely scan chain diagnosis and logic diagnosis, corresponding to the diagnosis when the scan chain test fails and the diagnosis when the scan chain test passes but the logic test fails respectively. In the early stage of chip risk trial production when the yield is relatively low, the proportion of scan chain test failures among all failing chips exceeds half, and multiple scan chains fail simultaneously mainly. Figure 1 It is a schematic diagram of the proportion of scan chain test failures and logic test failures in the samples. Among them, the proportion of scan chain test failures is 60%, and the proportion of logic test failures is 40%. Figure 2 It is a schematic diagram of the number of problematic scan chains in the scan chain test failure samples. Among them, the proportion of samples with 1 problematic scan chain is 40%, the proportion of samples with 2 problematic scan chains is 9%, and the proportion of samples with more than 2 problematic scan chains is 51%. Due to multiple scan chains failing simultaneously, the error signals generated are coupled and superimposed on each other, making it difficult to analyze the specific failure positions of the scan chains.

[0073] Figure 3 It is a schematic structural diagram of a circuit design provided by an embodiment of the present application.

[0074] The circuit design includes multiple test channels. Each test channel includes an input channel and an output channel, and multiple scan chains are included between the input channel and the output channel. The circuit starts from the input channel, passes through the test compression structure and is connected to multiple circuits. The multiple circuits are then converged together through the test compression structure and connected to the output channel. These multiple circuits are the scan chains. The scan chain includes multiple consecutive registers, and test vectors are loaded into the registers of the scan chain and then transmitted through the scan chain. In some possible implementation manners, the register may be a scan cell.

[0075] The following takes Figure 3 the three test channels included in the circuit design as an example to illustrate the method provided by this application. Test channel 1 corresponds to scan chains chain1, chain2, and chain3. Test channel 2 corresponds to scan chains chain4, chain5, and chain6. Test channel 3 corresponds to scan chains chain7, chain8, and chain9. The multiple scan chains corresponding to each test channel are mutually related through various combinational logics and sequential logics, such as being mutually related through AND gates, OR gates, NOT gates, XOR gates, or shift registers. There is almost no relationship between the multiple scan chains corresponding to different test channels.

[0076] Figure 4 is an exemplary flowchart of a test vector generation method in a circuit design provided by an embodiment of this application.

[0077] 410. Obtain a scan chain group in the circuit design.

[0078] The scan chain group includes N scan chains, and each scan chain in the N scan chains includes at least one register, where N is an integer greater than or equal to 1. In some possible implementation manners, the at least one register included in the scan chain may be a scan cell.

[0079] 420. Perform value constraint on at least one register of each scan chain in the scan chain group according to a preset code pattern.

[0080] The value constraint is used to limit the value of the at least one register to 0 or 1, and the length of consecutive 0s or the length of consecutive 1s in the preset code pattern does not exceed Q, where Q≥1.

[0081] It should be understood that the preset code pattern can be referred to as an unload code pattern, which is composed of 0s and 1s. When Q = 1, the unload code pattern can be "01..." or "10...", where "..." represents the loop of the previous numbers, such as "01..." being "010101010101...". When Q = 2, the unload code pattern can be "01...", "10...", "0011...", "1100...", "1001..." or "0110...". When Q = 3, the unload code pattern can be "01...", "10...", "0011...", "1100...", "1001...", "0110...", "000111...", "111000...", "10001...", "01110", etc.

[0082] It should be understood that value constraints are imposed on at least one register of each scan chain according to the preset code pattern, including imposing value constraints on at least one register according to the corresponding values in the preset code pattern. Exemplarily, when N = 3 and the preset code pattern is "0011...", the value of the first register in the 3 scan chains can be constrained to 0, or the value of the first register in the 3 scan chains can be constrained to 0 and the value of the fourth register in the 3 scan chains can be constrained to 1.

[0083] 430, and the test vectors corresponding to the scan chain group are obtained by solving.

[0084] Exemplarily, the ATPG method or the SAT method can be used to solve and obtain the test vectors corresponding to the scan chain group.

[0085] The method provided by the embodiments of the present application can pre-generate diagnosis-oriented test vectors before chip testing, can be combined with other test coverage-oriented vectors for testing, and can reduce the complexity of the test process.

[0086] Figure 5 It is an exemplary flowchart of another test vector generation method in circuit design provided by the embodiments of the present application.

[0087] 510, clock compatibility analysis.

[0088] Each scan chain in the circuit design corresponds to one or more capture clocks, and each capture clock is used to control a part of the circuit area. There may be conflicts between different capture clocks. Exemplarily, for five capture clocks A, B, C, D, and E, when clock B is turned on, clock E cannot be turned on, and clocks A, C, and D can be turned on, which means there is a conflict between clock B and clock E, but it can be compatible with clocks A, C, and D, that is, the number of compatible clocks of clock B is 3. According to the above principle, compatibility analysis can be performed on each of the capture clocks corresponding to the scan chain. For example, the number of compatible clocks of each capture clock can be obtained.

[0089] 520, the scan chains in each test channel are sorted in descending order of clock compatibility.

[0090] Each test channel in the circuit corresponds to at least one scan chain, and each scan chain corresponds to one or more capture clocks. The first capture clock is the capture clock with the lowest compatibility among the one or more capture clocks corresponding to each scan chain. Exemplarily, the circuit design includes five capture clocks A, B, C, D, and E. The number of compatible clocks of clock A is 4, the number of compatible clocks of clock B is 3, the number of compatible clocks of clock C is 2, the number of compatible clocks of clock D is 1, and the number of compatible clocks of clock E is 1. Table 1 shows the test channels in the circuit design and the scan chains sorted in descending order of the compatibility of the first capture clock. Scan chains chain1, chain4, and chain7 are controlled by capture clock A, scan chains chain2, chain5, and chain8 are controlled by capture clock B, scan chain chain3 is controlled by capture clocks A and C (only the first capture clock of chain3 is shown in Table 1), scan chain chain6 is controlled by capture clock D, and scan chain chain9 is controlled by capture clock E. The sorting result of the scan chains corresponding to test channel 1 in descending order of the compatibility of the first capture clock is chain1, chain2, and chain3. The sorting result of the scan chains corresponding to test channel 2 in descending order of the compatibility of the first capture clock is chain4, chain5, and chain6. The sorting result of the scan chains corresponding to test channel 3 in descending order of the compatibility of the first capture clock is chain7, chain8, and chain9.

[0091] Table 1

[0092] Test channels of the chip circuit to be tested Scan chain corresponding to the test channel / (First capture clock) Test channel 1 chain1 / (A), chain2 / (B), chain3 / (C) Test channel 2 chain4 / (A), chain5 / (B), chain6 / (D) Test channel 3 chain7 / (A), chain8 / (B), chain9 / (E)

[0093] It should be understood that the 520 step is an optional step. Performing clock compatibility sorting is beneficial to reducing the number of generated test vectors, improving the efficiency of generating production test vectors, and reducing test time and costs. The scan chains within each test channel can be sorted according to other rules or in a random order for the 530 step, and the method provided in this application can still be implemented.

[0094] 530 is to group the scan chains.

[0095] According to the sorting numbers of the scan chains in the corresponding test channels, those with the same sorting number are grouped together. For example, scan chains chain 1, chain4, and chain7 are all in the first position of the corresponding test channel and should be grouped together. Table 2 shows different groups and the scan chains included in each group. Among them, group 1 includes chain 1, chain4, and chain7, group 2 includes chain2, chain5, and chain8, and group 3 includes chain3, chain6, and chain9.

[0096] Table 2

[0097] Group Scan chain / (First capture clock) Group 1 chain1 / (A), chain4 / (A), chain7 / (A) Group 2 chain2 / (B), chain5 / (B), chain8 / (B) Group 3 chain3 / (C), chain6 / (D), chain9 / (E)

[0098] In the embodiments of this application, first, the multiple scan chains corresponding to each test channel are sorted in descending order of the compatibility of the capture clocks, and then the scan chains with the same sorting number are grouped into the same group. Since the scan chains included in group 1 have relatively high clock compatibility, it is more likely to achieve the simultaneous activation of the capture clocks of multiple scan chains within the group, which can reduce the number of generated test vectors, improve the efficiency of generating production test vectors, and reduce test time and costs.

[0099] By generating test vectors dedicated to diagnosis, the accuracy and precision of the analysis by the diagnostic tool can be improved. The test vector generation method provided in the embodiments of this application can generate test vectors for the scan chains belonging to the same group simultaneously before chip testing. The generated test vectors can be combined with other vectors for test coverage for testing, reducing the complexity of the test process.

[0100] Moreover, when different scan chains within the same group belong to different test channels, the generated signals will not be coupled and superimposed on each other, avoiding the problem that it is difficult to locate the specific failure position of the scan chain when multiple scan chains fail simultaneously.

[0101] 540 is further split into multiple groups.

[0102] Scan chains with incompatible capture clocks within a group are further split into multiple groups according to the compatibility of the capture clocks. Exemplarily, when clock C is on, clock D can be on, but clock E cannot be on, that is, clock C and D are compatible, but clock C and E are not compatible. Therefore, the original group 3 can be further split into a new group 3 {chain3, chain6} and a group 4 {chain 9}. Table 3 shows the grouping after further splitting. One or more capture clocks corresponding to the scan chains in each group can drive the scan chains in the group to work in parallel.

[0103] Table 3

[0104] Group Scan chain / (First capture clock) Group 1 chain1 / (A), chain4 / (A), chain7 / (A) Group 2 chain2 / (B), chain5 / (B), chain8 / (B) Group 3 chain3 / (C), chain6 / (D) Group 4 chain9 / (E)

[0105] It should be understood that step 540 is an optional step and is performed when there is a need for further splitting. When there is no need, it can be skipped and the next step can be directly executed.

[0106] 550. Determine whether there is a scan chain grouping for which test vectors are to be generated.

[0107] If there is a scan chain grouping for which test vectors are to be generated, then step 560 is performed on this grouping. If there is no scan chain grouping for which test vectors are to be generated, it means that corresponding test vectors have been generated for all groupings, and the method ends.

[0108] Exemplarily, in the embodiments of the present application, test vectors can be generated in ascending order of the group numbers. If the grouping with the largest group number has generated the corresponding test vectors, it means that corresponding test vectors have been generated for all groupings, and the method ends. Otherwise, it means that the method has not ended, and step 560 is continued. Optionally, the test vectors corresponding to different groupings can also be generated simultaneously using the parallel computing power of a multi-core computer. There is no order of generation and dependency relationship between the test vectors corresponding to multiple groups. The above examples should not be construed as a limitation of the present application.

[0109] 560. Determine whether there is an out pattern to be attempted.

[0110] In some possible implementation manners, the test vectors generated by the method provided in this application can meet a specific unload pattern. The unload pattern consists of 0s and 1s, and the length of consecutive 0s or consecutive 1s does not exceed Q, where Q is a positive integer greater than or equal to 1. Exemplarily, Q = 3, and the unload pattern can be "0011...", "1100...", "1001...", "0110...", "0101...", "1010...", "000111..." or "111000...", etc. The "..." represents the cyclic repetition of the previous numbers. For example, "0011..." is "0011001100110011......". The specific unload pattern provided in the embodiments of this application can improve the diagnostic efficiency of chip scan chain faults. For example, for stuck-at faults such as stuck-at 1 and stuck-at 0, the location of the fault can be quickly located.

[0111] In the embodiments of this application, the unload pattern can be preset for the registers on the scan chain within the same group. Exemplarily, it can be any one or more of "0011...", "1100...", "1001...", "0110...", "0101...", "1010...", "000111...", "111000...".

[0112] In the embodiments of this application, the value constraints can be randomly added to the registers on the scan chain within the selected group one by one according to the preset unload pattern in the order of increasing group numbers. For example, first, the value constraints are randomly added to the registers on the scan chain in group 1 one by one, and then the value constraints are randomly added to the registers on the scan chain in group 2 one by one, and so on. Optionally, the parallel computing ability of a multi-core computer can also be used to add value constraints to the registers on the scan chains of different groups at the same time. The above examples should not be construed as a limitation of this application.

[0113] Exemplarily, the embodiments of this application preset 8 unload patterns, including "0011...", "1100...", "1001...", "0110...", "0101...", "1010...", "000111..." and "111000...". For each pattern, steps 570-591 will be executed, that is, the scan chains within the selected group will add value constraints to the registers according to each pattern.

[0114] If there are unload patterns to be tried, that is, there are still unload patterns in the preset one or more unload patterns that have not been used by the scan chain, then step 570 is executed. If there are no unload patterns to be tried, it means that the scan chains within the selected group have all added value constraints according to all the preset unload patterns, and step 550 is executed.

[0115] 570, Determine whether there is a register in the group that needs to be added with a value constraint.

[0116] If there is a register in the selected group that needs to be added with a value constraint, perform step 580; otherwise, it means that for the specified shift-out pattern, all the registers on the scan chains in the group have been tried to add value constraints, and perform steps 571 and 560.

[0117] 571, Save the test vectors that meet the requirements.

[0118] After all the registers in the group have been tried to add value constraints (including the registers that have been added with value constraints and then deleted), save the test vectors that meet the requirements corresponding to the group. The test vectors can make the values of the registers on the scan chains in the group conform to the preset shift-out pattern. Exemplarily, the test vector T1 corresponding to group 1 can make the shift-out pattern formed by multiple registers on scan chains chain1, chain4, and chain7 in group 1 be "0011...". For example, the shift-out pattern formed by multiple registers on scan chain chain1 is "001100110011001100110011001100", the shift-out pattern formed by multiple registers on scan chain chain4 is "0011001100110011001100110011", and the shift-out pattern formed by multiple registers on scan chain chain7 is "0011001100110011001100110".

[0119] Based on the test vectors obtained for each group, the chip can be subjected to a fault diagnosis test. Exemplarily, the test vectors can be input bit by bit into the input channels of the chip, and the output channels will output corresponding test result vectors according to the test vectors. If a certain bit in the test result vector is different from the corresponding bit value of the preset pattern of this group, the specific location of the chip fault can be located based on this "different bit".

[0120] 580, Randomly add a value constraint to the next register according to the shift-out pattern and solve the vector.

[0121] For a specific shift-out pattern, the value constraints corresponding to the registers on the scan chain are fixed, but the order of adding value constraints is random. Exemplarily, the shift-out pattern "0011..." is used to add value constraints to the Kth register in the scan chain within Group 1, where K is a positive integer, chain1 includes 30 registers, chain4 includes 28 registers, and chain7 includes 25 registers. The value constraints for the first register in scan chains chain1, chain4, and chain7 are 0, the value constraints for the second register are 0, the value constraints for the third register are 1, the value constraints for the fourth register are 1, the value constraints for the fifth register are 0, and so on. During the process of adding value constraints to solve for scan chains chain1, chain4, and chain7, the order of adding value constraints to the registers on the scan chain is random. For example, the constraint with a value of 1 can be first added to the third register in scan chains chain1, chain4, and chain7, and then the constraint with a value of 0 can be added to the fifth register in scan chains chain1, chain4, and chain7. In the embodiments of the present application, the method of randomly selecting registers within a group to add value constraints for solving can achieve a greater range of register matching between the generated test vector pattern and the preset pattern compared to the method of adding constraint values to the registers within the group in order, which is beneficial to improving the accuracy of fault location on the scan chain. It should be understood that other orders of adding constraints to the registers can also implement this step.

[0122] Exemplarily, if the solution fails after adding a constraint with a value of 0 or 1 to the Kth register in scan chains chain1, chain4, and chain7 within Group 1 last time, after deleting the value constraint on the Kth register in this group, a constraint can be randomly added to the next register that has not been added with a value constraint. For example, a constraint with a value of 0 or 1 can be added to the Pth register in scan chains chain1, chain4, and chain7 within Group 1, where P is a positive integer and not equal to K.

[0123] For each additional register value constraint, test vectors can be solved using the ATPG method or the SAT method. The ATPG method continuously determines the states that circuit nodes (nets) should have in the circuit. Therefore, in some cases, it may face the situation that the current required state of the circuit is not unique, which means that decisions need to be made to determine the state of the circuit. According to the locations where the decisions occur, there are currently two main types of ATPG methods. One is represented by the D-algorithm. The characteristic of this type of algorithm is to make decisions at the logical value requirements (where the decisions occur). The other is represented by the path oriented decision making (PODEM). This type of algorithm traces the requirements back to the primary inputs (PIs) and makes decisions at the PIs. The SAT method usually needs to first convert the circuit into a Boolean expression in CNF. In the CNF expression, variables and their negations are both called literals. Different literals are connected by logical symbols such as AND, OR, and NOT to form clauses, and then a SAT solver is used to solve the CNF.

[0124] 590, Solved successfully?

[0125] If the solution is successful, it means that the obtained test vector can make the values of the registers with value constraints added on the scan chains within the group meet the requirements of the preset pattern, and step 570 is executed. Exemplarily, when the solution is successful for the test vector corresponding to 3 registers (the 1st register, the 4th register, and the 5th register) with value constraints added in scan chains chain1, chain4, and chain7 in group 1, it can make the values corresponding to the 1st register, the 5th register, and the 6th register on scan chains chain1, chain4, and chain7 within group 1 meet the requirements of the shifted-out pattern "0011…". For example, the pattern formed by multiple registers on scan chain chain1 is "0XX10XXXXXXXXXXXXXXXXXXXXXXXXX", the pattern formed by multiple registers on scan chain chain4 is "0XX10XXXXXXXXXXXXXXXXXXXXXXX", and the pattern formed by multiple registers on scan chain chain7 is "0XX10XXXXXXXXXXXXXXXXXXXX". Here, X can be either 0 or 1.

[0126] If the solution fails, it means that no set of test vectors can be found to make the values of the registers with value constraints added on the scan chains within the group meet the requirements of the preset pattern, and step 591 is executed.

[0127] 591, Delete the last added register constraint.

[0128] Exemplarily, the test vector T2 corresponding to Group 1 may cause the shift-out pattern formed by multiple registers on scan chain chain1 in Group 1 to be "001X0011X0110011X01X0011001100", the shift-out pattern formed by multiple registers on scan chain chain4 to be "001X0011001X00110X1100X1001X", and the shift-out pattern formed by multiple registers on scan chain chain7 to be "0X11001X001100X100110011001X", where X represents a bit that does not conform to the preset pattern value.

[0129] Performing the step of deleting the register constraint of 591 means that the shift-out value constraint on some registers is cancelled during the solving process. Exemplarily, if the last added register constraint is that the value constraint of the third register of scan chains chain1, chain4, and chain7 is 1, then the value constraint of the third register of scan chains chain1, chain4, and chain7 is deleted, and the process returns to execute step 570.

[0130] The test vector generation method provided by this application can generate test vectors according to the preset patterns of registers, enabling the diagnostic tool to achieve high-precision diagnosis on chips where the original vectors cannot diagnose or the diagnosis does not converge.

[0131] The above describes the test vector generation method according to the embodiments of this application. The implementation of this method can be an application program running on a computer, and the test vectors generated by this application program can make the registers on the scan chain conform to the preset shift-out patterns.

[0132] The following will separately combine Figure 6 and Figure 7 to describe the device and equipment according to the embodiments of this application.

[0133] The embodiments of this application also provide a computer storage medium, in which program instructions are stored. When the program is executed, it may include some or all of the steps of the test vector generation method in the corresponding embodiments such as Figure 4 and Figure 5

[0134] Figure 6 This is a structural example diagram of a computer device 1000 provided by the embodiments of this application. The computer device 1000 includes an acquisition module 1010 and a processing module 1020. The acquisition module 1010 and the processing module 1020 can be implemented by software, hardware, or a combination of both. Therefore, the computer device 1000 can be a computer simulation tool for implementing test vector generation, such as an EDA software tool or a related module or device installed with the tool.

[0135] Among them, the obtaining module 1010 is configured to obtain a scan chain group in a circuit design. The scan chain group includes N scan chains, and each of the N scan chains includes at least one register to execute Figure 4 410 in the method.

[0136] The processing module 1020 is configured to perform value constraint and solution on at least one register of each of the N scan chains according to a preset code pattern, and execute Figure 4 and Figure 5 some or all of the steps in the method of.

[0137] Figure 7 FIG. 13 is a structural example diagram of another computer device 1300 provided in an embodiment of the present application. The computer device 1300 includes a processor 1302, a communication interface 1303, and a memory 1304. An example of the computer device 1300 is a computing device, such as a server for performing EDA simulation.

[0138] The method disclosed in the above embodiments of the present application can be applied to the processor 1302 or implemented by the processor 1302. The processor 1302 may be a central processing unit (CPU), or may also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor, etc. In the implementation process, each step of the above method may be completed by an integrated logic circuit in the hardware of the processor 1302 or an instruction in the form of software. The various methods, steps, and logic block diagrams disclosed in the embodiments of the present application may be implemented or executed. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc. The steps of the method disclosed in combination with the embodiments of the present application may be directly embodied as being executed and completed by a hardware decoding processor, or executed and completed by a combination of hardware and software modules in the decoding processor.

[0139] The memory 1304 can be a volatile memory, a non-volatile memory, or can include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM), or a flash memory. The volatile memory can be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchlink DRAM (SLDRAM), and direct rambus RAM (DRRAM). It should be noted that the memory of the methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0140] Communication can occur between the processor 1302, the memory 1304, and the communication interface 1303 via a bus. Executable code is stored in the memory 1304, and the processor 1302 reads the executable code in the memory 1304 to execute the corresponding method. The memory 1304 can also include software modules such as an operating system required for other running processes. The operating system can be LINUX TM , UNIX TM , WINDOWS TM and so on.

[0141] For example, the executable code in the memory 1304 is used to implement Figure 4 and Figure 5 the methods shown. The processor 1302 reads the executable code in the memory 1304 to execute Figure 4 and Figure 5 the methods shown.

[0142] In some embodiments of the present application, the disclosed method may be implemented as computer program instructions encoded in a machine-readable format on a computer-readable storage medium or encoded on other non-transitory media or articles. Figure 8 A conceptual partial view of an example computer program product arranged in accordance with at least some of the embodiments presented herein is schematically shown, the example computer program product including a computer program for performing a computer process on a computing device. In one embodiment, the example computer program product 1400 is provided using a signal-bearing medium 1401. The signal-bearing medium 1401 may include one or more program instructions 1402 which, when run by one or more processors, may provide the functions or portions of the functions described above for Figure 4 and Figure 5 the methods described as shown. Thus, for example, referring to the embodiments shown in Figure 4 and Figure 5 , one or more of the features therein may be carried out by one or more instructions associated with the signal-bearing medium 1401.

[0143] In some examples, the signal-bearing medium 1401 may include a computer-readable medium 1403, such as but not limited to, a hard disk drive, a compact disc (CD), a digital video disc (DVD), a digital tape, a memory, a read-only memory (ROM), or a random access memory (RAM), and so on. In some embodiments, the signal-bearing medium 1401 may include a computer-recordable medium 1404, such as but not limited to, a memory, a read / write (R / W) CD, an R / W DVD, and so on. In some embodiments, the signal-bearing medium 1401 may include a communication medium 1405, such as but not limited to, a digital and / or analog communication medium (e.g., an optical fiber cable, a waveguide, a wired communication link, a wireless communication link, and so on). Thus, for example, the signal-bearing medium 1401 may be conveyed by a wireless form of the communication medium 1405 (e.g., a wireless communication medium compliant with the IEEE 802.11 standard or other transmission protocols). One or more program instructions 1402 may be, for example, computer-executable instructions or logic implementation instructions. In some examples, the foregoing computing device may be configured to provide various operations, functions, or actions in response to the program instructions 1402 communicated to the computing device via one or more of the computer-readable medium 1403, the computer-recordable medium 1404, and / or the communication medium 1405. It should be understood that the arrangements described herein are for illustrative purposes only. Thus, those skilled in the art will understand that other arrangements and other elements (e.g., machines, interfaces, functions, sequences, and groups of functions, etc.) can be used instead, and some elements may be omitted altogether depending on the desired results. Additionally, many of the elements described can be implemented as discrete or distributed components, or as functional entities combined with other components in any suitable combination and location.

[0144] Those of ordinary skill in the art can realize that the units and method steps of each example described in conjunction with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0145] Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the devices and units described above can refer to the corresponding processes in the foregoing method embodiments and will not be elaborated herein.

[0146] In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some interfaces. The indirect couplings or communication connections of the devices or units can be in electrical, mechanical or other forms.

[0147] The units described as separate components may or may not be physically separated. The components displayed as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0148] In addition, in each embodiment of the present application, the functional units can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit.

[0149] If the functions are implemented in the form of software function units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in each embodiment of the present application. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical discs that can store program codes.

[0150] The above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed in the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A test vector generation method in circuit design, It is characterized in that The method comprises: Acquire a scan chain group in a circuit design, the scan chain group comprising N scan chains, each of the N scan chains comprising at least one register, and N is an integer greater than or equal to 1; Performing a value constraint on at least one register of each of the N scan chains according to a preset code pattern, wherein the value constraint is used to limit the value of the at least one register to 0 or 1, and the length of consecutive 0s or consecutive 1s in the preset code pattern does not exceed Q, and Q ≥ 1; The test vector corresponding to the scan chain group is obtained by solving the register after the value constraint.

2. The method according to claim 1, It is characterized in that The circuit design includes M test channels and the scan chain group, the N scan chains correspond to different test channels among the M test channels, 1<N≤M.

3. The method according to claim 1 or 2, It is characterized in that The one or more capture clocks corresponding to the N scan chains can drive the N scan chains to work in parallel.

4. The method according to any one of claims 1 to 3, It is characterized in that Q＝3。 5. The method according to any one of claims 1 to 4, It is characterized in that The constraining the value of at least one register of each of the N scan chains according to a preset code pattern comprises: A value constraint is performed on the Kth register of each of the N scan chains, where the value constrained by the Kth register is the Kth value in the preset code pattern, and K is a positive integer.

6. The method according to claim 5, It is characterized in that The step of obtaining the test vector corresponding to the scan chain group by solving the register after the value constraint includes: In case of a solution failure, deleting the value constraint on the K-th register; Performing a value constraint on a P-th register of each of the N scan chains, where the value constrained by the P-th register is the P-th value in the preset code pattern, where P is a positive integer and is not equal to K; The test vector corresponding to the scan chain group is obtained by solving.

7. The method according to any one of claims 1 to 6, It is characterized in that The solving to obtain the test vector corresponding to the scan chain group includes: The test vector corresponding to the scan chain group is obtained by using an automatic test vector generation ATPG method or a Boolean satisfiability SAT method.

8. A computer device, It is characterized in that include: An acquisition module, used to acquire a scan chain group in a circuit design, wherein the scan chain group includes N scan chains, each of the N scan chains includes at least one register, and N is an integer greater than or equal to 1; a processing module, configured to perform a value constraint on at least one register of each of the N scan chains according to a preset code pattern, wherein the value constraint is used to limit the value of the at least one register to 0 or 1, and the length of consecutive 0s or consecutive 1s in the preset code pattern does not exceed Q, where Q ≥ 1; The processing module is further used to solve the test vector corresponding to the scan chain group according to the register after the value constraint.

9. The device according to claim 8, It is characterized in that The circuit design includes M test channels and the scan chain group, the N scan chains correspond to different test channels among the M test channels, 1<N≤M.

10. The device according to claim 8 or 9, It is characterized in that The one or more capture clocks corresponding to the N scan chains can drive the N scan chains to work in parallel.

11. The device according to any one of claims 8 to 10, It is characterized in that Q＝3。 12. The device according to any one of claims 8 to 11, It is characterized in that The processing module is specifically used for: A value constraint is performed on the Kth register of each of the N scan chains, where the value constrained by the Kth register is the Kth value in the preset code pattern, and K is a positive integer.

13. The device according to claim 12, It is characterized in that The processing module is specifically used for: In case of a solution failure, deleting the value constraint on the K-th register; Performing a value constraint on a P-th register of each of the N scan chains, where the value constrained by the P-th register is the P-th value in the preset code pattern, where P is a positive integer and is not equal to K; The test vector corresponding to the scan chain group is obtained by solving.

14. The device according to any one of claims 8 to 13, It is characterized in that The processing module is specifically used to use an automatic test vector generation ATPG method or a Boolean satisfiability SAT method to solve and obtain the test vector corresponding to the scan chain group.

15. A computer device, It is characterized in that include: A processor, wherein the processor is used to be coupled to a memory, read and execute instructions and / or program codes in the memory, so as to perform the method according to any one of claims 1 to 7.

16. A computer readable medium, It is characterized in that The computer-readable medium stores a computer program code, and when the computer program code is executed on a computer, the computer is caused to execute the method according to any one of claims 1 to 7.

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