Laminated pixel detector with expanded dynamic range
By connecting the pixel detector to the external capacitor array chip, the problem of dynamic range expansion of the pixel detector is solved, and a larger input dynamic range and more efficient use of the readout circuit space is achieved.
Patent Information
- Application Number
- CN202510196448.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-21
- Publication Date
- 2025-05-27
AI Technical Summary
The dynamic range of existing pixel detectors is difficult to expand because the capacitance value of the charge integration capacitor Cf in the pixel is limited by the pixel area.
Through packaging methods such as flip welding and through-silicon holes, the pixel detector is connected to the external capacitor array sheet, and the optoelectrons generated by the sensor are stored on the external capacitor array sheet, thereby expanding the dynamic range of pixel input.
The effective increase of pixel integration capacitor is achieved, the dynamic range of pixels is expanded, and the area of the readout circuit is saved, so that the readout circuit can realize more circuit functions.
Smart Images
Figure CN120051021A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of pixel detector readout chips and relates to a stacked pixel detector with extended dynamic range. Background Art
[0002] Pixel detectors are widely used in various imaging devices. According to whether the sensor and the readout circuit are on the same substrate, they can be divided into monolithic and hybrid types. As shown in Figure 1 , in a monolithic pixel detector, the sensor and the readout circuit are on the same substrate. As shown in Figure 2 , in a hybrid pixel detector, the sensor and the readout circuit are on two different substrates, and they are connected by flip-chip bonding.
[0003] Whether it is a monolithic pixel detector or a hybrid pixel detector, the dynamic range (or full well capacity) of its pixels is determined by the charge integration capacitor C f in the pixel. The larger the capacitance value of C f , the larger the dynamic range of the pixel. C f and the readout circuit are in the same pixel on the same substrate, and its capacitance value is limited by the pixel area. Therefore, it is difficult to further expand the dynamic range of the pixel. Summary of the Invention
[0004] Aiming at the problems existing in the prior art, the purpose of the present invention is to provide a stacked pixel detector with extended dynamic range. Through packaging methods such as flip-chip bonding and through-silicon vias, each pixel of the pixel detector is connected to an external capacitor array chip, and the photoelectrons generated by the sensor are stored in the external capacitor array chip, so as to achieve the purpose of expanding the input dynamic range of the pixel. Compared with the traditional pixel detector, its integration capacitor is not limited by the pixel size of the readout circuit, and it can realize the integration and readout of more photoelectrons, thereby achieving a larger input dynamic range.
[0005] The key of this patent lies in the independent capacitor array chip. Figure 3 shows a stacked structure for extending the dynamic range based on a monolithic pixel detector. An independent capacitor array chip is connected to the pixel array by flip-chip bonding. Since the entire capacitor array chip is a capacitor structure, the capacitance value of C f can be much larger than the capacitor in the original readout circuit structure, so the dynamic range of the pixel detector is effectively improved.
[0006] Figure 4A stacked structure for dynamic range extension based on a hybrid pixel detector is presented. In this structure, the capacitor array chip is located between the sensor and the readout circuit. Similar to the monolithic type, the independent capacitor array chip is connected to the readout circuit by flip-chip bonding. To ensure the connectivity between the sensor and the readout circuit, through-silicon vias need to be implemented on the capacitor array chip, and the sensor is connected to the readout circuit via flip-chip bonding and through-silicon vias.
[0007] Another stacked structure for dynamic range extension based on a hybrid pixel detector is as Figure 5 shown. In this stacked structure, the readout circuit is located between the sensor and the capacitor array chip, and the sensor is connected to the readout circuit via flip-chip bonding and through-silicon vias. Both stacked structures can effectively expand the capacitance value of the pixel integration capacitor, thereby expanding the dynamic range of the detector.
[0008] The technical solution of the present invention is as follows:
[0009] A stacked pixel detector with extended dynamic range includes a pixel array, and each pixel in the pixel array includes a sensor and a readout circuit; characterized in that the integration capacitors of each readout circuit are arranged on an external substrate to form an external capacitor array chip for storing the photoelectrons generated by each sensor.
[0010] Further, the capacitor array chip is connected to the readout circuit in the pixel array by a flip-chip packaging method; wherein, the i-th integration capacitor in the capacitor array chip is connected to the readout circuit of the i-th pixel in the pixel array, and the readout circuit of the i-th pixel is used to read the photoelectrons generated by the sensor of the i-th pixel and store them in the i-th integration capacitor.
[0011] Further, a plurality of vias are provided on the capacitor array chip, and the sensor array is connected to the readout circuit array through the vias; each integration capacitor on the capacitor array chip is connected to a corresponding readout circuit in the pixel array by flip-chip bonding; wherein, the i-th integration capacitor in the capacitor array chip is connected to the readout circuit of the i-th pixel in the pixel array, and the readout circuit of the i-th pixel is used to read the photoelectrons generated by the sensor of the i-th pixel and store them in the i-th integration capacitor.
[0012] Further, a plurality of vias are provided on the capacitor array chip; the sensors of each pixel are disposed on a substrate to form a sensor array, and the readout circuits of each pixel are disposed on a substrate to form a readout circuit array; the capacitor array chip is located between the sensor array and the readout circuit array. One end of each via on the capacitor array chip is connected to the sensor array by a flip-chip packaging method, and the other end of each via on the capacitor array chip and each integrating capacitor are connected to the readout circuit array by a flip-chip packaging method; wherein, the i-th sensor in the sensor array is connected to the i-th readout circuit in the readout circuit array through the i-th via on the capacitor array chip, and the i-th integrating capacitor in the capacitor array chip is connected to the i-th readout circuit in the readout circuit array. The i-th readout circuit is configured to read the photoelectrons generated by the i-th sensor and store them in the i-th integrating capacitor.
[0013] Further, the sensors of each pixel are disposed on a substrate to form a sensor array, and the readout circuits of each pixel are disposed on a substrate to form a readout circuit array. A plurality of vias are provided on the readout circuit array, and the i-th via is connected to the i-th readout circuit in the readout circuit array; the readout circuit array is located between the sensor array and the capacitor array chip. One end of each via on the readout circuit array is connected to the sensor array by a flip-chip packaging method, and each integrating capacitor on the capacitor array chip is connected to the readout circuit array by a flip-chip packaging method; wherein, the i-th readout circuit in the readout circuit array is connected to the i-th sensor in the sensor array through the i-th via for reading the photoelectrons generated by the i-th sensor; the i-th integrating capacitor in the capacitor array chip is connected to the i-th readout circuit in the readout circuit array for storing the photoelectrons read by the i-th readout circuit.
[0014] Further, N parallel integrating capacitors are externally provided for each readout circuit as an integrating capacitor group corresponding to the readout circuit. The n-th integrating capacitor of each readout circuit is disposed on the n-th externally disposed substrate to form the n-th externally disposed capacitor array chip, where n = 1 to N, and a total of N capacitor array chips are formed; the capacitor array chips are stacked. Except for the top-layer capacitor array chip, a plurality of pairs of capacitor connection holes are provided on the remaining N - 1 capacitor array chips. Both ends of each integrating capacitor on the N - 1 capacitor array chips are connected to a pair of capacitor connection holes on the capacitor array chip where the integrating capacitor is located. Adjacent capacitor array chips are connected by a flip-chip packaging method, and the two integrating capacitors of the i-th readout circuit on adjacent two-layer capacitor array chips are connected in parallel through a pair of corresponding capacitor connection holes; the bottom-layer capacitor array chip is connected to the readout circuit in the pixel array by a flip-chip packaging method; wherein, the readout circuit of the i-th pixel is configured to read the photoelectrons generated by the sensor of the i-th pixel and store them in the integrating capacitor group corresponding to the i-th pixel.
[0015] Further, the sensors of each pixel are disposed on a substrate to form a sensor array, and the readout circuits of each pixel are disposed on a substrate to form a readout circuit array; N parallel integrating capacitors are externally disposed for each readout circuit as the integrating capacitor group corresponding to the readout circuit. The nth integrating capacitor of each readout circuit is disposed on the nth externally disposed substrate to form the nth externally disposed capacitor array sheet, where n = 1 to N, and a total of N capacitor array sheets are formed; the capacitor array sheets are stacked. Each of the capacitor array sheets is provided with a plurality of first vias. Except for the top-layer capacitor array sheet, the remaining N - 1 capacitor array sheets are each provided with multiple pairs of capacitor connection holes. Both ends of each integrating capacitor on the N - 1 capacitor array sheets are connected to a pair of capacitor connection holes on the capacitor array sheet where the integrating capacitor is located. Adjacent capacitor array sheets are connected by a flip-chip packaging method. The two integrating capacitors of the ith readout circuit on adjacent two-layer capacitor array sheets are connected in parallel through a pair of corresponding capacitor connection holes; the bottom-layer capacitor array sheet is connected to the readout circuit array by a flip-chip packaging method, and the sensor array is connected to the top-layer capacitor array sheet by a flip-chip packaging method; wherein, the ith readout circuit in the readout circuit array is sequentially connected to the ith sensor in the sensor array through the ith first via on each layer of the capacitor array sheets, for reading the photoelectrons generated by the sensor corresponding to the ith pixel and storing them into the integrating capacitor group corresponding to the ith pixel.
[0016] Further, the sensors of each pixel are disposed on a substrate to form a sensor array, and the readout circuits of each pixel are disposed on a substrate to form a readout circuit array; N parallel integrating capacitors are externally disposed for each readout circuit as the integrating capacitor group corresponding to the readout circuit. The nth integrating capacitor of each readout circuit is disposed on the nth externally disposed substrate to form the nth externally disposed capacitor array sheet, where n = 1 to N, and a total of N capacitor array sheets are formed; the readout circuit array is provided with a plurality of first vias. Each readout circuit is connected to a first via. The capacitor array sheets are stacked. Except for the top-layer capacitor array sheet, the remaining N - 1 capacitor array sheets are each provided with multiple pairs of capacitor connection holes. Both ends of each integrating capacitor on the N - 1 capacitor array sheets are connected to a pair of capacitor connection holes on the capacitor array sheet where the integrating capacitor is located. Adjacent capacitor array sheets are connected by a flip-chip packaging method. The two integrating capacitors of the ith readout circuit on adjacent two-layer capacitor array sheets are connected in parallel through a pair of corresponding capacitor connection holes; the top-layer capacitor array sheet is connected to the readout circuit array by a flip-chip packaging method, and the sensor array is connected to the readout circuit array by a flip-chip packaging method; wherein, the ith readout circuit in the readout circuit array is connected to the ith sensor in the sensor array through the ith first via, for reading the photoelectrons generated by the sensor corresponding to the ith pixel and storing them into the integrating capacitor group corresponding to the ith pixel.
[0017] The advantages of the present invention are as follows:
[0018] By means of an external capacitor array chip, the present invention effectively expands the size of the pixel integration capacitor. Its beneficial effects are mainly reflected in the following aspects.
[0019] 1. Expansion of pixel dynamic range
[0020] By adding a stacked structure of an independent capacitor array chip, the present invention realizes an effective increase in the pixel integration capacitor, and thus effectively expands the pixel dynamic range.
[0021] 2. Improvement of the available space of the readout circuit
[0022] The structure proposed by the present invention transfers the integration capacitor outside the readout circuit, thereby saving the area of the readout circuit. Without increasing the pixel size, more circuit functions can be realized within the pixel of the readout circuit. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] Figure 1 It is a schematic diagram of the structure of a traditional monolithic pixel detector.
[0024] Figure 2 It is a schematic diagram of the stacked structure of a traditional hybrid pixel detector.
[0025] Figure 3 It is a stacked structure diagram of the monolithic pixel detector proposed in this patent.
[0026] Figure 4 It is a stacked structure diagram of the first hybrid pixel detector proposed in this patent.
[0027] Figure 5 It is a stacked structure diagram of the second hybrid pixel detector proposed in this patent.
[0028] Figure 6 It is a multi-layer capacitor array expansion structure diagram of the stacked structure of the monolithic pixel detector proposed in this patent.
[0029] Figure 7 It is a multi-layer capacitor array expansion structure diagram of the first pixel detector stacked structure proposed in this patent.
[0030] Figure 8 It is a multi-layer capacitor array expansion structure diagram of the second pixel detector stacked structure proposed in this patent. DETAILED DESCRIPTION OF THE INVENTION
[0031] The present invention will be further described in detail below with reference to the accompanying drawings. The examples given are only used to explain the present invention and are not intended to limit the scope of the present invention.
[0032] A stacked dynamic range expansion structure proposed in this patent. The key point lies in an independent capacitor array chip, which is connected to the readout circuit through packaging technologies such as flip-chip bonding and through-silicon vias. The number of capacitor array chips is not limited to a single layer. As Figures 6 to 8 shown, the expansion of multi-layer circuit array chips still falls within the protection scope of the technical solution of the present invention.
[0033] As Figure 6 shown, there are N parallel integrated capacitors outside each readout circuit as the integrated capacitor group corresponding to the readout circuit. The nth integrated capacitor of each readout circuit is arranged on the nth external substrate to form the nth external capacitor array chip, where n = 1 to N, and a total of N capacitor array chips are formed; the capacitor array chips are stacked. Except for the top-layer capacitor array chip, there are multiple pairs of capacitor connection holes on the remaining N - 1 capacitor array chips. Both ends of each integrated capacitor on the N - 1 capacitor array chips are connected to a pair of capacitor connection holes on the capacitor array chip where the integrated capacitor is located. Adjacent capacitor array chips are connected through the flip-chip bonding packaging method. The two integrated capacitors of the ith readout circuit on adjacent two-layer capacitor array chips are connected in parallel through a pair of corresponding integrated capacitor connection holes; the bottom-layer capacitor array chip is connected to the readout circuit in the pixel array through the flip-chip bonding packaging method; among them, the readout circuit of the ith pixel is used to read the photoelectrons generated by the sensor of the ith pixel and store them in the integrated capacitor group corresponding to the ith pixel.
[0034] As Figure 7 shown, the sensors of each pixel are arranged on a substrate to form a sensor array, and the readout circuits of each pixel are arranged on a substrate to form a readout circuit array; there are N parallel integrated capacitors outside each readout circuit as the integrated capacitor group corresponding to the readout circuit. The nth integrated capacitor of each readout circuit is arranged on the nth external substrate to form the nth external capacitor array chip, where n = 1 to N, and a total of N capacitor array chips are formed; the capacitor array chips are stacked. Each capacitor array chip is provided with multiple first through-holes. Except for the top-layer capacitor array chip, there are multiple pairs of capacitor connection holes on the remaining N - 1 capacitor array chips. Both ends of each integrated capacitor on the N - 1 capacitor array chips are connected to a pair of capacitor connection holes on the capacitor array chip where the integrated capacitor is located. Adjacent capacitor array chips are connected through the flip-chip bonding packaging method. The two integrated capacitors of the ith readout circuit on adjacent two-layer capacitor array chips are connected in parallel through a pair of corresponding capacitor connection holes; the bottom-layer capacitor array chip is connected to the readout circuit array through the flip-chip bonding packaging method, and the sensor array is connected to the top-layer capacitor array chip through the flip-chip bonding packaging method; among them, the ith readout circuit in the readout circuit array is sequentially connected to the ith sensor in the sensor array through the ith first through-hole on each layer of the capacitor array chips, and is used to read the photoelectrons generated by the sensor corresponding to the ith pixel and store them in the integrated capacitor group corresponding to the ith pixel.
[0035] As shown Figure 8 in the figure, the sensors of each pixel are arranged on a substrate to form a sensor array, and the readout circuits of each pixel are arranged on a substrate to form a readout circuit array; N parallel integration capacitors are externally arranged for each readout circuit as the integration capacitor group corresponding to the readout circuit. The nth integration capacitor of each readout circuit is arranged on the nth externally arranged substrate to form the nth externally arranged capacitor array sheet, where n = 1 to N, and a total of N capacitor array sheets are formed; a plurality of first vias are provided on the readout circuit array, and each readout circuit is connected to a first via. The capacitor array sheets are stacked. Except for the top-layer capacitor array sheet, multiple pairs of capacitor connection holes are provided on the remaining N - 1 capacitor array sheets. The two ends of each integration capacitor on the N - 1 capacitor array sheets are connected to a pair of capacitor connection holes on the capacitor array sheet where the integration capacitor is located. Adjacent capacitor array sheets are connected by a flip-chip packaging method. The two integration capacitors of the ith readout circuit on adjacent two-layer capacitor array sheets are connected in parallel through a pair of corresponding capacitor connection holes; the top-layer capacitor array sheet is connected to the readout circuit array by a flip-chip packaging method, and the sensor array is connected to the readout circuit array by a flip-chip packaging method; wherein, the ith readout circuit in the readout circuit array is connected to the ith sensor in the sensor array through the ith first via, and is used to read the photoelectrons generated by the sensor corresponding to the ith pixel and store them in the integration capacitor group corresponding to the ith pixel.
[0036] There can be various different implementation forms for the types of sensors, readout circuits, and integration capacitors in the capacitor array sheets. Based on the patent solution of the present invention, the replacement of specific components still falls within the protection scope of the technical solution of the present invention.
[0037] Although specific embodiments of the present invention are disclosed for illustrative purposes, which are intended to help understand the content of the present invention and implement it accordingly, those skilled in the art can understand that: within the spirit and scope of the present invention and the appended claims, various replacements, changes, and modifications are possible. Therefore, the present invention should not be limited to the content disclosed in the best embodiments, and the scope of protection required by the present invention is defined by the scope defined in the claims.
Claims
1. A stacked dynamic range extended pixel detector, comprising a pixel array, wherein each pixel in the pixel array comprises a sensor and a readout circuit; characterized in that: The integrating capacitor of each of the readout circuits is arranged on an external substrate to form an external capacitor array sheet for storing the photoelectrons generated by each of the sensors.
2. The pixel detector according to claim 1, characterized in that The capacitor array sheet is connected to the readout circuit in the pixel array through a flip-chip packaging method; wherein the i-th integrating capacitor in the capacitor array sheet is connected to the readout circuit of the i-th pixel in the pixel array, and the readout circuit of the i-th pixel is used to read the photoelectrons generated by the sensor of the i-th pixel and store them in the i-th integrating capacitor.
3. The pixel detector according to claim 1, characterized in that: The capacitor array sheet is provided with a plurality of through holes, and the sensor array is connected to the readout circuit array through the through holes; each integrating capacitor on the capacitor array sheet is connected to a corresponding readout circuit in the pixel array through flip-chip welding; wherein the i-th integrating capacitor in the capacitor array sheet is connected to the readout circuit of the i-th pixel in the pixel array, and the readout circuit of the i-th pixel is used to read the photoelectrons generated by the sensor of the i-th pixel and store them in the i-th integrating capacitor.
4. The pixel detector according to claim 3, characterized in that: The capacitor array sheet is provided with a plurality of through holes; the sensor of each pixel is arranged on a substrate to form a sensor array, and the readout circuit of each pixel is arranged on a substrate to form a readout circuit array; the capacitor array sheet is located between the sensor array and the readout circuit array, one end of each through hole on the capacitor array sheet is connected to the sensor array through a flip-chip packaging method, and the other end of each through hole on the capacitor array sheet and each integrating capacitor are connected to the readout circuit array through a flip-chip packaging method; wherein the i-th sensor in the sensor array is connected to the i-th readout circuit in the readout circuit array through the i-th through hole on the capacitor array sheet, the i-th integrating capacitor in the capacitor array sheet is connected to the i-th readout circuit in the readout circuit array, and the i-th readout circuit is used to read the photoelectrons generated by the i-th sensor and store them in the i-th integrating capacitor.
5. The pixel detector according to claim 3, characterized in that: The sensor of each pixel is arranged on a substrate to form a sensor array, and the readout circuit of each pixel is arranged on a substrate to form a readout circuit array. The readout circuit array is provided with a plurality of through holes, and the i-th through hole is connected to the i-th readout circuit in the readout circuit array; the readout circuit array is located between the sensor array and the capacitor array sheet, one end of each through hole on the readout circuit array is connected to the sensor array through a flip-chip packaging method, and each integral capacitor on the capacitor array sheet is connected to the readout circuit array through a flip-chip packaging method; wherein the i-th readout circuit in the readout circuit array is connected to the i-th sensor in the sensor array through the i-th through hole, so as to read the photoelectrons generated by it; the i-th integral capacitor in the capacitor array sheet is connected to the i-th readout circuit in the readout circuit array, so as to store the photoelectrons read by it.
6. The pixel detector according to claim 1, characterized in that: Each of the readout circuits is externally provided with N parallel integral capacitors as the integral capacitor group of the corresponding readout circuit. The nth integral capacitor of each of the readout circuits is arranged on the nth external substrate to form the nth external capacitor array sheet, n=1~N, and a total of N capacitor array sheets are formed; each capacitor array sheet is stacked, and except for the capacitor array sheet on the top layer, the remaining N-1 capacitor array sheets are provided with multiple pairs of capacitor connection holes, and the two ends of each integral capacitor on the N-1 capacitor array sheets are connected to a pair of capacitor connection holes on the capacitor array sheet where the integral capacitor is located, and adjacent capacitor array sheets are connected by a flip-chip packaging method, and the two integral capacitors of the i-th readout circuit on two adjacent layers of capacitor array sheets are connected in parallel through a pair of corresponding capacitor connection holes; the capacitor array sheet on the bottom layer is connected to the readout circuit in the pixel array by a flip-chip packaging method; wherein the readout circuit of the i-th pixel is used to read the photoelectrons generated by the sensor of the i-th pixel and store them in the integral capacitor group corresponding to the i-th pixel.
7. The pixel detector according to claim 1, characterized in that: The sensor of each pixel is arranged on a substrate to form a sensor array, and the readout circuit of each pixel is arranged on a substrate to form a readout circuit array; each of the readout circuits is externally provided with N parallel integral capacitors as the integral capacitor group of the corresponding readout circuit, and the nth integral capacitor of each of the readout circuits is arranged on the nth external substrate to form the nth external capacitor array sheet, n=1~N, and a total of N capacitor array sheets are formed; each capacitor array sheet is stacked, and each of the capacitor array sheets is provided with a plurality of first through holes, and the remaining N-1 capacitor array sheets except the capacitor array sheet on the top layer are provided with a plurality of pairs of capacitor connection holes, and the two ends of each integral capacitor on the N-1 capacitor array sheets are connected to the integral capacitor. A pair of capacitor connection holes on a capacitor array sheet are connected, adjacent capacitor array sheets are connected by a flip-chip packaging method, and two integral capacitors of the i-th readout circuit on two adjacent layers of capacitor array sheets are connected in parallel through a pair of corresponding capacitor connection holes; the capacitor array sheet on the bottom layer is connected to the readout circuit array by a flip-chip packaging method, and the sensor array is connected to the capacitor array sheet on the top layer by a flip-chip packaging method; wherein the i-th readout circuit in the readout circuit array is sequentially connected to the i-th sensor in the sensor array through the i-th first through hole on each layer of the capacitor array sheet, so as to read the photoelectrons generated by the sensor corresponding to the i-th pixel and store them in the integral capacitor group corresponding to the i-th pixel.
8. The pixel detector according to claim 1, characterized in that: The sensor of each pixel is arranged on a substrate to form a sensor array, and the readout circuit of each pixel is arranged on a substrate to form a readout circuit array; each of the readout circuits is externally provided with N parallel integral capacitors as the integral capacitor group of the corresponding readout circuit, and the nth integral capacitor of each of the readout circuits is arranged on the nth external substrate to form the nth external capacitor array sheet, n=1 to N, and a total of N capacitor array sheets are formed; The readout circuit array is provided with a plurality of first through holes, each readout circuit is connected to a first through hole, each capacitor array sheet is stacked, and the remaining N-1 capacitor array sheets except the capacitor array sheet on the top layer are provided with a plurality of pairs of capacitor connection holes, the two ends of each integral capacitor on the N-1 capacitor array sheets are connected to a pair of capacitor connection holes on the capacitor array sheet where the integral capacitor is located, adjacent capacitor array sheets are connected by a flip-chip packaging method, and the two integral capacitors of the i-th readout circuit on two adjacent layers of capacitor array sheets are connected in parallel through a pair of corresponding capacitor connection holes; the capacitor array sheet on the top layer is connected to the readout circuit array by a flip-chip packaging method, and the sensor array is connected to the readout circuit array by a flip-chip packaging method; wherein the i-th readout circuit in the readout circuit array is connected to the i-th sensor in the sensor array through the i-th first through hole, and is used to read the photoelectrons generated by the sensor corresponding to the i-th pixel and store them in the integral capacitor group corresponding to the i-th pixel.