True random number generator and generation method based on memristor

Abstract

The invention relates to the field of true random number generation, and discloses a true random number generator based on a memristor and a generation method.The true random number generator comprises a biasing circuit, a current hunger type ring oscillator and a time-to-digital conversion circuit which are cascaded; the bias circuit comprises a memristor; the current hunger type ring oscillator comprises an inverter chain formed by cascading a plurality of current hunger type inverters. The invention solves the problems of poor randomness and high power consumption of true random numbers in the prior art, and has the characteristics of small occupied area, simple circuit structure and high generation rate.

Description

Technical Field

[0001] The present invention relates to the field of true random number generation, and more specifically, to a true random number generator and generation method based on a memristor. Background Art

[0002] With the continuous improvement of the value of information, information security issues have become increasingly important. Random number generators play a fundamental role in secure communication and information systems, especially in fields such as encryption technology, authentication protocols, data encryption, and random padding. In contrast, pseudo-random number generators are based on deterministic mathematical models and initial seeds, so they are vulnerable to attacks; while true random number generators extract randomness from physical processes (such as electrical noise in circuits), and this randomness cannot be predicted theoretically. By collecting noise-based entropy through a dedicated chip circuit, a raw bit stream with high randomness can be generated, and these bit streams are then further refined by a post-processing unit to enhance their randomness.

[0003] There is a prior art true random number generator that amplifies power supply noise. It includes a first oscillator, a second oscillator, a decorrelation module, a data stream register counting module, a data post-processing module, a synchronizer, and a counting state generator. The second oscillator contains a ring voltage-controlled oscillator, and the bias voltage of the ring voltage-controlled oscillator is generated by a noise source.

[0004] However, the prior art has deficiencies such as poor randomness and high power consumption in generating true random numbers. Therefore, how to invent a true random number generator that can continuously generate true random numbers with high randomness and high energy efficiency is a technical problem that urgently needs to be solved in this technical field. Summary of the Invention

[0005] In order to solve the problems of poor randomness and high power consumption of true random numbers in the prior art, the present invention provides a true random number generator and generation method based on a memristor, which has the characteristics of small occupied area, simple circuit structure, and high generation rate.

[0006] To achieve the above object of the present invention, the following technical solutions are adopted:

[0007] A true random number generator based on a memristor includes a cascaded bias circuit, a current-starved ring oscillator, and a time-to-digital conversion circuit; the bias circuit includes a memristor; the current-starved ring oscillator includes an inverter chain composed of a plurality of cascaded current-starved inverters.

[0008] Preferably, the bias circuit further includes an access transistor M1, an access transistor M3, and a strobe transistor M2. Among them, M1 is a PMOS transistor, and M2 and M3 are NMOS transistors. The source of M1 is externally connected to a positive voltage Vdd. The gate of M1 is connected to the drain of M1. The drain of M1 is also connected to the drain of M2. The gate of M2 is externally connected to a control voltage Vcrtl. The source of M2 is connected to one end of the memristor. The other end of the memristor is respectively connected to the drain and the gate of M3. The source of M3 is externally connected to a reference voltage Vss.

[0009] Further, the bias circuit further includes transistors M4 and M5 for limiting the current of the current-starved inverter. The source of M4 is connected to Vdd. The drain of M4 is connected to one end of a plurality of current-starved inverters. The gate of M4 is connected to the other end of the memristor. The source of M5 is connected to Vss. The drain of M5 is connected to the other end of a plurality of current-starved inverters. The gate of M5 is connected to the drain of M1.

[0010] Furthermore, it further includes a transistor group M4 and M5 for limiting the current of the current-starved inverter. The M4 and M5 include multiple parallel-connected transistors. The sources of the transistors in M4 are connected to Vdd. The sources of the transistors in M4 are connected to Vdd. The drains of the transistors in M4 are connected to one end of a plurality of current-starved inverters. The gates of the transistors in M4 are connected to the other end of the memristor. The sources of the transistors in M5 are connected to Vss. The drains of the transistors in M5 are connected to the other end of a plurality of current-starved inverters. The gates of the transistors in M5 are connected to the drain of M1.

[0011] Furthermore, the current-starved ring oscillator further includes a NAND gate and an XOR gate. The NAND gate, the inverter chain, and the XOR gate are connected in sequence. The positive terminals of the NAND gate, a plurality of current-starved inverters are connected to the drain of M4. The negative terminals of the NAND gate, a plurality of current-starved inverters are connected to the source of M5. The first input terminal of the NAND gate is externally connected to an oscillator enable terminal, and the second input terminal of the NAND gate is connected to the first input terminal of the XOR gate. The second input terminal of the XOR gate is connected to the output of the intermediate current-starved inverter.

[0012] Furthermore, the time-to-digital conversion circuit includes a time-to-digital conversion unit. The output terminal of the XOR gate is connected to the time-to-digital conversion unit. The time-to-digital conversion unit continuously quantifies the pulse width of the pulse signal output by the XOR gate and takes the lower bits as a series of original random bits for output.

[0013] Further, the time digital conversion circuit further includes a delay module; the output end of the exclusive OR gate is also connected to the delay module; the output of the delay module is connected to the EN end of the time digital conversion unit; the delay unit further controls and adjusts the width of the signal output by the exclusive OR gate by setting a specific delay time.

[0014] A true random number generation method, based on the true random number generator, includes the following specific steps:

[0015] Provide a random bias voltage for the current-starved ring oscillator through a bias circuit including a memristor and an access transistor;

[0016] The current-starved ring oscillator generates a pulse signal with a random pulse width based on the random bias voltage;

[0017] The time digital conversion circuit continuously quantifies the width of the generated pulse signal, converts the pulse width randomness into a digital signal, and provides a random bit stream for random number generation.

[0018] Preferably, a random bias voltage is provided for the current-starved ring oscillator through a bias circuit embedded with a memristor. The specific steps are as follows:

[0019] Connect the control voltage V of the NMOS transistor in the access transistor ctrl to a constant voltage higher than the device threshold voltage;

[0020] Set the source voltage V of the NMOS transistor in the access transistor Nbias to vary around VDD, and set the source voltage V of the PMOS access transistor in the access transistor Pbias to vary around GND;

[0021] Set the current change through the RRAM to cause a differential change in V Pbias and V Nbias and provide a random bias voltage for the current-starved ring oscillator through the differential change.

[0022] Further, the pulse width output by the current-starved ring oscillator quantifies the phases of two stages of the current-starved ring oscillator. Its pulse width T pluse is expressed as:

[0023] T pluse = N×T inv + T jitter + T XOR + T NAND

[0024] where T inv is the propagation delay of a single current-starved inverter, which is affected by the random resistance fluctuation of the memristor, Tjitter is the random jitter noise accumulated from the first stage to the intermediate stage of the current-starved inverter. N is half of the number of current-starved inverters, and T XOR and T NAND are the propagation delays of the exclusive-OR gate and the NAND gate of the current-starved ring oscillator respectively. T inv and T jitter both vary with time, and the entropy in T pluse is determined by both of them.

[0025] The beneficial effects of the present invention are as follows:

[0026] The present invention discloses a memristor-based true random number generator, which innovatively combines the random telegraph noise of the memristor and the jitter noise of the oscillator to form a composite entropy source. Through the digital processing of these dynamic entropy sources, high-quality and unpredictable true random numbers can be continuously generated, and it has the characteristics of small occupied area, simple circuit structure, and high generation rate. Description of the Drawings

[0027] Figure 1 is the overall structure diagram of the memristor-based true random number generator.

[0028] Figure 2 is the circuit schematic diagram of the bias circuit and the current-starved ring oscillator in Embodiment 2.

[0029] Figure 3 is the circuit schematic diagram of the time-to-digital conversion circuit in Embodiment 3.

[0030] Figure 4 is the flow schematic diagram of a true random number generation method. Detailed Embodiments

[0031] The present invention will be described in detail below with reference to the drawings and specific embodiments.

[0032] Embodiment 1

[0033] As Figure 1 shown, a memristor-based true random number generator includes a cascaded bias circuit, a current-starved ring oscillator, and a time-to-digital conversion circuit; the bias circuit includes a memristor; the current-starved ring oscillator includes an inverter chain composed of a plurality of cascaded current-starved inverters.

[0034] In this embodiment, the propagation delay of the ring oscillator can be adjusted by adjusting the working current, and this adjustment is achieved by controlling the gate voltages of the NMOS and PMOS transistors connected in series in the inverter chain. The gate voltages are provided by the bias circuit.

[0035] In this embodiment, an RRAM is embedded in the bias circuit, and the random telegraph noise (RTN) of the RRAM is used to randomly regulate the gate bias voltage, so that the propagation delay of the inverter exhibits random variation characteristics. Connecting an even number of current-starved inverters in series with a NAND gate can form a CSRO. When the input EN signal of the NAND gate is at a high level, the CSRO is equivalent to an odd-numbered inverter chain and thus starts to oscillate.

[0036] In this embodiment, the phase difference between different stages of the oscillator is mainly affected by two factors: one is the propagation delay of the inverter chain, which is affected by the thermal noise and random telegraph noise of the RRAM; the other is the phase shift caused by the power supply noise. The combined action of these two factors makes the phase difference between different stages of the oscillator determined by parameters that change with time.

[0037] By performing an exclusive OR operation on the signals of two stages of the oscillator, the pulse width of the exclusive OR output can be obtained, and this pulse width quantifies the dynamic entropy source. Then, a time-to-digital converter is used to digitally quantify the pulse width. The low bits of the time-to-digital converter directly reflect the delay changes caused by the above two kinds of noises, and the generated output has a high degree of randomness.

[0038] Embodiment 2

[0039] In a specific embodiment, the bias circuit further includes an access transistor M1, an access transistor M3, and a strobe transistor M2; among them, M1 is a PMOS transistor, and M2 and M3 are NMOS transistors; the source of M1 is externally connected to the positive voltage Vdd; the gate of M1 is connected to the drain of M1; the drain of M1 is also connected to the drain of M2; the gate of M2 is externally connected to the control voltage Vcrtl; the source of M2 is connected to one end of the memristor; the other end of the memristor is respectively connected to the drain and gate of M3; the source of M3 is externally connected to the reference voltage Vss.

[0040] In this embodiment, the bias circuit is as shown on the left. The access transistor of this circuit has a 1T-1R structure and is used to program the memristor as needed. The size of the NMOS is designed to withstand the compliance current of the memristor. During normal true random number generation operations, the V of the access transistor can be connected to a constant voltage higher than the threshold voltage of the NMOS device. Among them, the change of V is positively correlated with the current flowing through the RRAM, and V is negatively correlated with the current of the memristor. That is, V = V - (V + V + V). V is set to vary around VDD, and V Figure 2 as shown on the left. The access transistor of this circuit has a 1T-1R structure and is used to program the memristor as needed. The size of the NMOS is designed to withstand the compliance current of the memristor. During normal true random number generation operations, the V of the access transistor can be connected to a constant voltage higher than the threshold voltage of the NMOS device. Among them, the change of V is positively correlated with the current flowing through the RRAM, and V is negatively correlated with the current of the memristor. That is, V = V - (V + V + V). V is set to vary around VDD, and V ctrl is connected to a constant voltage higher than the threshold voltage of the NMOS device. Among them, the change of V is positively correlated with the current flowing through the RRAM, and V is negatively correlated with the current of the memristor. That is, V = V - (V + V + V). V is set to vary around VDD, and V Nbias is positively correlated with the current flowing through the RRAM, and V Pbias is negatively correlated with the current of the memristor. That is, V Pbias = V DD - (V RRAM + V DS + V Nbias ). V Nbias is set to vary around VDD, and V PbiasSet to vary around GND, ensuring that the series-connected PMOS and NMOS transistors in the current-starved inverter operate near their respective threshold voltages.

[0041] In a specific embodiment, it further includes transistor groups M4 and M5 that limit the current of the current-starved inverter; multiple parallel-connected transistors are included in M4 and M5; the sources of the transistors in M4 are connected to Vdd; the sources of the transistors in M4 are connected to Vdd; the drains of the transistors in M4 are connected to one end of several current-starved inverters; the gates of the transistors in M4 are connected to the other end of the memristor; the sources of the transistors in M5 are connected to Vss; the drains of the transistors in M5 are connected to the other ends of several current-starved inverters; the gates of the transistors in M5 are connected to the drain of M1.

[0042] In a specific embodiment, the current-starved ring oscillator is as Figure 2 shown on the right, and it further includes NAND gates and XOR gates; the NAND gates, the inverter chain, and the XOR gates are connected in sequence; the positive terminals of the NAND gates, several current-starved inverters are connected to the drain of M4; the negative terminals of the NAND gates, several current-starved inverters are connected to the source of M5; the first input terminal of the NAND gate is externally connected to the oscillator enable terminal, and the second input terminal of the NAND gate is connected to the first input terminal of the XOR gate; the second input terminal of the XOR gate is connected to the output of the middle current-starved inverter.

[0043] In this embodiment, at the beginning, through the enable EN, the current-starved ring oscillator starts to oscillate, and its oscillation frequency will be affected by the random telegraph noise and jitter noise of the memristor. Jitter noise is caused by random factors such as thermal noise and the intrinsic noise of electronic components, and it is manifested as an unpredictable time offset. The two ends of the XOR gate are respectively connected to the first stage and the middle stage of the current-starved ring oscillator. The output of the XOR gate will generate continuous pulse outputs, and the pulse width of the output quantifies the phase difference between the two stages of the current-starved ring oscillator. This pulse width T pluse can be expressed as:

[0044] T pluse = N × T inv + T jitter + T XOR + T NAND

[0045] where T inv is the propagation delay of a single current-starved inverter, which is affected by the true random number generation of the memristor. T jitter is the accumulated random jitter noise from the first stage to the middle stage. N is half of the number of current-starved inverters. T XOR 、T NAND are the propagation delays of the XOR gate and the NAND gate respectively. In the formula, Tinv With T jitter both change with time, and T pluse The entropy in is determined by both of them.

[0046] In a specific embodiment, the time-to-digital conversion circuit is as Figure 3 shown, and includes a time-to-digital conversion unit; the output end of the exclusive-OR gate is connected to the time-to-digital conversion unit; the time-to-digital conversion unit continuously quantifies the pulse width of the pulse signal output by the exclusive-OR gate, and takes the lower bits thereof as a series of original random bits for output.

[0047] In a specific embodiment, the time-to-digital conversion circuit further includes a delay module; the output end of the exclusive-OR gate is further connected to the delay module; the output of the delay module is connected to the EN end of the time-to-digital conversion unit; the delay unit further controls and adjusts the width of the signal output by the exclusive-OR gate by setting a specific delay time.

[0048] In this embodiment, XOR_out is a continuous pulse signal generated by the previous-stage exclusive-OR, and this signal is simultaneously connected to the data input ends of the delay module and the time-to-digital conversion unit. The delay module further controls and adjusts the width of the XOR_out pulse signal by setting a specific delay time, so as to achieve more refined pulse width measurement. This design can effectively enhance the measurement accuracy, enabling the TDC unit to more accurately quantify the width of the pulse signal and improving the resolution and randomness in the random number generation process. The time-to-digital conversion unit continuously quantifies the pulse width of the pulse signal, and finally takes the lower bits of the output signal of the time-to-digital conversion unit as the true random number composed of original random bits for output.

[0049] Embodiment 3

[0050] As Figure 4 shown, a true random number generation method, based on the true random number generator, includes the following specific steps:

[0051] Provide a random bias voltage to the current-starved ring oscillator through a bias circuit including a memristor and an access transistor;

[0052] The current-starved ring oscillator generates a pulse signal with a random pulse width based on the random bias voltage;

[0053] The time-to-digital conversion circuit continuously quantifies the width of the generated pulse signal, converts the pulse width randomness into a digital signal, and provides a random bit stream for random number generation.

[0054] In a specific embodiment, providing a random bias voltage to the current-starved ring oscillator through a bias circuit embedded with a memristor, the specific steps are:

[0055] Connect the control voltage V of the NMOS transistor in the access transistor ctrl to a constant voltage higher than the device threshold voltage;

[0056] Set the source voltage V of the NMOS transistor in the access transistor Nbias to vary around VDD, and set the source voltage V of the PMOS access transistor in the access transistor Pbias to vary around GND;

[0057] Make the differential change of V Pbias and V Nbias through the current change set by the RRAM, and provide a random bias voltage to the current-starved ring oscillator through the differential change.

[0058] In a specific embodiment, the pulse width output by the current-starved ring oscillator quantifies the phase of two stages of the current-starved ring oscillator, and its pulse width T pluse is expressed as:

[0059] T pluse = N×T inv + T jitter + T XOR + T NAND

[0060] where T inv is the propagation delay of a single current-starved inverter, which is affected by the random resistance fluctuation of the memristor, T jitter is the random jitter noise accumulated from the first stage to the intermediate stage of the current-starved inverter, N is half of the number of current-starved inverters, T XOR 、T NAND are the propagation delays of the exclusive-OR gate and the NAND gate of the current-starved ring oscillator respectively, T inv and T jitter both change with time, and the entropy in T pluse is determined by both.

[0061] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not limitations on the implementation manners of the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the claims of the present invention.

Claims

1. A true random number generator based on a memristor, characterized in that: It comprises a cascaded bias circuit, a current-starved ring oscillator and a time-to-digital conversion circuit; the bias circuit comprises a memristor; the current-starved ring oscillator comprises an inverter chain composed of a plurality of cascaded current-starved inverters.

2. The true random number generator based on memristor according to claim 1, characterized in that: The bias circuit also includes an access transistor M1, an access transistor M3, and a selection transistor M2; wherein M1 is a PMOS transistor, and M2 and M3 are NMOS transistors; the source of M1 is externally connected to a positive voltage Vdd; the gate of M1 is connected to the drain of M1; the drain of M1 is also connected to the drain of M2; the gate of M2 is externally connected to a control voltage Vcrtl; the source of M2 is connected to one end of a memristor; the other end of the memristor is respectively connected to the drain and gate of M3; and the source of M3 is externally connected to a reference voltage Vss.

3. The memristor-based true random number generator according to claim 2, characterized in that: The bias circuit also includes transistors M4 and M5 for limiting the current of the current-starved inverter; the source of M4 is connected to Vdd; the drain of M4 is connected to one end of several current-starved inverters; the gate of M4 is connected to the other end of the memristor; the source of M5 is connected to Vss; the drain of M5 is connected to the other end of several current-starved inverters; and the gate of M5 is connected to the drain of M1.

4. The memristor-based true random number generator according to claim 2, characterized in that: It also includes transistor groups M4 and M5 for limiting the current of the current-starved inverter; the M4 and M5 include multiple parallel transistors; the source of the transistor in M4 is connected to Vdd; the source of the transistor in M4 is connected to Vdd; the drain of the transistor in M4 is connected to one end of several current-starved inverters; the gate of the transistor in M4 is connected to the other end of the memristor; the source of the transistor in M5 is connected to Vss; the drain of the transistor in M5 is connected to the other end of several current-starved inverters; the gate of the transistor in M5 is connected to the drain of M1.

5. The memristor-based true random number generator according to any one of claims 3 or 4, characterized in that: The current-starved ring oscillator also includes a NAND gate and an XOR gate; the NAND gate, an inverter chain, and the XOR gate are connected in sequence; the NAND gate and the positive terminals of a plurality of current-starved inverters are connected to the drain of M4; the NAND gate and the negative terminals of a plurality of current-starved inverters are connected to the source of M5; the first input terminal of the NAND gate is externally connected to the oscillator enable terminal, and the second input terminal of the NAND gate is connected to the first input terminal of the XOR gate; the second input terminal of the XOR gate is connected to the output of the intermediate current-starved inverter.

6. The memristor-based true random number generator according to claim 5, characterized in that: The time-to-digital conversion circuit comprises a time-to-digital conversion unit; the output end of the XOR gate is connected to the time-to-digital conversion unit; the time-to-digital conversion unit continuously quantizes the pulse width of the pulse signal output by the XOR gate, and takes the low bit as a series of original random bits for output.

7. The memristor-based true random number generator according to claim 6, characterized in that: The time-to-digital conversion circuit also includes a delay module; the output end of the XOR gate is also connected to the delay module; the output of the delay module is connected to the EN end of the time-to-digital conversion unit; the delay unit further controls and adjusts the width of the signal output by the XOR gate by setting a specific delay time.

8. A method for generating true random numbers, characterized in that: Based on the true random number generator according to any one of claims 1 to 7, the method comprises the following specific steps: providing a random bias voltage to a current-starved ring oscillator through a bias circuit including a memristor and an access transistor; The current-starved ring oscillator generates a pulse signal with a random pulse width based on a random bias voltage; The time-to-digital conversion circuit continuously quantizes the width of the generated pulse signal, converts the randomness of the pulse width into a digital signal, and provides a random bit stream for random number generation.

9. The method for generating true random numbers according to claim 8, wherein: The random bias voltage is provided to the current-starved ring oscillator through the bias circuit embedded with the memristor. The specific steps are as follows: The control voltage V of the NMOS transistor in the access transistor ctrl Connect to a constant voltage above the device threshold voltage; The source voltage V of the NMOS transistor in the access transistor Nbias Set to vary around VDD, the source voltage V of the PMOS access transistor in the access transistor Pbias Set to vary around GND; The RRAM sets the current to change the V Pbias and V Nbias The differential change is used to provide a random bias voltage to the current-starved ring oscillator.

10. The method for generating true random numbers according to claim 8, wherein: The pulse width of the current starved ring oscillator output quantifies the phase of the two phases of the current starved ring oscillator. Its pulse width T pluse It is expressed as: T pluse =N×T inv +T jitter +T XOR +T NAND Where T inv is the propagation delay of a single starved current inverter, which is affected by the random resistance fluctuations of the memristor, T jitter is the random jitter noise accumulated from the first stage to the middle stage of the current-starved inverter, N is half the number of current-starved inverters, T XOR , T NAND are the propagation delays of the XOR gate and NAND gate of the current-starved ring oscillator, T inv With T jitter All change with time, T pluse The entropy in is determined by both.

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