Low-power-consumption slew rate increasing circuit

Abstract

The invention relates to the technical field of semiconductor integrated circuit design, in particular to a low-power-consumption slew rate increasing circuit which is composed of two field-effect tubes J1 and J2, six transistors Q1 to Q6, two current sources I1 and I2 and two resistors R1 and R2 which are correspondingly connected to form the slew rate increasing circuit. The slew rate increasing circuit is applied to the operational amplifier and is used for solving the problems of slew rate and power consumption of the amplifier. According to the invention, the slew rate is increased by about 10 times on the premise that the direct current characteristic and the small-signal alternating current characteristic are not influenced and extra power consumption is basically not increased.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor integrated circuit design, and particularly relates to a low-power slew rate boosting circuit. Background Art

[0002] The operational amplifier is the most important and popular building block in the design of circuits for realizing high-precision analog and mixed-mode modules, and its performance largely determines the performance of the entire circuit or even the system. With the development of technologies such as wireless network technology, 5G technology, and Internet of Things technology, the speed of signals to be processed is getting higher and higher, which puts higher requirements on the slew rate performance of operational amplifiers. The slew rate (SR) of an amplifier, also known as the conversion rate, is an important indicator for measuring the performance of signal processing circuits. The slew rate affects the ability of the amplifier to track and amplify rapidly changing signals. If the change rate of the input signal exceeds the slew rate of the operational amplifier, the output signal cannot respond in time and distortion will occur. The slew rate calculation formula is SR = I / C, where C is the frequency compensation capacitor and I is the current for charging and discharging C. In addition, due to the development and progress of intelligent, miniaturized, and portable electronic devices, operating under low-power conditions has gradually become an essential requirement for the system.

[0003] The mainstream methods for boosting the slew rate in the prior art are as follows: increasing the device's characteristic frequency and reducing the parasitic capacitance, but this depends on the high-frequency characteristics of transistors in the manufacturing process and will increase the processing cost; increasing the static current of the amplifier circuit to increase the charging and discharging current provided to the frequency compensation capacitor, but this will greatly increase the power consumption and may also reduce the stability of the operational amplifier; reducing the compensation capacitor will reduce the stability of the operational amplifier.

[0004] Therefore, there is an urgent need for a low-power slew rate boosting circuit at present. Summary of the Invention

[0005] In view of this, the present invention discloses a low-power slew rate boosting circuit to solve the above problems; it includes: two field effect transistors J1, J2, six transistors Q1 to Q6, two current sources I1, I2, and two resistors R1, R2; the connection method is as follows: the base of Q1 is connected to the base of Q2, the emitter of Q1 is respectively connected to the emitter of Q2, one end of R1, one end of R2, and one end of the current source I2, and the collector of Q1 is respectively connected to the base of Q4 and the drain of J1; the collector of Q2 is respectively connected to the base of Q3 and the drain of J2; the emitter of Q3 is connected to the other end of R1, and the collector of Q3 is respectively connected to the collector of Q4, the other end of I2, the collector of Q5, the base of Q5, and the base of Q6; the emitter of Q4 is connected to the other end of R2; the emitter of Q5 is respectively connected to one end of I1 and the emitter of Q6; the source of J1 is respectively connected to the other end of I1 and the source of J2.

[0006] The present invention provides a low-power slew rate boosting circuit, which realizes a boost of about 10 times in slew rate on the premise of not affecting the DC characteristics, small-signal AC characteristics, and basically not increasing additional power consumption. Description of the Drawings

[0007] Figure 1 is the circuit diagram of the low-power slew rate boosting circuit in the present invention;

[0008] Figure 2 is the circuit diagram of the two-stage operational amplifier applying the circuit of the present invention in the embodiment;

[0009] Figure 3 is the schematic diagram of the slew rate simulation comparison of the low-power slew rate boosting circuit in the present invention. Detailed Embodiments

[0010] In order to make the purpose, technical solutions, features and advantages of the present invention clearer and more understandable, the present invention will be further described below in conjunction with the drawings and embodiments.

[0011] Embodiment 1 is a preferred embodiment of the present invention:

[0012] As Figure 1 shown, this embodiment includes: two field effect transistors J1, J2, six transistors Q1 to Q6, two current sources I1, I2, and two resistors R1, R2; their connection method is: the base of Q1 is connected to the base of Q2, the emitter of Q1 is respectively connected to the emitter of Q2, one end of R1, one end of R2, and one end of the current source I2, and the collector of Q1 is respectively connected to the base of Q4 and the drain of J1; the collector of Q2 is respectively connected to the base of Q3 and the drain of J2; the emitter of Q3 is connected to the other end of R1, and the collector of Q3 is respectively connected to the collector of Q4, the other end of I2, the collector of Q5, the base of Q5, and the base of Q6; the emitter of Q4 is connected to the other end of R2; the emitter of Q5 is respectively connected to one end of I1 and the emitter of Q6; the source of J1 is respectively connected to the other end of I1 and the source of J2.

[0013] The base of Q1 serves as the bias voltage terminal, the emitter of Q5 serves as the negative power supply terminal, the gate of J1 serves as the inverting input terminal, the gate of J2 serves as the non-inverting input terminal, and the collector of Q5 serves as the output terminal.

[0014] Figure 1 The circuit in the dashed box 1 in [[ ]] is the input circuit, and the circuit in the dashed box 2 is the output circuit. The input circuit includes Q1, Q2, J1, J2, and I1, and the output circuit includes Q3, Q4, Q5, Q6, R1, R2, and I2. The input circuit and the output circuit are connected to form the low-power slew rate boosting circuit of this embodiment.

[0015] Furthermore, the NJFET transistors J1 and J2 are of the same type; Q1, Q2, Q3, and Q4 are PNP transistors, and Q5 and Q6 are NPN transistors.

[0016] In this embodiment, the static current IC1 of the transistor Q1 is equal to the static current IC2 of the transistor Q2. The static current of the current source I1 is I11. Considering fluctuations in temperature, power supply voltage, and process, etc., by designing IC1, IC2, and I11 to be in a mismatched state, I11 / 2 is made less than IC1 and IC2, and the difference between IC1 and IC2 and I11 / 2 should not be too large. IC1 and IC2 are preferably 1.1 to 1.5 times of I11 / 2, that is, the static current of Q1 is 0.55 to 0.75 times the static current of I1.

[0017] Embodiment 2 is a preferred embodiment of the present invention:

[0018] As Figure 2 shown in the circuit diagram of this embodiment, the circuit in the dashed box 3 is the slew rate boosting circuit of the present invention, the collector of Q5 outputs IOUT, and the circuit in the dashed box 4 is a traditional two-stage operational amplifier, and the collector of Q6 outputs IOUT1. This embodiment is powered by ±15V with a static current of 0.6mA.

[0019] Furthermore, in the static state, to conform to Kirchhoff's law at the collector VOUT1 point of Q1 and the collector VOUT2 point of Q2, the transistors Q1 and Q2 must enter the saturation region, and the voltages at the VOUT1 point and the VOUT2 point will surely be raised to be close to the positive power supply VCC, resulting in the base voltages of the transistors Q3 and Q4 also being close to the positive power supply VCC, and the transistors Q3 and Q4 being in the off state, that is, no current flows through the transistors Q3 and Q4. At this time, the output current IOUT of the low-power slew rate boosting circuit is equal to the static current I22 of the current source I2; in this state, except for IC1 and IC2, the low-power slew rate boosting circuit hardly adds extra static current.

[0020] Furthermore, in the dynamic state, the behavior of the circuit is divided into two cases: large signal and small signal.

[0021] Taking the small signal case as an example, VIN DM <100mV, where VIN DM is the differential input voltage. The difference between the current IJ1 flowing through J1 and the current IJ2 flowing through J2 is not too large. At this time, IC1 < IJ1 and IC2 < IJ2, the voltages at the VOUT1 point and the VOUT2 point are close to the positive power supply VCC, the transistors Q3 and Q4 remain off, and the slew rate boosting circuit does not work, similar to the static state.

[0022] Taking the large-signal case as an example, at this time VIN DM >> 100mV, only one of the NJFET J1 and NJFET J2 conducts, and the current I11 of the current source I1 will only flow through one of the NJFET J1 or NJFET J2. The input of the inverting input terminal is -IN, and the input of the non-inverting input terminal is +IN. If +IN >> -IN, the NJFET J2 conducts and the NJFET J1 turns off, and IJ2 = I11. Since both the current IC1 and the current IC2 are less than I11, the NJFET J2 tends to enter the saturation region, and the base voltage VOUT2 of Q3 is greatly reduced, and the transistor Q3 conducts, and a large dynamic current IC3 is generated at the collector. At this time, the output current of the low-power slew rate boosting circuit: IOUT = I22 + IC3. IOUT is mirrored by the transistor Q6 to the input stage of the second-stage operational amplifier as the tail current IOUT1 for charging and discharging the compensation capacitor in the large-signal dynamic case to improve the slew rate. As the output voltage gradually increases, +IN and -IN gradually approach, and the circuit gradually returns to the small-signal operating state until the static situation, that is, the slew rate boosting circuit of the present invention can adaptively improve the slew rate with the change of the input voltage; if +IN << -IN, the slew rate boosting circuit will generate a large dynamic current IC4. That is, in any case, a large IOUT will be generated to increase the charging and discharging current of the compensation capacitor in the large dynamic case, thereby improving the slew rate, while basically not affecting the static and small-signal operations.

[0023] Such as Figure 3 shown is a schematic diagram of the slew rate simulation comparison of the low-power slew rate boosting circuit, Figure 3 The simulation results show that on the premise of consuming the same static current of 0.6 mA, the positive slew rate of the traditional second-stage operational amplifier before improvement is 3.6 V / μs, and the negative slew rate is 3 V / μs; while the positive slew rate of the improved second-stage operational amplifier using the low-power slew rate boosting circuit of the present invention is 39 V / μs, and the negative slew rate is 32 V / μs, and the slew rate is increased by about 10 times.

[0024] It should be noted that although the present invention describes the working principle of the circuit based on the bipolar process and the second-stage operational amplifier, the core principle of the present invention can also be applied to the NPN or PNP operational amplifier based on the bipolar process with minor modifications, and can also be applied to the NMOS or PMOS operational amplifier based on the CMOS process.

[0025] Finally, it should be noted that the above description only describes some embodiments of the present invention. For those skilled in the art, various changes, modifications, substitutions, and deformations can be conceived without departing from the principles and spirits of the present invention. The protection scope of the present invention is defined by the appended claims and their equivalents, and the above actions should all be covered within the protection scope of the present invention.

Claims

1. A low power consumption slew rate boosting circuit, applied to an operational amplifier, characterized in that: include: Two field effect tubes J1 and J2, six transistors Q1 to Q6, two current sources I1 and I2, and two resistors R1 and R2; the connection method is as follows: the base of Q1 is connected to the base of Q2, the emitter of Q1 is respectively connected to the emitter of Q2, one end of R1, one end of R2, and one end of the current source I2, the collector of Q1 is respectively connected to the base of Q4 and the drain of J1; the collector of Q2 is respectively connected to the base of Q3 and the drain of J2; the emitter of Q3 is connected to the other end of R1, the collector of Q3 is respectively connected to the collector of Q4, the other end of I2, the collector of Q5, the base of Q5, and the base of Q6; the emitter of Q4 is connected to the other end of R2; the emitter of Q5 is respectively connected to one end of I1 and the emitter of Q6; the source of J1 is respectively connected to the other end of I1 and the source of J2.

2. A low power consumption slew rate boosting circuit according to claim 1, characterized in that: The emitter of Q1 serves as a positive power supply terminal, the base of Q1 serves as a bias voltage terminal, the emitter of Q5 serves as a negative power supply terminal, the gate of J1 serves as an inverting input terminal, the gate of J2 serves as a non-inverting input terminal, and the collector of Q5 serves as an output terminal.

3. The low power consumption slew rate boosting circuit according to claim 1, characterized in that: Field effect transistors J1 and J2 are both NJFET tubes.

4. The low power consumption slew rate boosting circuit according to claim 1, characterized in that: Q1, Q2, Q3, and Q4 are PNP transistors, and Q5 and Q6 are NPN transistors.

5. A low power consumption slew rate boosting circuit according to claim 4, characterized in that: The quiescent current of Q1 is 0.55 to 0.75 times the quiescent current of I1.

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