Heat effect decoupling method in amorphous oxide semiconductor transistor HCD test

Abstract

The invention discloses a thermal effect decoupling method in an amorphous oxide semiconductor transistor HCD test, and belongs to the technical field of semiconductor transistor test. The method comprises the following steps: dividing amorphous oxide semiconductor transistor devices into a plurality of test batches; dividing the devices of the same test batch into an HCD group and a BTI group; all the devices are subjected to HCD testing, the testing conditions of the devices in different testing batches are different, and the HCD group pressure applying stage in each testing batch is Vdsgt; vds = 0, and Vds = 0 in the BTI group; and extracting electrical parameters of the device after pressure application under each test condition to draw a transfer characteristic curve, and obtaining a thermal effect threshold voltage variation of the to-be-tested device by using the threshold voltage variation of the HCD group device after pressure application and the threshold voltage variation of the BTI group device after pressure application. According to the method, the blank of the quantitative evaluation method for the HCD effect of the small-size amorphous oxide semiconductor device is filled, and important reference is provided for the design of a DRAM (Dynamic Random Access Memory) array circuit.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor transistor testing, and particularly relates to a method for decoupling thermal effects in the HCD test of amorphous oxide semiconductor transistors. Background Art

[0002] The miniaturization process of the traditional silicon-based 1T1C structure has gone through technology nodes of 18nm, 1x, 1y, and 1a. Currently, it faces huge bottlenecks near the 10nm node. Oxide semiconductors are regarded as the key technology for the further miniaturization of dynamic random access memory (DRAM) and a significant reduction in area overhead due to their low off-state current, low overall process temperature, and compatibility with back-end processes. However, when oxide semiconductor materials are applied to the DRAM field, they will have to face new stability problems. Taking 2T0C DRAM as an example, the write and read transistors simultaneously experience stresses of V gs and V ds during the write and read phases, respectively, that is, they are damaged by the hot carrier degradation (HCD) effect, which may cause the degradation of transistor performance and the failure of the overall DRAM device unit.

[0003] For amorphous oxide semiconductor transistor devices, small-sized amorphous oxide semiconductor transistors (gate length / gate width < 100nm) have more complex HCD behaviors while having the potential to continue the DRAM miniaturization path. Therefore, a comprehensive, systematic, and scientific evaluation method for small-sized devices damaged by the HCD effect has not been established, making the circuit design of DRAM arrays more difficult. Summary of the Invention

[0004] In view of the damage caused by the HCD effect to small-sized amorphous oxide semiconductor devices, the present invention proposes a method for decoupling thermal effects in the HCD test of amorphous oxide semiconductor transistors.

[0005] The technical solution of the present invention is as follows:

[0006] A method for decoupling thermal effects in the HCD test of amorphous oxide semiconductor transistors, characterized by specifically including the following steps:

[0007] 1) Select multiple amorphous oxide semiconductor transistors of the same model as the devices to be tested, divide the devices to be tested into several test batches, and divide the devices in each test batch into an HCD group and a BTI group;

[0008] 2) Perform an "apply pressure - measure - apply pressure -... - apply pressure - measure" HCD test on the devices to be tested. The "apply pressure" is to apply a drain-source voltage V ds between the source and drain electrodes of the device, and apply a gate-source voltage V gs; among them, devices in different test batches are subjected to different test conditions, and the test conditions include temperature, humidity, bending stress, and the peak value, frequency, and duty cycle of V gs and V ds ; the test conditions for all devices in each test batch are the same, except that V ds >0 during the pressure application stage of the HCD group, while V ds =0 for the BTI group;

[0009] 3) Extract the test results of the devices to be tested in step 2), draw the transfer characteristic curve according to the electrical parameters of the devices after applying pressure under each test condition, extract the threshold voltage change of the devices in the HCD group after applying pressure and the threshold voltage change of the devices in the BTI group after applying pressure, and obtain the threshold voltage change caused by the thermal effect of the devices to be tested through the following formula:

[0010] ΔV th,热效应 =ΔV th,HCD -ΔV th,BTI .

[0011] Furthermore, the electrical parameters include V th , I on , SS, g m , DIBL or I off .

[0012] Furthermore, the amorphous oxide semiconductor transistor device is a back-gate structure, a top-gate structure, a double-gate structure, and three-dimensional fin-gate structure, gate-all-around structure, ring-channel structure, stacked nanosheet structure, or vertical-channel structure.

[0013] Furthermore, the channel layer of the amorphous oxide semiconductor transistor device is ITO, ln 2 O 3 , IGZO, IAZO, ITZO, CAAC-IGZO, IZO, ZnO, IWO, ITWO, or a multi-element doped or composite stacked-channel oxide semiconductor based on the above materials.

[0014] Furthermore, the channel length of the channel layer of the amorphous oxide semiconductor transistor device is 5-10000 nm, and the channel width is 10-10000 nm.

[0015] Furthermore, the number of devices in the HCD group and the BTI group in each test batch exceeds 100.

[0016] Furthermore, the pressure application is to apply a direct current, alternating current, or pulsed voltage.

[0017] The beneficial effects of the present invention: It fills the blank of the quantitative evaluation method for the HCD effect of small-sized amorphous oxide semiconductor devices, and provides an important reference for the design of DRAM array circuits based on amorphous oxide semiconductors. Description of the Drawings

[0018] Figure 1 Shows an amorphous oxide semiconductor transistor device to be measured with a back-gate structure, where 1 is the substrate, 2 is the back-gate electrode, 3 is the high-κ dielectric layer, 4 is the channel layer, 5 is the source electrode, and 6 is the drain electrode. A drain-source voltage V is applied between the source and drain electrodes ds , and a gate-source voltage V is applied between the gate and source electrodes gs .

[0019] Figure 2 Shows the waveforms of V gs and V ds in the i-th "pressure application - measurement" cycle of the reliability test using DC pressure application in a specific embodiment of the present invention, where (a) shows the corresponding waveform of the HCD group, and (b) shows the corresponding waveform of the BTI group

[0020] Figure 3 Shows the threshold voltage extraction process of the device after pressure application and the test results under different conditions in a specific embodiment of the present invention. Among them, (a) shows the transfer characteristic curves of the device after different pressure application times under the same test conditions, and the gate-source voltage V d when I th reaches the threshold current I gs is extracted from each transfer characteristic curve, which is the threshold voltage of the corresponding transfer characteristic curve; (b) shows the relationship between the change in threshold voltage and the pressure application time under different test conditions

[0021] Figure 4 Shows the process of decoupling the thermal effect in a specific embodiment of the present invention Detailed Embodiments

[0022] The following describes the method for decoupling the thermal effect of an amorphous oxide semiconductor transistor based on HCD testing provided by the present invention with reference to the drawings. In the following description, many details are elaborated to fully understand the present invention, but the present invention can be implemented in many other ways different from the description. In summary, the present invention is not limited by the following disclosed embodiments

[0023] As Figure 1 shown, in a specific embodiment of the present invention, taking a back-gate amorphous oxide semiconductor transistor device as an example, an HCD test is performed on the amorphous oxide semiconductor transistor device to be measured, that is, V is applied between the gate and source of the back-gate amorphous oxide semiconductor transistor device gs , and V is applied between the drain and source ds .

[0024] The method for decoupling the thermal effect of the amorphous oxide semiconductor transistor of the present invention specifically includes the following steps

[0025] In step S01, the field effect transistors to be tested are divided into multiple test batches. The present invention does not limit the division method of the test batches. The transistors to be tested in the same test batch need to be divided into an HCD group and a BTI group. For example, the transistors to be tested in the same test batch can be evenly divided into the HCD group and the BTI group. The present invention also does not limit the division method of the HCD and BTI groups.

[0026] In step S02, all devices are subjected to the HCD test of "applying pressure - measuring - applying pressure -... - applying pressure - measuring". The test conditions of devices in different test batches are different. The test conditions include temperature, humidity, bending stress, and the peak value, frequency, and duty cycle of V gs and V ds . For example, in the pressure application stage, a DC waveform is used, and the temperature of the device to be tested is changed. During the pressure application stage, V ds and V gs are applied to the device.

[0027] During the pressure application stage of all devices in each test batch, except for the V ds waveform, other test conditions are the same. That is, V ds >0 in the pressure application stage of the HCD group, while V ds =0 in the BTI group. The waveforms of the two groups during a single "applying pressure - measuring" process are as shown in Figure 2 . Among them, Figure (a) is the waveform of the HCD group, and V ds >0; while Figure (b) is the waveform of the BTI group, and V ds =0.

[0028] In step S03, transfer characteristic curves are plotted based on the electrical parameters of the devices to be tested under each test condition, and the threshold voltage of the device after applying pressure is extracted. Taking the extraction by the fixed - current method of the threshold voltage as an example, Figure 3 (a) shows the transfer characteristic curves of the devices in the HCD group after different pressure application times under the same test conditions. The gate - source voltage V d when I th reaches the threshold current I gs is extracted from each transfer characteristic curve, which is the threshold voltage of the corresponding transfer characteristic curve. Figure 3 (b) shows the relationship between the change in the threshold voltage and the pressure application time under different test conditions in the HCD test.

[0029] In step S04, the change amounts of the threshold voltages of the HCD group and the BTI group during the test time are extracted through the following formula:

[0030] ΔV th,热效应 =ΔV th,HCD -ΔV th,BTI

[0031] As shown inFigure 4 As shown, the change in the threshold voltage caused by the thermal effect of the device is decoupled from the HCD test results. Although the overall HCD test results of the device under test meet the failure criteria within the test time range, by decoupling the thermal effect using the present invention, it is possible to effectively determine that the dominant effect in the HCD test results of the device is the BTI effect.

[0032] Although the embodiments of the present invention have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions, and variations can be made to the embodiments without departing from the principles and spirit of the present invention. The scope of the present invention is defined by the claims and their equivalents.

Claims

1. A method for decoupling thermal effects in HCD testing of an amorphous oxide semiconductor transistor, characterized in that: The specific steps include: 1) selecting a plurality of amorphous oxide semiconductor transistors of the same type as devices to be tested, dividing the devices to be tested into several test batches, and dividing the devices in each test batch into an HCD group and a BTI group; 2) Performing a "stress-measure-stress-…-stress-measure" HCD test on the device under test, wherein the stress is to apply a drain-source voltage V between the source and drain electrodes of the device respectively. ds , a gate-source voltage V is applied between the gate-source electrodes gs ; Different test batches of devices are subjected to different test conditions, including temperature, humidity, bending stress and V gs With V ds The peak value, frequency and duty cycle of each test batch are the same for all devices, except that the HCD group is under stress during the V ds >0, while BTI group V ds =0; 3) Extract the test results of the device under test in step 2), draw the transfer characteristic curve according to the electrical parameters of the device after pressure under each test condition, extract the threshold voltage change of the HCD group device after pressure and the threshold voltage change of the BTI group device after pressure, and obtain the threshold voltage change caused by the thermal effect of the device under test through the following formula: ΔV th,热效应 =ΔV th,HCD -ΔV th,BTI 。 2. The method for decoupling thermal effects in HCD testing of an amorphous oxide semiconductor transistor according to claim 1, characterized in that: The electrical parameters include V th ,I on , SS, g m ,DIBL or I off .

3. The method for decoupling thermal effects in HCD testing of an amorphous oxide semiconductor transistor according to claim 1, characterized in that: The amorphous oxide semiconductor transistor device is a back gate structure, a top gate structure, a double gate structure, a three-dimensional fin-type gate structure, a surround gate structure, a ring channel structure, a stacked nanosheet structure or a vertical channel structure.

4. The method for decoupling thermal effects in HCD testing of an amorphous oxide semiconductor transistor according to claim 4, characterized in that: The channel layer of the amorphous oxide semiconductor transistor device is ITO, In2O3, IGZO, IAZO, ITZO, CAAC-IGZO, IZO, ZnO, IWO, ITWO or a multi-doped or composite stacked channel oxide semiconductor based on the above materials.

5. The method for decoupling thermal effects in HCD testing of an amorphous oxide semiconductor transistor according to claim 4, characterized in that: The channel layer of the amorphous oxide semiconductor transistor device has a channel length of 5 to 10000 nm and a channel width of 10 to 10000 nm.

6. The method for decoupling thermal effects in HCD testing of an amorphous oxide semiconductor transistor according to claim 1, characterized in that: The number of devices in the HCD group and the BTI group in the test batch both exceeds 100.

7. The method for decoupling thermal effects in HCD testing of an amorphous oxide semiconductor transistor according to claim 1, characterized in that: The pressure is applied by applying direct current, alternating current or pulse voltage.

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