Intelligent test management system and method for circuit board

Abstract

The invention relates to the technical field of circuit board performance detection, in particular to an intelligent test management system and method for a circuit board. The method comprises the following steps: continuously monitoring the current conduction amount of the hole site of the circuit board; when it is detected that the current conduction amount is lower than a preset current conduction amount threshold value, it is judged that the current conduction state of the hole site is abnormal, and abnormal state time and abnormal initial site coordinates are recorded; acquiring a circuit board hole site image according to the abnormal initial site coordinate; and identifying hole site internal characteristics of the circuit board hole site image, extracting a defect area of the hole site internal characteristics, and marking the defect area as a hole site potential defect area. Through the data processing technology, the laser scanning technology and the image detection technology, abnormal current conduction judgment on the hole site of the circuit board is achieved, the defect area image of the abnormal hole site of the circuit board is recognized, the defect optimization scheme of the circuit board is determined, and therefore the accuracy of circuit board testing is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of printed circuit board performance detection, and particularly to an intelligent test management system and method for printed circuit boards. Background Art

[0002] A printed circuit board (PCB for short) is a support for electronic components and also a hardware carrier for the electrical connection of electronic components. In the early days, the testing of printed circuit boards mainly relied on manual inspection and simple electrical testing equipment, with low efficiency and easy to make mistakes. With the development of electronic technology, the bed-of-nails in-line testing technology emerged. By using a special bed-of-nails to contact the components on the printed circuit board for testing, problems such as missing components, mis-mounted components, and parameter deviations can be quickly detected. Traditional printed circuit board testing methods usually cannot monitor the current conduction amount of the holes on the printed circuit board in real time and continuously, and can only perform static or stage-by-stage detection. Once the current conduction of the holes on the printed circuit board is abnormal, it is difficult to quickly and accurately locate the initial abnormal site, resulting in low fault troubleshooting efficiency. Although the existing printed circuit board testing uses automatic optical inspection (AOI) technology to detect the appearance defects of the printed circuit board, the ability to identify the internal features of the holes is limited, and it is difficult to accurately extract the defective areas inside the holes, and it is easy to miss detection or misjudgment. Summary of the Invention

[0003] Based on this, it is necessary to provide an intelligent test management system and method for printed circuit boards to solve at least one of the above technical problems.

[0004] To achieve the above object, an intelligent test management method for printed circuit boards, the method includes the following steps: Step S1: Continuously monitor the current conduction amount of the holes on the printed circuit board; when it is detected that the current conduction amount is lower than the preset current conduction amount threshold, it is determined as the abnormal state of the current conduction of the holes, and the abnormal state time and the coordinates of the initial abnormal site are recorded; Step S2: Obtain the printed circuit board hole image according to the coordinates of the initial abnormal site; identify the internal features of the holes in the printed circuit board hole image, extract the defective areas of the internal features of the holes, and mark them as the potential defective areas of the holes; Step S3: If the abnormal state time is greater than the preset abnormal state duration, perform laser detection on the potential defective areas of the holes to generate defective laser detection data; perform structural topology recognition on the defective laser detection data to obtain defective structural topology data; determine the printed circuit board defect optimization plan based on the defective structural topology data; Step S4: Real-time monitor the current value of the holes on the printed circuit board. When the current value of the holes on the printed circuit board is lower than the preset current conduction amount threshold again, obtain the real-time abnormal site coordinates; when the real-time abnormal site coordinates match the coordinates of the initial abnormal site, perform optimization and repair management on the printed circuit board according to the printed circuit board defect optimization plan.

[0005] The present invention continuously monitors the current conduction amount of the via holes on the circuit board. When the current conduction amount is lower than the preset current conduction amount threshold, it can accurately determine the abnormal state of the via hole current conduction, and record the abnormal state time and the coordinates of the abnormal initial site. This precise positioning and recording function ensures the timely discovery and detailed recording of the abnormal conditions of the via holes on the circuit board, providing an accurate basis for subsequent detection and repair; obtaining the circuit board via hole image according to the coordinates of the abnormal initial site, identifying the internal features of the via hole and extracting the defective area, and marking it as the potential defective area of the via hole. This process realizes the rapid identification and positioning of potential internal defects of the circuit board via holes, improves the detection efficiency, avoids misjudgment of normal areas, and ensures the accuracy of detection; when the abnormal state time is greater than the preset abnormal state duration, laser detection is performed on the potential defective area of the via hole to generate defective laser detection data. By performing structural topology identification on the defective laser detection data, defective structure topology data is obtained, and based on this data, an optimization scheme for circuit board defects is determined. This scheme can formulate targeted repair measures according to the actual defect situation to ensure the scientificity and effectiveness of the repair; continuously monitor the current value of the circuit board via holes in real time. When the current value of the circuit board via hole is lower than the preset current conduction amount threshold again, obtain the real-time abnormal site coordinates. If the real-time abnormal site coordinates match the abnormal initial site coordinates, optimize and repair the management of the circuit board according to the circuit board defect optimization scheme. This real-time monitoring and repair management mechanism can effectively prevent the further deterioration of the circuit board via hole defects, extend the service life of the circuit board, and improve the reliability and stability of the circuit board. Therefore, the present invention realizes the judgment of abnormal current conduction of the circuit board via holes through data processing technology, laser scanning technology and image detection technology, identifies the defective area image of the abnormal via holes on the circuit board, determines the optimization scheme for circuit board defects, thereby improving the accuracy of circuit board testing.

[0006] Preferably, step S1 includes the following steps: Step S11: Current sensors are respectively arranged at the power input terminal via holes and the power distribution node via holes of the circuit board, and continuous sampling of the current conduction amount is carried out according to a sampling period of 1 millisecond to 100 milliseconds, and the duration of each sampling is 10 microseconds to 100 microseconds to obtain current monitoring data; Step S12: The current monitoring data is processed in segments according to the time sequence, each segment contains 50 to 200 sampling points, and the average value, maximum value and minimum value of each segment of data are calculated as the current conduction amount; Step S13: When it is detected that the current conduction amount is lower than the preset current conduction amount threshold, it is determined that the via hole current conduction is in an abnormal state; Step S14: Record the abnormal detection time, data acquisition time and abnormal confirmation time when the abnormal state occurs to obtain the abnormal state time; Step S15: Mark the abnormal conduction sites on the circuit board according to the abnormal state of hole current conduction to obtain the coordinates of the initial abnormal sites.

[0007] In the present invention, current sensors are respectively arranged at the hole positions of the power input end and the power distribution node hole position of the circuit board, which can specifically monitor the key current transmission nodes of the circuit board to ensure comprehensive monitoring of the current conduction state; continuous sampling of the current conduction amount is carried out according to the sampling period of 1 millisecond to 100 milliseconds and the sampling duration of 10 microseconds to 100 microseconds, which can capture the transient changes of the current with high time resolution, ensure the integrity and accuracy of the current monitoring data, and provide a reliable basis for subsequent analysis; the current monitoring data is processed in segments according to the time sequence, each segment contains 50 to 200 sampling points, and the average value, maximum value and minimum value of each segment of data are calculated as the current conduction amount, which can effectively simplify the data processing process, extract key features, reduce data complexity, while retaining the key information of current changes and improving data processing efficiency; by comparing the calculated current conduction amount with the preset current conduction amount threshold, when it is detected that the current conduction amount is lower than the threshold, it is determined as the abnormal state of hole current conduction. This threshold-based determination method can quickly and accurately identify the abnormal current conduction situation of the circuit board holes, avoid missed detection and misjudgment, and ensure the timely discovery of abnormal states; record the abnormal detection time, data acquisition time and abnormal confirmation time when the abnormal state occurs, which can accurately determine the time point and duration of the abnormal occurrence, provide an accurate time reference for subsequent fault analysis and location, and help quickly evaluate the severity and influence range of the abnormality; mark the abnormal conduction sites on the circuit board according to the abnormal state of hole current conduction to obtain the coordinates of the initial abnormal sites, which can accurately determine the specific location where the abnormality occurs, provide accurate spatial positioning for subsequent defect detection and repair, and facilitate quickly finding the root cause of the problem and taking targeted measures.

[0008] Preferably, the obtaining the circuit board hole position image according to the coordinates of the initial abnormal sites in step S2 includes: Place the circuit board on the detection platform, and align the lens of the optical imaging device with the area where the initial abnormal site of the circuit board is located according to the coordinates of the initial abnormal sites; Start the optical imaging device, and sequentially take pictures of the area where the initial abnormal site of the circuit board is located from the front, 45-degree angle and 90-degree angle. When taking pictures from the front, the lens aperture size is set to F4.1 - F5.6; when taking pictures from the 45-degree angle, the lens aperture size is set to F5.6 - F8; when taking pictures from the 90-degree angle, the lens aperture size is set to F8 - F11; Collect the initial image of the circuit board hole position; convert the initial image of the circuit board hole position into a grayscale image, and remove the hole position noise in the image to obtain the circuit board hole position image.

[0009] The present invention realizes the accurate positioning and focusing of the abnormal area of the circuit board by placing the circuit board on the detection platform and aligning the lens of the optical imaging device with the area where the initial abnormal site of the circuit board is located according to the coordinates of the initial abnormal site, ensuring the accuracy and pertinence of imaging and providing a clear image basis for subsequent image analysis. The optical imaging device is started, and the area where the initial abnormal site of the circuit board is located is photographed successively from the front, 45-degree angle, and 90-degree angle, and the corresponding lens aperture size is set according to different shooting angles (the aperture for front shooting is F4.1 - F5.6, the aperture for 45-degree angle shooting is F5.6 - F8, and the aperture for 90-degree angle shooting is F8 - F11). This multi-angle shooting method combined with the optimized aperture setting can comprehensively capture the detailed features of the abnormal area of the circuit board, while ensuring that the images taken at different angles have appropriate depth of field and clarity, avoiding image blurring or detail loss caused by improper aperture setting. After collecting the initial image of the circuit board hole positions, it is converted into a grayscale image and the noise of the image hole positions is removed to obtain the circuit board hole position image. Grayscale conversion can simplify the image data and reduce the complexity of subsequent processing; removing noise further improves the image quality and enhances the recognizability of the hole position features in the image, providing high-quality image input for subsequent defect detection and analysis.

[0010] Preferably, the defect areas for identifying the internal features of the hole positions in the circuit board hole position image and extracting the internal features of the hole positions include: Traverse the pixel points of the circuit board hole position image and extract the pixel values of the pixel points; Perform binary processing on the circuit board hole position image according to the pixel values. If the pixel value is 0 - 125, it is classified as the hole position area; if the pixel value is 126 - 255, it is classified as the non-hole position area; Determine the flatness and thickness of the circuit board for the non-hole position area; identify the hole position contour boundary of the hole position area according to the flatness of the circuit board; Measure the hole depth of the circuit board based on the thickness of the circuit board; measure the diameter of the largest inscribed circle of the hole position contour boundary to obtain the hole diameter of the circuit board; identify the texture degree of the hole wall of the hole position contour boundary to obtain the hole wall roughness; Combine the hole depth of the circuit board, the hole diameter of the circuit board, and the hole wall roughness into the internal features of the hole position; Extract the defect areas where the internal features of the hole positions are located and mark them as potential defect areas of the hole positions.

[0011] The present invention traverses pixel points of the hole position image on the circuit board and extracts pixel values, and performs binarization processing according to the pixel value range (0 - 125 is the hole position area, 126 - 255 is the non-hole position area), which can accurately divide the image into the hole position area and the non-hole position area. This processing method effectively simplifies the complexity of image analysis and provides a clear regional division basis for subsequent feature extraction; for the non-hole position area, the flatness and thickness of the circuit board are determined, which can comprehensively evaluate the physical state of the non-hole position area. The flatness and thickness information are important parameters for analyzing the overall quality of the circuit board and provide accurate background information for subsequent hole position feature extraction; according to the flatness of the circuit board, the hole position contour boundary of the hole position area is identified, and based on the thickness of the circuit board, the hole depth of the circuit board is measured, which can accurately extract the geometric features of the hole position. At the same time, measuring the diameter of the largest inscribed circle of the hole position contour boundary to obtain the aperture of the circuit board, and identifying the texture degree of the hole wall to obtain the roughness of the hole wall, these operations provide important data for comprehensively evaluating the quality of the hole position; combining the hole depth, aperture and hole wall roughness of the circuit board into the internal features of the hole position, and extracting the defective area where the internal features of the hole position are located, which is marked as the potential defective area of the hole position. This integration and marking method can effectively identify the potential defects of the hole position and provide a clear target area for subsequent defect analysis and repair.

[0012] Preferably, in step S3, if the abnormal state time is greater than the preset abnormal state duration, the laser detection of the potential defective area of the hole position includes: If the abnormal state time is greater than the preset abnormal state duration, the laser camera of the laser detection device is aligned with the potential defective area of the hole position; The laser detection device is started, and the emission wavelength parameter is set to 532 nanometers to 1064 nanometers, the power range parameter is set to 10 milliwatts to 100 milliwatts, the emission laser beam time parameter is set to 10 milliseconds to 100 milliseconds, and the emission frequency is 1 hertz to 10 hertz; The laser signal reflected from the potential defective area of the hole position is received, and the signal intensity and reflection time of the laser signal are extracted; The laser signal is fitted into defective laser detection data according to the signal intensity and reflection time.

[0013] When the abnormal state time is greater than the preset abnormal state duration in the present invention, the laser camera of the laser detection device is aligned with the potential defect area of the hole position, ensuring that the laser detection can accurately focus on the area where defects may exist, improving the detection efficiency and accuracy; the laser detection device is started, and the emission wavelength parameter is set to 532 nanometers to 1064 nanometers, the power range parameter is set to 10 milliwatts to 100 milliwatts, the emission laser beam time parameter is set to 10 milliseconds to 100 milliseconds, and the emission frequency is set to 1 hertz to 10 hertz. The optimized configuration of these parameters can ensure that the laser beam has sufficient energy and appropriate wavelength during the penetration and reflection processes to adapt to the hole position detection requirements of different materials and depths, while avoiding unnecessary damage to the circuit board; the laser signal reflected from the potential defect area of the hole position is received, and the signal intensity and reflection time of the laser signal are extracted. The signal intensity and reflection time are key characteristic parameters in laser detection, which can reflect the physical state and defect characteristics inside the hole position and provide an important basis for subsequent data analysis; the laser signal is fitted into defect laser detection data according to the signal intensity and reflection time, which can convert the collected original signal into detection data with clear physical meaning, facilitating further analysis and processing. This data fitting method can effectively extract defect characteristics and provide accurate data support for subsequent structure topology recognition and defect assessment.

[0014] Preferably, the structure topology recognition of the defect laser detection data in step S3 includes: Determining the coordinates of the defective hole position for the defect laser detection data; Measuring the distance between the hole position and the adjacent component pins according to the coordinates of the defective hole position to obtain the hole position component pin distance; Measuring the distance between the hole position and the edge of the circuit board according to the coordinates of the defective hole position to obtain the hole position edge distance; Measuring the perpendicularity deviation and the concentricity deviation of the hole wall of the hole position according to the coordinates of the defective hole position; Detecting the conductive connection relationship of the hole position based on the hole position component pin distance and the hole position edge distance; detecting the hole position stack-up misalignment structure based on the perpendicularity deviation of the hole position and the concentricity deviation of the hole wall; Conducting structure topology recognition on the defect laser detection data through the conductive connection relationship of the hole position and the hole position stack-up misalignment structure to obtain defect structure topology data.

[0015] The present invention determines the coordinates of the defect hole positions for the defect laser detection data, which can accurately locate the specific positions of the defects in the hole positions, providing an accurate spatial reference for subsequent measurement and analysis; measures the distance between the hole positions and the adjacent component pins according to the defect hole position coordinates to obtain the pin spacing of the hole positions and components, which can evaluate the relative positional relationship between the hole positions and the surrounding components, ensuring a reasonable spacing between the component pins and the hole positions and avoiding problems such as short circuits or poor contacts caused by insufficient spacing; measures the distance between the hole positions and the edge of the circuit board according to the defect hole position coordinates to obtain the edge spacing of the hole positions, which can evaluate the relative position of the hole positions and the edge of the circuit board, ensuring the accuracy of the hole positions in the design and manufacturing processes and avoiding circuit board structure problems caused by position deviation; measures the perpendicularity deviation and the concentricity deviation of the hole wall of the hole positions according to the defect hole position coordinates, which can accurately evaluate the geometric accuracy of the hole positions, detect problems of perpendicularity and concentricity that may occur in the manufacturing process of the hole positions, and provide an important basis for subsequent defect analysis; detects the conductive connection relationship of the hole positions based on the pin spacing of the hole positions and the edge spacing of the hole positions, which can accurately judge the conductive connection state between the hole positions and the surrounding components, ensuring that the electrical performance of the circuit board meets the design requirements; detects the stacked layer misalignment structure of the hole positions based on the perpendicularity deviation and the concentricity deviation of the hole wall, which can identify the stacked layer misalignment of the hole positions in the multi-layer circuit board, ensuring the accuracy of the interlayer connection of the hole positions and avoiding electrical failures caused by stacked layer misalignment; performs structure topology recognition on the defect laser detection data through the conductive connection relationship of the hole positions and the stacked layer misalignment structure of the hole positions to obtain the defect structure topology data, which can comprehensively analyze the structural characteristics and topological relationships of the defects, improve the description of the defect data, and provide an accurate and comprehensive basis for subsequent defect evaluation and the formulation of repair plans.

[0016] Preferably, the step of determining the circuit board defect optimization plan based on the defect structure topology data in step S3 includes: Dividing the defect structure topology data into structure short-circuit data and structure misalignment data; Marking the short-circuit positions of the circuit board for the structure short-circuit data, determining the short-circuit influence range of the short-circuit positions of the circuit board, and generating short-circuit influence range data; detecting the affected components for the short-circuit influence range data to obtain short-circuit affected component data; Marking the misaligned areas of the circuit board for the structure misalignment data, identifying the wiring paths of the misaligned areas of the circuit board, and generating misaligned wiring path data.

[0017] The present invention divides the topological data of defect structures into structural short - circuit data and structural misalignment data, realizing the classification management of different types of defect data, facilitating subsequent targeted analysis and processing for different defect types, and improving the efficiency and accuracy of defect handling; marking the short - circuit positions on the circuit board for the structural short - circuit data can accurately locate the specific positions where the short - circuit occurs, providing a clear target for the repair of short - circuit problems; determining the short - circuit influence range for the short - circuit positions on the circuit board and generating short - circuit influence range data can comprehensively evaluate the potential influence range of the short - circuit on the circuit board, ensuring that all potentially affected areas are considered during the repair process; detecting the affected components for the short - circuit influence range data to obtain short - circuit affected component data can clearly identify the components that may be damaged or affected due to the short - circuit, providing an important basis for subsequent component detection and repair, and avoiding further damage caused by the short - circuit; marking the misaligned areas on the circuit board for the structural misalignment data can clearly identify the areas with misalignment problems on the circuit board, providing a clear positioning for the repair of misalignment problems; identifying the wiring paths in the misaligned areas of the circuit board and generating misaligned wiring path data can accurately identify the wiring paths within the misaligned areas, providing detailed wiring information for repairing the misalignment problem, ensuring that the wiring paths can be correctly adjusted during the repair process to restore the normal function of the circuit board.

[0018] Preferably, the step of determining the circuit board defect optimization plan based on the topological data of defect structures in step S3 further includes: Determining the types and quantities of components affected by the short - circuit based on the short - circuit affected component data, and repairing the component short - circuit points on the circuit board to obtain component short - circuit repair data; Determining the areas affected by the misaligned wiring based on the misaligned wiring path data, and rearranging the wiring paths in the misaligned wiring areas of the circuit board to obtain optimized wiring path data; Integrating the component short - circuit repair data and the optimized wiring path data to obtain the circuit board defect optimization plan.

[0019] Based on the data of components affected by short circuits, the present invention determines the types and quantities of components affected by short circuits, can clearly identify the specific scope of the impact of short circuits on the components on the circuit board, and provides an accurate target for the repair work; repairs the short-circuit points of the components on the circuit board to obtain the component short-circuit repair data, can specifically solve the short-circuit problem, restore the normal electrical connection of the components, and ensure the restoration of the function of the circuit board; determines the area affected by misaligned wiring based on the misaligned wiring path data, can accurately identify the wiring area affected by misalignment in the circuit board; rearranges the wiring paths in the misaligned wiring area of the circuit board to obtain the optimized wiring path data, can effectively adjust the wiring paths, solve the electrical connection problems caused by misalignment, optimize the wiring structure of the circuit board, and improve the reliability and performance of the circuit board; integrates the component short-circuit repair data and the optimized wiring path data to obtain an optimized solution for circuit board defects, can comprehensively consider the results of short-circuit repair and wiring optimization, and form a comprehensive repair plan. This integrated solution can ensure that after the circuit board is repaired, not only the current defect problems are solved, but also the overall structure is optimized, and the reliability and service life of the circuit board are improved.

[0020] Preferably, step S4 includes the following steps: Step S41: Monitor the current value of the circuit board hole position in real time. When the current value of the circuit board hole position is lower than the preset current conduction threshold again, trigger the switch of the circuit board positioning and acquisition device; Step S42: Use the circuit board positioning and acquisition device to perform real-time detection of the edge of the circuit board, and extract the real-time edge of the circuit board; Step S43: Measure the X coordinate value and Y coordinate value of the abnormal hole position of the circuit board in the X-axis and Y-axis directions parallel to the real-time edge of the circuit board; measure the Z coordinate value of the abnormal hole position of the circuit board in the Z-axis direction perpendicular to the real-time edge of the circuit board; Step S44: Based on the X coordinate value, Y coordinate value, and Z coordinate value, obtain the real-time abnormal site coordinates; Step S45: When the real-time abnormal site coordinates match the initial abnormal site coordinates, perform optimized repair management on the circuit board according to the optimized solution for circuit board defects.

[0021] The present invention monitors the current value of the via positions on the circuit board in real time. When the current value is lower than the preset current conduction threshold again, the switch of the circuit board positioning and acquisition device is triggered. This real-time monitoring and triggering mechanism can promptly detect the abnormal state of the via positions on the circuit board, ensuring that the subsequent detection process is quickly initiated when the abnormal situation occurs again, improving the detection efficiency and response speed. The circuit board positioning and acquisition device performs real-time detection of the circuit board edge, extracts the real-time edge of the circuit board, providing an accurate reference benchmark for subsequent coordinate calculation. The X coordinate value and Y coordinate value of the abnormal via position on the circuit board are calculated in the X-axis and Y-axis directions parallel to the real-time edge of the circuit board, and the Z coordinate value of the abnormal via position on the circuit board is calculated in the Z-axis direction perpendicular to the real-time edge of the circuit board. This coordinate calculation method can accurately determine the three-dimensional spatial position of the abnormal via position, ensuring the accuracy of positioning. Based on the X coordinate value, Y coordinate value, and Z coordinate value, the real-time abnormal site coordinates are obtained. In this way, the coordinate information of the abnormal via position can be obtained in real time and accurately, providing an accurate positioning basis for subsequent repair management. When the real-time abnormal site coordinates match the abnormal initial site coordinates, the circuit board is optimized and repaired according to the circuit board defect optimization plan. This repair management method based on coordinate matching can ensure that the repair measures are accurately applied to the initially detected abnormal area, avoiding misoperation, improving the accuracy and reliability of repair, and effectively solving the defect problem of the circuit board.

[0022] This specification also provides a circuit board intelligent test management system for implementing the circuit board intelligent test management method as described above. The circuit board intelligent test management system includes: An initial abnormal monitoring module for continuously monitoring the current conduction of the via positions on the circuit board. When it detects that the current conduction is lower than the preset current conduction threshold, it determines that the via current conduction is in an abnormal state and records the abnormal state time and the abnormal initial site coordinates. A via image recognition module for obtaining the via position image on the circuit board according to the abnormal initial site coordinates. It recognizes the internal features of the via in the via position image, extracts the defective area of the internal features of the via, and marks it as the via potential defect area. A defect structure topology detection module for, if the abnormal state time is greater than the preset abnormal state duration, performing laser detection on the via potential defect area to generate defect laser detection data. It performs structure topology recognition on the defect laser detection data to obtain defect structure topology data. Based on the defect structure topology data, it determines the circuit board defect optimization plan. A circuit board optimization and repair module for monitoring the current value of the via positions on the circuit board in real time. When the current value of the via positions on the circuit board is lower than the preset current conduction threshold again, it obtains the real-time abnormal site coordinates. When the real-time abnormal site coordinates match the abnormal initial site coordinates, it optimizes and repairs the circuit board according to the circuit board defect optimization plan.

[0023] Through the collaborative work of the initial anomaly monitoring module, hole position image recognition module, defect structure topology detection module, and circuit board optimization and repair module, the present invention realizes the full-process automated management from circuit board hole position anomaly monitoring, defect identification, structure topology detection to optimization and repair. The initial anomaly monitoring module can continuously monitor the current conduction amount of the circuit board hole positions, accurately determine the abnormal state, and record the abnormal time and the initial site coordinates, providing accurate information for subsequent processing. The hole position image recognition module obtains the hole position image according to the abnormal initial site coordinates, efficiently identifies and extracts the defective areas of the internal features of the hole positions, and marks them as potential defective areas. The defect structure topology detection module conducts laser detection and structure topology recognition on the potential defective areas, generates defect laser detection data, and determines the optimization and repair plan to ensure the scientificity and effectiveness of defect handling. The circuit board optimization and repair module monitors the hole position current value in real time. When the current value is lower than the threshold again, it obtains the real-time abnormal site coordinates and matches them with the initial site coordinates, and conducts repair management according to the optimization plan, effectively avoiding the deterioration of problems and extending the service life of the circuit board. This system significantly improves the efficiency and accuracy of circuit board test management, reduces manual intervention, reduces the risk of operation errors, simultaneously improves the production efficiency and quality control level, and reduces production delays caused by defects. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a schematic diagram of the step flow of a method for intelligent test management of a circuit board; Figure 2 is Figure 1 a detailed implementation step flow diagram of step S1 in Figure 3 is Figure 1 a detailed implementation step flow diagram of step S4 in The realization, functional features, and advantages of the object of the present invention will be further described with reference to the embodiments and the accompanying drawings. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0025] The technical method of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of the present invention, rather than all embodiments. All other embodiments obtained by those skilled in the art within the scope of the present invention without creative work based on the embodiments of the present invention belong to the scope of protection of the present invention.

[0026] In addition, the accompanying drawings are only schematic illustrations of the present invention and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus repeated descriptions thereof will be omitted. Some of the block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. The functional entities may be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor methods and / or microcontroller methods.

[0027] It should be understood that although the terms "first", "second", etc. may be used herein to describe various units, these units should not be limited by these terms. These terms are only used to distinguish one unit from another. For example, without departing from the scope of the exemplary embodiments, the first unit may be referred to as the second unit, and similarly the second unit may be referred to as the first unit. The term "and / or" used herein includes any and all combinations of one or more of the listed associated items.

[0028] To achieve the above object, please refer to Figures 1 to 3 , a method for intelligent test management of a circuit board, the method comprising the following steps: Step S1: Continuously monitor the current conduction amount of the circuit board hole positions; when it is detected that the current conduction amount is lower than the preset current conduction amount threshold, it is determined that the hole position current conduction is in an abnormal state, and the abnormal state time and the abnormal initial site coordinates are recorded; Step S2: Obtain the circuit board hole position image according to the abnormal initial site coordinates; identify the internal features of the hole positions in the circuit board hole position image, extract the defective areas of the internal features of the hole positions, and mark them as potential defective areas of the hole positions; Step S3: If the abnormal state time is greater than the preset abnormal state duration, perform laser detection on the potential defective areas of the hole positions to generate defective laser detection data; perform structural topology recognition on the defective laser detection data to obtain defective structural topology data; determine the circuit board defect optimization scheme based on the defective structural topology data; Step S4: Real-time monitor the current value of the circuit board hole positions. When the current value of the circuit board hole positions is lower than the preset current conduction amount threshold again, obtain the real-time abnormal site coordinates; when the real-time abnormal site coordinates match the abnormal initial site coordinates, optimize and repair the circuit board according to the circuit board defect optimization scheme.

[0029] The present invention continuously monitors the current conduction amount of the holes on the circuit board. When the current conduction amount is lower than the preset current conduction amount threshold, it can accurately determine the abnormal state of the current conduction of the holes, and record the abnormal state time and the coordinates of the abnormal initial site. This precise positioning and recording function ensures the timely discovery and detailed recording of the abnormal conditions of the holes on the circuit board, providing an accurate basis for subsequent detection and repair; obtaining the circuit board hole image according to the coordinates of the abnormal initial site, identifying the internal features of the hole and extracting the defective area, which is marked as the potential defective area of the hole. This process realizes the rapid identification and positioning of potential internal defects of the holes on the circuit board, improves the detection efficiency, avoids misjudgment of normal areas, and ensures the accuracy of detection; when the abnormal state time is greater than the preset abnormal state duration, laser detection is performed on the potential defective area of the hole to generate defective laser detection data. By performing structural topology recognition on the defective laser detection data, defective structure topology data is obtained, and based on this data, an optimization scheme for the circuit board defect is determined. This scheme can formulate targeted repair measures according to the actual defect situation to ensure the scientificity and effectiveness of the repair; continuously monitor the current value of the circuit board holes in real time. When the current value of the circuit board holes is lower than the preset current conduction amount threshold again, obtain the real-time abnormal site coordinates. If the real-time abnormal site coordinates match the abnormal initial site coordinates, optimize and repair the management of the circuit board according to the circuit board defect optimization scheme. This real-time monitoring and repair management mechanism can effectively prevent the further deterioration of the defects of the circuit board holes, extend the service life of the circuit board, and improve the reliability and stability of the circuit board. Therefore, the present invention realizes the judgment of abnormal current conduction of the circuit board holes through data processing technology, laser scanning technology and image detection technology, identifies the defective area image of the abnormal holes on the circuit board, and determines the optimization scheme for the circuit board defects, thereby improving the accuracy of the circuit board test.

[0030] In an embodiment of the present invention, refer to Figure 1 As shown, it is a schematic diagram of the step flow of a method for intelligent test management of a circuit board according to the present invention. In this example, the method for intelligent test management of a circuit board includes the following steps: Step S1: Continuously monitor the current conduction amount of the holes on the circuit board; when it is detected that the current conduction amount is lower than the preset current conduction amount threshold, it is determined that the current conduction of the hole is in an abnormal state, and the abnormal state time and the coordinates of the abnormal initial site are recorded; In the embodiments of the present invention, the current detection chip is connected in series in the circuit and can directly measure the current passing through the via holes of the circuit board. This chip has the characteristics of high precision and low noise and can accurately detect tiny current changes. First, the current detection chip is connected in series with the via hole circuit of the circuit board to ensure that the current can be accurately measured when passing through the chip. The output terminal of the current detection chip is connected to an analog-to-digital converter (ADC) for converting the analog current signal into a digital signal. The sampling rate of the analog-to-digital converter is set to 1000 times per second to ensure that the current changes can be captured in real time. In the system initialization stage, a preset current conduction amount threshold is set, denoted as I_threshold. This threshold is calibrated according to the current range of the via holes when the circuit board is working normally, for example, set to 10 milliamperes. The system compares the real-time collected current value I_measured with I_threshold through a simple comparison logic. When I_measured is lower than I_threshold, the system determines that the current conduction of this via hole is in an abnormal state. At this time, the system starts a timer to record the duration T_abnormal of the abnormal state. At the same time, through a built-in coordinate positioning module, the initial coordinate position (X_abnormal, Y_abnormal) of this via hole is obtained. The coordinate positioning module accurately calculates the coordinates of the abnormal via hole by combining the pre-set layout diagram of the circuit board via holes and the position information of the current detection chip. The system stores the duration T_abnormal of the abnormal state and the initial coordinates of the abnormal site (X_abnormal, Y_abnormal) in the local memory for subsequent analysis and processing. The entire monitoring process is implemented through a simple loop control logic to ensure continuous monitoring of the current conduction amount of the circuit board via holes and timely record relevant information when an abnormality occurs.

[0031] Step S2: Obtain the circuit board via hole image according to the initial coordinates of the abnormal site; identify the internal features of the via holes in the circuit board via hole image, extract the defective areas of the internal features of the via holes, and mark them as potential defective areas of the via holes; In the embodiments of the present invention, an industrial camera with high resolution is used to collect images of the hole positions on the circuit board. The pixel resolution of the industrial camera is set to 4000×4000 to ensure that the details of the hole positions can be clearly captured. The aperture size of the camera is adjusted to F8, and the shutter speed is set to 1 / 200 second to balance the light conditions and image clarity. The focal length of the camera lens is selected as 50 mm to ensure that the magnification ratio of the hole position image is appropriate, which can completely cover the hole position area and will not be over-magnified to cause distortion. The collected images of the hole positions on the circuit board are transmitted to the image processing system. The system first performs grayscale processing on the images, converting the RGB color images into grayscale images to reduce the data volume and simplify the subsequent processing process. After grayscale processing, the images are binarized. The threshold is set to 128. Pixel points with grayscale values higher than 128 are set to white (value 255), and pixel points lower than or equal to 128 are set to black (value 0), so as to highlight the characteristic areas inside the hole positions. Next, the system uses an edge detection algorithm, such as the Canny algorithm, to perform edge detection on the binarized images. The low threshold of the Canny algorithm is set to 50, and the high threshold is set to 150 to accurately identify the contours and defect edges inside the hole positions. Through edge detection, the characteristic contours inside the hole positions are extracted, including structures such as hole walls and hole bottoms. Subsequently, the system analyzes the extracted characteristic features inside the hole positions to identify the defect areas. By calculating the area, shape, and texture features of the characteristic areas and comparing them with the pre-defined normal hole position characteristic templates. If the area deviation of a certain area exceeds 10%, or the shape irregularity exceeds 20%, or the similarity of the texture feature to the normal template is lower than 80%, then this area is marked as a potential defect area of the hole position. The marking process is achieved by drawing a red rectangular box on the image, and the coordinate and size information of the rectangular box are recorded in a data file for subsequent further analysis and processing.

[0032] Step S3: If the abnormal state time is greater than the preset abnormal state duration, then perform laser detection on the potential defect area of the hole position to generate defect laser detection data; perform structural topology identification on the defect laser detection data to obtain defect structural topology data; determine the circuit board defect optimization scheme based on the defect structural topology data; In the embodiment of the present invention, first, the abnormal state time T_abnormal is compared with the preset abnormal state duration T_threshold. When T_abnormal is greater than T_threshold, the laser detection device is activated to detect the potential defect area of the hole position. The laser detection device uses a laser source with a wavelength of 1064 nanometers, the laser power is set to 50 milliwatts, and the scanning speed is 100 millimeters per second to ensure that the potential defect area of the hole position can be accurately covered. The laser beam of the laser detection device is focused on the potential defect area of the hole position, and defect information is collected through laser reflection and scattering signals. During the detection process, the laser detection device scans the potential defect area point by point with a step distance of 0.1 millimeter, and simultaneously records the laser reflection intensity value I_laser of each scanning point. The generated defect laser detection data includes the coordinates (X_laser, Y_laser) of each scanning point and the corresponding reflection intensity value I_laser, and these data are stored in a data file. Subsequently, structural topology recognition is performed on the defect laser detection data. A threshold-based recognition algorithm is used, and the reflection intensity threshold I_threshold is set to 200. For the scanning points with a reflection intensity I_laser lower than I_threshold, they are identified as defect points, and their coordinates are recorded. By analyzing the spatial distribution relationship of the defect points, defect structure topology data is constructed, including the connection relationship between the defect points and the boundary information of the defect area. Based on the defect structure topology data, an optimization scheme for the circuit board defects is determined. According to the shape, size and distribution of the defect area, the hole position area that needs to be repaired or adjusted is calculated. If the area of the defect area is less than 1 square millimeter, a laser repair technology is adopted to remove excess material or fill missing material by laser ablation; if the area of the defect area is greater than 1 square millimeter, an optimization scheme of locally replacing the hole position is recommended. The specific parameters of the optimization scheme, such as the power of laser repair, the scanning path and the size range of local replacement, are accurately calculated and recorded according to the defect structure topology data Step S4: Real-time monitor the current value of the circuit board hole position. When the current value of the circuit board hole position is lower than the preset current conduction threshold again, obtain the real-time abnormal site coordinates; when the real-time abnormal site coordinates match the abnormal initial site coordinates, perform optimization repair management on the circuit board according to the circuit board defect optimization scheme.

[0033] In an embodiment of the present invention, a current detection device is used to continuously monitor the current value of the via holes on the circuit board. The current detection device adopts a high-precision Hall effect sensor with a sensitivity set to 100 mV / A, which can detect the current change of the via holes on the circuit board in real time and output the current value in milliamperes. The preset current conduction threshold I_threshold is set to 10 milliamperes. When it is detected that the current value I_current of the via holes on the circuit board is lower than I_threshold again, an abnormal detection process is triggered. After detecting an abnormality, the real-time abnormal site coordinates are obtained through a positioning system. The positioning system adopts a high-precision optical positioning technology with a positioning accuracy of ±0.05 millimeters. The positioning system quickly locates the abnormal via hole according to the abnormal signal fed back by the current detection device and obtains the real-time abnormal site coordinates (X_realtime, Y_realtime). Subsequently, the real-time abnormal site coordinates (X_realtime, Y_realtime) are compared with the abnormal initial site coordinates (X_abnormal, Y_abnormal) recorded in step S1. The comparison process is achieved by calculating the Euclidean distance between the two coordinate points. If the distance is less than the set matching threshold D_threshold (for example, 0.1 millimeter), it is determined that the real-time abnormal site matches the abnormal initial site. When the match is determined, the circuit board is optimized and repaired according to the circuit board defect optimization plan determined in step S3. If the optimization plan is laser repair, a laser repair device is started. Its laser wavelength is set to 532 nanometers, the power is 30 milliwatts, and the scanning speed is 50 millimeters per second. The defect area is repaired according to the scanning path planned in the optimization plan. During the repair process, the laser device precisely controls the emission and movement of the laser according to the shape and size of the defect area to ensure the accuracy and integrity of the repair. After the repair is completed, the current of the repaired via hole is detected again by the current detection device to verify whether the repair effect meets the requirements of the preset current conduction threshold.

[0034] As an example of the present invention, refer to Figure 2 shown, in this example, step S1 includes: Step S11: Current sensors are respectively set at the power input terminal via holes and the power distribution node via holes of the circuit board, and continuous sampling of the current conduction amount is carried out according to a sampling period of 1 millisecond to 100 milliseconds, and the duration of each sampling is 10 microseconds to 100 microseconds to obtain current monitoring data; Step S12: The current monitoring data is processed in segments according to the time sequence. Each segment contains 50 to 200 sampling points, and the average value, maximum value, and minimum value of each segment of data are calculated as the current conduction amount; Step S13: When it is detected that the current conduction amount is lower than the preset current conduction threshold, it is determined that the via hole current conduction is in an abnormal state; Step S14: Record the anomaly detection time, data acquisition time, and anomaly confirmation time when the abnormal state occurs to obtain the abnormal state time; Step S15: Mark the abnormal conduction site of the circuit board according to the abnormal state of the hole position current conduction to obtain the coordinates of the initial abnormal site.

[0035] In the embodiments of the present invention, first, high-precision current sensors are respectively installed at the power input terminal holes and power distribution node holes of the circuit board. The current sensors adopt the Hall effect principle, and their sensitivity is set to 100 mV / mA, which can convert the current signal into a voltage signal for output. The sampling period of the current sensor is set to 10 milliseconds, and the duration of each sampling is 50 microseconds. The settings of the sampling period and duration are realized through the built-in timer and trigger of the current sensor to ensure accurate acquisition of the current signal within each sampling period. The output terminal of the current sensor is connected to an analog-to-digital converter (ADC). The sampling rate of the ADC is 100,000 times per second, which can convert the analog voltage signal output by the current sensor into a digital signal to form current monitoring data. The current monitoring data is recorded in milliamperes, and the data of each sampling point includes the sampling timestamp and the corresponding current. The collected current monitoring data is processed in segments according to the time sequence. Each segment of data contains 100 sampling points, and the data processing unit performs statistical analysis on each segment of data. The data processing unit first reads all the current values in each segment of data, and then calculates the average value μ_segment, the maximum value I_max, and the minimum value I_min of each segment of data. The average value μ_segment is obtained by adding all the current values in each segment of data and then dividing by the number of sampling points (100); the maximum value I_max is found by scanning all the current values in each segment of data to find the maximum value; the minimum value I_min is found by scanning all the current values in each segment of data to find the minimum value. These three parameters are used as the current conduction amount characteristics during this time period for subsequent analysis and judgment. The system presets a current conduction amount threshold I_threshold, which is set to 15 milliamperes. The data processing unit compares the average value μ_segment of each segment of data with I_threshold. When μ_segment is lower than I_threshold, the system determines that the hole position is in an abnormal current conduction state and triggers the subsequent abnormal handling process. When an abnormal current conduction state is detected, the data processing unit records the abnormal detection time T_detect, that is, the time point when the system first determines the abnormality; records the data acquisition time T_acquire, that is, the starting acquisition time of this segment of data; and records the abnormal confirmation time T_confirm, that is, the time point when the system finally confirms the abnormality. The abnormal detection time T_detect is obtained through the internal clock of the data processing unit, accurate to the millisecond level; the data acquisition time T_acquire is obtained by reading the timestamp of the first sampling point of this segment of data; the abnormal confirmation time T_confirm is obtained through the current time of the data processing unit after confirming the abnormality.By calculating the time difference between T_confirm and T_acquire, the abnormal state time T_abnormal is obtained, with the unit of millisecond, which is used to characterize the duration of the abnormal state; according to the abnormal state of the hole position current conduction, combined with the layout information of the circuit board and the position information of the sensor, the abnormal conduction sites of the circuit board are marked. The initial coordinates of the abnormal sites are obtained through the positioning system, denoted as the abnormal initial site coordinates (X_initial, Y_initial). The positioning system determines the precise coordinates of the abnormal sites through geometric calculation based on the installation position of the current sensor and the layout diagram of the circuit board. The abnormal initial site coordinates (X_initial, Y_initial) are recorded in millimeters, and the data processing unit stores this coordinate information in the system database for subsequent further analysis and processing.

[0036] Preferably, obtaining the circuit board hole position image according to the abnormal initial site coordinates in step S2 includes: Place the circuit board on the detection platform, and align the lens of the optical imaging device with the area where the abnormal initial site of the circuit board is located according to the abnormal initial site coordinates; Start the optical imaging device, and sequentially take pictures of the area where the abnormal initial site of the circuit board is located from the front, 45-degree angle, and 90-degree angle. When taking pictures from the front, the lens aperture size is set to F4.1 - F5.6; when taking pictures from the 45-degree angle, the lens aperture size is set to F5.6 - F8; when taking pictures from the 90-degree angle, the lens aperture size is set to F8 - F11; Collect the initial circuit board hole position image; convert the initial circuit board hole position image into a grayscale image and remove the image hole position noise to obtain the circuit board hole position image.

[0037] In the embodiments of the present invention, the circuit board is placed on the fixing device of the detection platform to ensure its stable and flat position. The detection platform is equipped with a high-precision positioning system, which can accurately adjust the position of the optical imaging device according to the input coordinate information. According to the abnormal initial site coordinates (X_initial, Y_initial) recorded in step S15, the positioning system drives the lens of the optical imaging device to move above the area corresponding to the coordinates, so that the center of the lens is aligned with the area where the abnormal initial site of the circuit board is located. Start the optical imaging device and take pictures of the area where the abnormal initial site of the circuit board is located from different angles in sequence. First, take a picture from the front, set the lens aperture size to F5, the shutter speed to 1 / 125 seconds, and the ISO sensitivity to 200 to ensure clear images and appropriate exposure. After the shooting is completed, adjust the lens angle to 45 degrees. At this time, adjust the lens aperture size to F6.3, keep the shutter speed unchanged, and the ISO sensitivity is still 200 for the second shooting. Finally, adjust the lens angle to 90 degrees, set the lens aperture size to F9, adjust the shutter speed to 1 / 60 seconds, and the ISO sensitivity is still 200 to complete the third shooting. After each shooting is completed, the optical imaging device transmits the image data to the image processing system. After the image processing system receives the three images taken from the front, 45-degree angle, and 90-degree angle, it first processes the image taken from the front. Convert the image from the RGB color format to a grayscale image, and use the weighted average method for conversion, where the weights of the red, green, and blue channels are 0.299, 0.587, and 0.114 respectively. After the conversion is completed, perform denoising processing on the grayscale image, using the median filtering algorithm, and set the filtering window size to 3×3 pixels to remove the noise in the holes of the image and obtain a clear image of the circuit board holes.

[0038] Preferably, the defect areas for identifying the internal features of the holes in the circuit board hole image and extracting the internal features of the holes in step S2 include: Traverse the pixel points of the circuit board hole image and extract the pixel values of the pixel points; Perform binary processing on the circuit board hole image according to the pixel values. If the pixel value is 0-125, it is divided into the hole area; if the pixel value is 126-255, it is divided into the non-hole area; Determine the flatness and thickness of the circuit board for the non-hole area; identify the hole contour boundary of the hole area according to the flatness of the circuit board; Measure the hole depth of the circuit board based on the thickness of the circuit board; measure the diameter of the largest inscribed circle of the hole contour boundary to obtain the hole diameter of the circuit board; identify the texture degree of the hole wall of the hole contour boundary to obtain the hole wall roughness; Combine the hole depth of the circuit board, the hole diameter of the circuit board, and the hole wall roughness into the internal features of the hole; Extract the defective area where the internal features of the hole positions are located and mark it as the potential defective area of the hole positions.

[0039] In the embodiments of the present invention, during the analysis of the circuit board hole position image, first, the gray-scaled circuit board hole position image is traversed pixel by pixel. The image processing system reads the gray value of each pixel in the image row by row and column by column, and stores the gray value as the pixel value P(x, y), where (x, y) represents the coordinate position of the pixel. Subsequently, the circuit board hole position image is binarized according to the pixel value. A binarization threshold range is set. When the pixel value P(x, y) is between 0 and 125, the pixel is classified as the hole position area, and its pixel value is set to 0; when the pixel value P(x, y) is between 126 and 255, the pixel is classified as the non-hole position area, and its pixel value is set to 255. After binarization, the image is divided into the hole position area and the non-hole position area. For the non-hole position area, image processing algorithms are used to determine the flatness and thickness of the circuit board. The flatness is evaluated by calculating the standard deviation σ_flatness of the gray values of the pixels in the non-hole position area. The smaller the standard deviation, the better the flatness. The circuit board thickness is measured by analyzing the gray distribution of the non-hole position area and combining it with the pre-calibrated relationship model between gray and thickness, obtaining the circuit board thickness value T_board. According to the flatness of the circuit board, the hole position contour boundary of the hole position area is identified. An edge detection algorithm, such as the Canny algorithm, is used to perform edge detection on the binarized hole position area. The low threshold of the Canny algorithm is set to 50, and the high threshold is set to 150, detecting the hole position contour boundary and representing it as a series of coordinate points C(x, y). Based on the circuit board thickness T_board, the circuit board hole depth D_hole is measured. By analyzing the gray value distribution of the pixels in the hole position area and combining it with the circuit board thickness, the linear interpolation method is used to calculate the hole depth. Assuming that the depth corresponding to the lowest gray value in the hole position area is the circuit board thickness T_board, and the depth corresponding to the highest gray value is 0, the corresponding depth value is calculated according to the gray value ratio of the pixel, obtaining the hole depth D_hole. The maximum inscribed circle diameter D_inner of the hole position contour boundary is measured. Using geometric calculation methods, the largest circle that can be completely inscribed in the hole position contour is found from the hole position contour boundary C(x, y), and the diameter D_inner of this circle is calculated as the circuit board aperture amount. The hole wall texture degree of the hole position contour boundary is identified to obtain the hole wall roughness R_roughness. A texture analysis algorithm, such as the gray level co-occurrence matrix (GLCM) method, is used to analyze the pixels near the hole position contour boundary. The contrast eigenvalue of the GLCM matrix is calculated. The larger the contrast eigenvalue, the higher the hole wall roughness. According to the corresponding relationship between the contrast eigenvalue and the hole wall roughness, the hole wall roughness R_roughness is obtained. The circuit board hole depth D_hole, the circuit board aperture amount D_inner, and the hole wall roughness R_roughness are combined into the internal features of the hole position.By analyzing the distribution of the internal features of the hole positions, the areas that do not meet the normal range are extracted, that is, the areas where the internal feature values of the hole positions deviate from the normal threshold range, and these areas are marked as potential defect areas of the hole positions.

[0040] Preferably, in step S3, if the abnormal state time is greater than the preset abnormal state duration, the laser detection of the potential defect area of the hole position includes: If the abnormal state time is greater than the preset abnormal state duration, align the laser camera of the laser detection device with the potential defect area of the hole position; Start the laser detection device, and set the emission wavelength parameter to 532 nanometers to 1064 nanometers, the power range parameter to 10 milliwatts to 100 milliwatts, the emission laser beam time parameter to 10 milliseconds to 100 milliseconds, and the emission frequency to 1 hertz to 10 hertz; Receive the laser signal reflected from the potential defect area of the hole position, and extract the signal intensity and reflection time of the laser signal; Fit the laser signal into defect laser detection data according to the signal intensity and reflection time.

[0041] In the embodiments of the present invention, during the implementation of the intelligent test management method for circuit boards, when the abnormal state time T_abnormal is greater than the preset abnormal state duration T_threshold, first, the laser camera of the laser detection device is aligned with the potential defect area of the hole position. The laser detection device is installed on the robotic arm of the detection platform. Through the high-precision positioning system of the robotic arm, according to the abnormal initial site coordinates (X_initial, Y_initial) recorded in step S15 and the boundary information of the potential defect area of the hole position, the position and angle of the laser camera are adjusted so that the center of its lens is accurately aligned with the potential defect area of the hole position. The laser detection device is started, and the emission wavelength parameter is set to 1064 nanometers, the power range parameter is set to 50 milliwatts, the emission laser beam time parameter is set to 50 milliseconds, and the emission frequency is set to 5 hertz. The selection of these parameters is based on the comprehensive consideration of the material characteristics of the circuit board and the detection requirements of the potential defects of the hole position, ensuring that the reflected signal of the potential defect area of the hole position can be effectively excited while avoiding damage to the circuit board. The laser detection device emits laser beams according to the set parameters. After the laser beams irradiate the potential defect area of the hole position, part of the laser energy is reflected back to the receiving device of the laser detection device. The receiving device receives the laser signals reflected from the potential defect area of the hole position in real time and converts the optical signals into electrical signals through the built-in photoelectric converter. The system analyzes each reflected laser signal and extracts the signal intensity I_reflected and the reflection time T_reflection of the laser signal. The signal intensity I_reflected is measured by the output voltage value of the photoelectric converter, and the reflection time T_reflection is calculated by the time difference between the laser emission moment and the signal reception moment. According to the signal intensity I_reflected and the reflection time T_reflection, the system performs data fitting on the laser signals. The least squares fitting algorithm is used to fit the signal intensity and reflection time data points of multiple collected reflected laser signals into a curve to obtain the defect laser detection data. During the fitting process, the system considers the relationship between the reflection time and the signal intensity, as well as the physical characteristics of the potential defect area of the hole position, to ensure that the fitting result can accurately reflect the laser reflection characteristics of the potential defect area of the hole position. The defect laser detection data includes the mathematical expression of the fitting curve, key parameters (such as slope, intercept, etc.), and the corresponding reflection time range, and these data will be stored and used for subsequent defect analysis and processing.

[0042] Preferably, the structural topology identification of the defect laser detection data in step S3 includes: Determining the coordinates of the defective hole positions for the defect laser detection data; Measuring the distance between the hole position and the adjacent component pins according to the coordinates of the defective hole positions to obtain the hole position component pin spacing; Measure the distance between the hole position and the edge of the circuit board according to the coordinates of the defective hole position to obtain the edge distance of the hole position; Measure the perpendicularity deviation and the concentricity deviation of the hole wall according to the coordinates of the defective hole position; Detect the conductive connection relationship of the hole position based on the pin spacing of the hole position component and the edge distance of the hole position; detect the stacked layer misalignment structure of the hole position based on the perpendicularity deviation of the hole position and the concentricity deviation of the hole wall; Perform structural topology recognition on the defective laser detection data through the conductive connection relationship of the hole position and the stacked layer misalignment structure of the hole position to obtain the defective structure topology data.

[0043] In the embodiments of the present invention, during the intelligent test management of a circuit board, the coordinates of defective hole positions are first determined for the defective laser detection data. By analyzing the reflection time T_reflection and signal intensity I_reflected in the defective laser detection data, combining the emission parameters of the laser detection device and the geometric information of the potential defective area of the hole position, the precise coordinates (X_defect, Y_defect) of the defective hole position are calculated using the triangulation method. Specifically, according to the positional relationship between the laser emission point and the receiving point, and the optical path corresponding to the reflection time T_reflection, the coordinate position of the defective hole position on the two-dimensional plane is calculated. Next, according to the determined coordinates of the defective hole position (X_defect, Y_defect), the distance between the hole position and the adjacent component pins is measured. A high-precision optical measurement device is used, and its measurement accuracy reaches ±0.01 mm. The lens of the optical measurement device is aligned with the defective hole position and the adjacent component pins, and the edge contours of the hole position and the pins are identified through an image recognition algorithm. The straight-line distance between the centers of the two is calculated to obtain the hole position component pin distance D_pin, with the unit of mm. At the same time, the distance between the hole position and the edge of the circuit board is measured. The lens of the optical measurement device is aligned with the defective hole position and the edge of the circuit board, and the positions of the hole position edge and the circuit board edge are determined through an image recognition algorithm. The shortest straight-line distance between the two is calculated to obtain the hole position edge distance D_edge, with the unit of mm. Further, according to the coordinates of the defective hole position (X_defect, Y_defect), the perpendicularity deviation and the hole wall concentricity deviation of the hole position are measured. For the perpendicularity deviation, the laser beam emitted by the laser detection device is used to measure the angle θ between the axis of the hole position and the plane of the circuit board. The perpendicularity deviation Δθ is defined as the difference between θ and 90 degrees. For the hole wall concentricity deviation, by analyzing the laser reflection signal of the hole wall in the defective laser detection data, the circularity feature of the hole wall contour is extracted. The center offset amount Δr between the minimum circumscribed circle and the maximum inscribed circle of the hole wall contour is calculated as the hole wall concentricity deviation. Based on the hole position component pin distance D_pin and the hole position edge distance D_edge, the conductive connection relationship of the hole position is detected. By setting the thresholds D_pin_threshold and D_edge_threshold, when D_pin is less than D_pin_threshold or D_edge is less than D_edge_threshold, it is determined that there is a risk of conductive connection between the hole position and the component pins or the edge of the circuit board. At the same time, based on the hole position perpendicularity deviation Δθ and the hole wall concentricity deviation Δr, the stacked layer misalignment structure of the hole position is detected. The perpendicularity deviation threshold Δθ_threshold and the concentricity deviation threshold Δr_threshold are set. When Δθ is greater than Δθ_threshold or Δr is greater than Δr_threshold, it is determined that the hole position has a stacked layer misalignment structure.Finally, the defect laser detection data is identified by the conductive connection relationship of the hole positions and the hole position stacked layer misalignment structure. Using image processing and geometric analysis algorithms, combined with the detection results of the conductive connection relationship and the stacked layer misalignment structure, the structural topology data of the defective hole positions is constructed. The structural topology data includes the geometric shape, size parameters, relative position relationship with the surrounding components and the edge of the circuit board, as well as the types and positions of potential defects. These data will be stored and used for subsequent defect analysis and the formulation of optimized repair plans.

[0044] Preferably, the optimization scheme for the circuit board defects determined based on the defect structural topology data in step S3 includes: Dividing the defect structural topology data into structural short-circuit data and structural misalignment data; Marking the short-circuit positions of the circuit board for the structural short-circuit data, and determining the short-circuit influence range of the short-circuit positions of the circuit board to generate short-circuit influence range data; detecting the affected components for the short-circuit influence range data to obtain short-circuit affected component data; Marking the misaligned areas of the circuit board for the structural misalignment data, and identifying the wiring paths of the misaligned areas of the circuit board to generate misaligned wiring path data.

[0045] In the embodiments of the present invention, during the intelligent test management of a circuit board, the defect structure topology data is first classified. By analyzing the geometric shapes, dimensional parameters, and defect types in the defect structure topology data, the data is divided into structural short - circuit data and structural misalignment data. Structural short - circuit data refers to those defect data with the risk of conductive connection, while structural misalignment data refers to those defect data with stacked - layer misalignment structures. For the structural short - circuit data, an image - processing algorithm is used to mark the short - circuit positions on the circuit board. By identifying the geometric features of the short - circuit positions, such as the abnormal connection points between the hole positions and component pins, the coordinates (X_short, Y_short) of the short - circuit positions are marked. Subsequently, the short - circuit influence range on the circuit board is determined. An algorithm based on the current diffusion model is adopted. According to the circuit layout of the circuit board and the short - circuit positions, the diffusion path and influence range of the short - circuit current are calculated. The threshold of the short - circuit influence range is set as the area from 1 millimeter to 5 millimeters around the short - circuit position, and short - circuit influence range data is generated, including the boundary coordinates and area of the affected area. The components affected by the short - circuit are detected for the short - circuit influence range data. By comparing and analyzing the short - circuit influence range with the component layout diagram of the circuit board, the components located within the short - circuit influence range are identified. Using an image - recognition algorithm and combining the shape and position information of the components, short - circuit - affected component data is obtained, including the types, coordinate positions, and quantities of the affected components. For the structural misalignment data, an image - processing algorithm is used to mark the misaligned areas on the circuit board. By identifying the geometric features of the misaligned areas, such as the deviation between the hole positions and the wiring paths, the coordinate range (X_misalign, Y_misalign) of the misaligned areas is marked. Subsequently, the wiring paths in the misaligned areas of the circuit board are identified. An image - analysis technique based on the path - tracing algorithm is adopted. Combining with the wiring diagram of the circuit board, the original wiring paths and the wiring paths changed due to misalignment within the misaligned areas are identified. Misaligned wiring path data is generated, including the starting and ending coordinates of the wiring paths, as well as the shape and length information of the paths. Through the above steps, the defect structure topology data is divided into structural short - circuit data and structural misalignment data, and the short - circuit positions and misaligned areas are marked and analyzed in detail, generating short - circuit influence range data and misaligned wiring path data, providing an accurate basis for the subsequent circuit - board optimization and repair scheme.

[0046] Preferably, the determining of the circuit - board defect optimization scheme based on the defect structure topology data in step S3 further includes: Determining the types and quantities of the components affected by the short - circuit based on the short - circuit - affected component data, and repairing the short - circuit points of the components on the circuit board to obtain component short - circuit repair data; Determining the areas affected by the misaligned wiring based on the misaligned wiring path data, and rearranging the wiring paths in the misaligned wiring areas on the circuit board to obtain wiring path optimization data; Integrate component short-circuit repair data and wiring path optimization data to obtain a circuit board defect optimization solution.

[0047] In an embodiment of the present invention, in the process of implementing the circuit board intelligent test management method, the type and quantity of components affected by the short circuit are first determined based on the short circuit affecting component data. By analyzing the component type and coordinate position information in the short circuit affecting component data, the number of different types of components affected by the short circuit is counted. For example, if the short circuit affecting component data includes three types of components, namely resistors, capacitors and chips, the number of each type of components is counted respectively to obtain the statistical results of the short circuit impact of the components, including the component type (Type_short) and the corresponding number (Count_short). Subsequently, the circuit board is repaired for the short circuit points of the components. According to the statistical results of the short circuit impact of the components, the laser repair technology is used to repair the components affected by the short circuit. The wavelength of the laser repair equipment is set to 532 nanometers, the power is 30 milliwatts, and the scanning speed is 50 millimeters per second. For each component affected by the short circuit, the laser repair equipment operates according to the preset repair path to remove the abnormal conductive connection point. After the repair is completed, the detailed information of the repair operation is recorded, including the type, coordinate position and repair parameters of the repaired component, and the component short circuit repair data is generated. Next, the area affected by the misaligned wiring is determined based on the misaligned wiring path data. The wiring area affected by the misalignment is identified by analyzing the coordinates of the starting and ending points of the wiring path and the path shape information in the misaligned wiring path data. The image processing algorithm is used to mark the boundary range of the area affected by the misaligned wiring (X_misroute, Y_misroute) in combination with the wiring diagram of the circuit board. The wiring path of the misaligned wiring area of ​​the circuit board is rearranged. The automatic wiring algorithm is used to replan the wiring path in the area affected by the misaligned wiring according to the electrical connection requirements and wiring rules of the circuit board. The automatic wiring algorithm considers factors such as the electrical performance of the circuit board, wiring spacing and wiring length to generate a new wiring path. The new wiring path meets the electrical connection requirements of the circuit board and avoids the impact of the misalignment. The rearranged wiring path information, including the coordinates of the starting and ending points of the new wiring path, as well as the path shape and length, is recorded to generate wiring path optimization data. Finally, the component short circuit repair data and the wiring path optimization data are integrated to obtain the circuit board defect optimization solution. The repair operation information in the component short circuit repair data and the rearrangement path information in the wiring path optimization data are summarized to form a complete circuit board defect optimization plan. The optimization plan records the specific operation steps, parameters and areas involved in the repair and rearrangement in detail, providing clear guidance for subsequent circuit board repair and optimization.

[0048] As an example of the present invention, refer to Figure 3 As shown, in this example, step S4 includes: Step S41: Real-time monitor the current value of the circuit board hole position. When the current value of the circuit board hole position is lower than the preset current conduction threshold again, trigger the switch of the circuit board positioning and acquisition device; Step S42: Use the circuit board positioning and acquisition device to perform real-time detection on the edge of the circuit board, and extract the real-time edge of the circuit board; Step S43: Measure the X coordinate value and Y coordinate value of the abnormal hole position of the circuit board in the X-axis and Y-axis directions parallel to the real-time edge of the circuit board; measure the Z coordinate value of the abnormal hole position of the circuit board in the Z-axis direction perpendicular to the real-time edge of the circuit board; Step S44: Based on the X coordinate value, Y coordinate value, and Z coordinate value, obtain the real-time abnormal site coordinates; Step S45: When the real-time abnormal site coordinates match the abnormal initial site coordinates, perform optimization and repair management on the circuit board according to the circuit board defect optimization plan.

[0049] In an embodiment of the present invention, during the implementation of the intelligent test management method for a circuit board, first step S41 is executed to continuously monitor the current value of the circuit board hole positions in real time through a high-precision current sensor. The sampling rate of the current sensor is 1000 times per second, which can accurately measure the current changes at the circuit board hole positions. When it is detected that the current value of the circuit board hole position is lower than the preset current conduction threshold I_threshold again, the switch of the circuit board positioning and acquisition device is triggered. The preset current conduction threshold I_threshold is set to 10 milliamperes. When the current value I_current is lower than this threshold, the switch of the positioning and acquisition device is activated. Then step S42 is entered. After the circuit board positioning and acquisition device is started, real-time edge detection of the circuit board is performed. The positioning and acquisition device uses laser scanning technology. The laser emitter moves along the surface of the circuit board at a scanning frequency of 2000 times per second, emits laser beams and receives reflected signals. By analyzing the intensity and time delay of the reflected signals, the real-time edge information of the circuit board is extracted. The real-time edge information includes the contour coordinates and shape characteristics of the edge, which are recorded in millimeters. In step S43, in the X-axis and Y-axis directions parallel to the real-time edge of the circuit board, the X coordinate value X_realtime and Y coordinate value Y_realtime of the abnormal hole positions on the circuit board are measured. The positioning and acquisition device calculates the positions of the abnormal hole positions in the X-axis and Y-axis directions by combining the edge contour information obtained through laser scanning with a pre-set coordinate system. At the same time, in the Z-axis direction perpendicular to the real-time edge of the circuit board, the Z coordinate value Z_realtime of the abnormal hole positions on the circuit board is measured. The Z coordinate value is measured by a laser ranging module with an accuracy of 0.01 millimeters, which can accurately reflect the position deviation of the hole position in the vertical direction. According to the X coordinate value X_realtime, Y coordinate value Y_realtime and Z coordinate value Z_realtime obtained in step S43, step S44 is executed to obtain the real-time abnormal site coordinates (X_realtime, Y_realtime, Z_realtime). The real-time abnormal site coordinates are calculated by integrating the coordinate values in the X, Y, and Z directions by a data processing unit and stored in the form of three-dimensional coordinates. Finally, in step S45, the real-time abnormal site coordinates (X_realtime, Y_realtime, Z_realtime) are matched with the abnormal initial site coordinates (X_initial, Y_initial, Z_initial) recorded in step S15. By calculating the Euclidean distance between the two coordinate points, when the distance is less than the set matching threshold D_threshold (for example, 0.1 millimeters), it is determined that the real-time abnormal site matches the abnormal initial site. At this time, the circuit board is optimized and repaired according to the circuit board defect optimization plan.The optimization and repair management includes repairing the components affected by short circuits and rearranging the wiring paths in the misaligned wiring areas. The specific operation parameters are executed according to the records in the optimization plan to ensure that the performance of the circuit board is restored to the normal level.

[0050] This specification also provides a circuit board intelligent test management system for executing the circuit board intelligent test management method described above. The circuit board intelligent test management system includes: An initial anomaly monitoring module for continuously monitoring the current conduction amount of the circuit board hole positions; when the detected current conduction amount is lower than the preset current conduction amount threshold, it is determined as an abnormal state of the hole position current conduction, and the abnormal state time and the coordinates of the initial anomaly site are recorded; A hole position image recognition module for obtaining the circuit board hole position image according to the coordinates of the initial anomaly site; recognizing the internal features of the hole positions in the circuit board hole position image, extracting the defective areas of the internal features of the hole positions, and marking them as potential defective areas of the hole positions; A defect structure topology detection module for, if the abnormal state time is greater than the preset abnormal state duration, performing laser detection on the potential defective areas of the hole positions to generate defect laser detection data; performing structure topology recognition on the defect laser detection data to obtain defect structure topology data; and determining a circuit board defect optimization plan based on the defect structure topology data; A circuit board optimization and repair module for real-time monitoring of the circuit board hole position current value. When the circuit board hole position current value is lower than the preset current conduction amount threshold again, the real-time anomaly site coordinates are obtained; when the real-time anomaly site coordinates match the initial anomaly site coordinates, the circuit board is subjected to optimization and repair management according to the circuit board defect optimization plan.

[0051] Through the collaborative work of the initial anomaly monitoring module, hole position image recognition module, defect structure topology detection module, and circuit board optimization and repair module, the present invention realizes the full-process automated management from circuit board hole position anomaly monitoring, defect recognition, structure topology detection to optimization and repair. The initial anomaly monitoring module can continuously monitor the current conduction amount of the circuit board hole positions, accurately determine the abnormal state, and record the abnormal time and the initial site coordinates, providing accurate information for subsequent processing. The hole position image recognition module obtains the hole position images according to the abnormal initial site coordinates, efficiently recognizes and extracts the defective areas of the internal features of the hole positions, and marks them as potential defective areas. The defect structure topology detection module conducts laser detection and structure topology recognition on the potential defective areas, generates defect laser detection data, and determines the optimization and repair plan to ensure the scientificity and effectiveness of defect handling. The circuit board optimization and repair module monitors the hole position current value in real time. When the current value is lower than the threshold again, it obtains the real-time abnormal site coordinates and matches them with the initial site coordinates, and conducts repair management according to the optimization plan, effectively avoiding the deterioration of the problem and extending the service life of the circuit board. This system significantly improves the efficiency and accuracy of circuit board test management, reduces manual intervention, reduces the risk of operation errors, and at the same time improves the production efficiency and quality control level, reducing production delays caused by defects.

[0052] Therefore, in any aspect, the embodiments should be regarded as exemplary and non-restrictive. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, it is intended to embrace all changes falling within the meaning and scope of the equivalent elements of the application documents within the present invention.

[0053] The above are only the specific embodiments of the present invention, enabling those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be obvious to those skilled in the art. The general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to these embodiments shown herein, but rather will conform to the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for intelligent testing management of circuit boards, characterized in that: The following steps are involved: Step S1: continuously monitoring the current conduction of the hole position of the circuit board; when the current conduction is detected to be lower than the preset current conduction threshold, it is determined to be an abnormal state of the hole current conduction, and the abnormal state time and the coordinates of the abnormal initial position are recorded; Step S2: acquiring a hole image of the circuit board according to the coordinates of the abnormal initial site; identifying the internal features of the hole in the hole image of the circuit board, extracting the defective area of ​​the internal features of the hole, and marking it as a potential defective area of ​​the hole; Step S3: If the abnormal state time is greater than the preset abnormal state duration, laser detection is performed on the potential defect area of ​​the hole position to generate defect laser detection data; structural topology recognition is performed on the defect laser detection data to obtain defect structural topology data; and a circuit board defect optimization plan is determined based on the defect structural topology data; Step S4: monitor the current value of the circuit board hole in real time. When the current value of the circuit board hole is lower than the preset current conduction threshold again, obtain the real-time abnormal site coordinates; when the real-time abnormal site coordinates match the abnormal initial site coordinates, optimize the circuit board according to the circuit board defect optimization plan. Repair management.

2. The method for intelligent testing management of circuit boards according to claim 1, characterized in that: Step S1 includes the following steps: Step S11: Current sensors are respectively arranged at the power input terminal hole and the power distribution node hole of the circuit board, and the current conduction is continuously sampled at a sampling period of 1 millisecond to 100 milliseconds, and each sampling lasts for 10 microseconds to 100 microseconds to obtain current monitoring data; Step S12: the current monitoring data is segmented in time sequence, each segment contains 50 to 200 sampling points, and the average value, maximum value and minimum value of each segment of data are calculated as the current conduction amount; Step S13: when it is detected that the current conduction is lower than the preset current conduction threshold, it is determined to be an abnormal current conduction state at the hole position; Step S14: Record the abnormality detection time, data collection time and abnormality confirmation time when the abnormal state occurs to obtain the abnormal state time; Step S15: marking abnormal conduction positions of the circuit board according to the abnormal conduction state of the hole current to obtain the coordinates of the abnormal initial position.

3. The method for intelligent testing management of circuit boards according to claim 1, characterized in that: The step S2 of acquiring the circuit board hole position image according to the abnormal initial position coordinates includes: Place the circuit board on the detection platform, and aim the lens of the optical imaging device at the area where the abnormal initial point of the circuit board is located according to the coordinates of the abnormal initial point; Start the optical imaging device and take photos of the area where the abnormal initial position of the circuit board is located from the front, 45 degrees and 90 degrees in turn. When shooting from the front, the lens aperture size is set to F4.1-F5.6; when shooting from a 45-degree angle, the lens aperture size is set to F5.6-F8; when shooting from a 90-degree angle, the lens aperture size is set to F8-F11; Collect the initial image of the circuit board hole position; convert the initial image of the circuit board hole position into a grayscale image, remove the image hole position noise, so as to obtain the circuit board hole position image.

4. The method for intelligent testing management of circuit boards according to claim 1, characterized in that: The step S2 of identifying the internal features of the hole positions of the circuit board hole position image and extracting the defective area of ​​the internal features of the hole positions includes: Traverse the pixel points of the circuit board hole position image and extract the pixel values ​​of the pixel points; Binarize the hole position image of the circuit board according to the pixel value. If the pixel value is 0-125, it is divided into the hole position area; if the pixel value is 126-255, it is divided into the non-hole position area; Determine the flatness and thickness of the circuit board for the non-hole area; identify the hole contour boundary of the hole area according to the flatness of the circuit board; Calculate the circuit board hole depth based on the circuit board thickness; calculate the maximum inscribed circle diameter of the hole contour boundary to obtain the circuit board hole diameter; identify the hole wall texture degree of the hole contour boundary to obtain the hole wall roughness; The circuit board hole depth, circuit board hole diameter and hole wall roughness are combined into the internal features of the hole position; The defective area where the internal features of the hole are located is extracted and marked as the potential defective area of ​​the hole.

5. The method for intelligent testing management of circuit boards according to claim 1, characterized in that: If the abnormal state time in step S3 is greater than the preset abnormal state duration, laser detection of the potential defect area of ​​the hole position includes: If the abnormal state time is greater than the preset abnormal state duration, aim the laser camera of the laser detection equipment at the potential defect area of ​​the hole; Start the laser detection device, and set the emission wavelength parameter to 532 nanometers to 1064 nanometers, the power range parameter to 10 milliwatts to 100 milliwatts, the emission laser beam time parameter to 10 milliseconds to 100 milliseconds, and the emission frequency to 1 Hz to 10 Hz; Receive the laser signal reflected from the potential defect area of ​​the hole, and extract the signal intensity and reflection time of the laser signal; The laser signal is fitted into defect laser detection data according to the signal intensity and reflection time.

6. The method for intelligent testing management of circuit boards according to claim 1, characterized in that: The structural topology recognition of the defect laser detection data in step S3 includes: Determine the defect hole coordinates based on defect laser detection data; According to the coordinates of the defective hole, the distance between the hole and the pins of the adjacent components is measured to obtain the distance between the pins of the hole components; According to the coordinates of the defective hole, the distance between the hole and the edge of the circuit board is measured to obtain the hole edge spacing; Measure the hole verticality deviation and hole wall concentricity deviation according to the defect hole coordinates; Detect the conductive connection relationship of the hole based on the hole component pin spacing and the hole edge spacing; detect the hole stacking misalignment structure based on the hole verticality deviation and hole wall concentricity deviation; The defective structure topology data is obtained by performing structural topological recognition on the defect laser detection data through the hole conductive connection relationship and the hole stacking dislocation structure.

7. The method for intelligent testing management of circuit boards according to claim 1, characterized in that: Determining the circuit board defect optimization solution based on the defect structure topology data in step S3 includes: The defect structure topology data is divided into structural short circuit data and structural dislocation data; Mark the short-circuit position of the circuit board on the structural short-circuit data, determine the short-circuit impact range of the short-circuit position on the circuit board, and generate short-circuit impact range data; perform impact component detection on the short-circuit impact range data to obtain short-circuit impact component data; The structural misalignment data is used to mark the misalignment area of ​​the circuit board, and the wiring path of the misalignment area of ​​the circuit board is identified to generate the misalignment wiring path data.

8. The method for intelligent testing management of circuit boards according to claim 1, characterized in that: Determining the circuit board defect optimization solution based on the defect structure topology data in step S3 also includes: Determine the type and quantity of components affected by the short circuit based on the short circuit-affected component data, and repair the short circuit points of the components on the circuit board to obtain component short circuit repair data; Determine the area affected by the misaligned wiring based on the misaligned wiring path data, and rearrange the wiring paths of the misaligned wiring area of ​​the circuit board to obtain wiring path optimization data; Integrate component short-circuit repair data and wiring path optimization data to obtain a circuit board defect optimization solution.

9. The method for intelligent testing management of circuit boards according to claim 1, characterized in that: Step S4 includes the following steps: Step S41: real-time monitoring of the current value of the circuit board hole position, when the current value of the circuit board hole position is lower than the preset current conduction threshold again, triggering the switch of the circuit board positioning acquisition device; Step S42: using a circuit board positioning and acquisition device to perform real-time detection of the circuit board edge and extract the real-time edge of the circuit board; Step S43: Calculate the X-coordinate value and Y-coordinate value of the abnormal hole position of the circuit board in the X-axis and Y-axis directions parallel to the real-time edge of the circuit board; Calculate the Z-coordinate value of the abnormal hole position of the circuit board in the Z-axis direction perpendicular to the real-time edge of the circuit board; Step S44: based on the X coordinate value, the Y coordinate value and the Z coordinate value, obtain the real-time abnormal site coordinates; Step S45: When the real-time abnormal site coordinates match the abnormal initial site coordinates, the circuit board is optimized and repaired according to the circuit board defect optimization solution.

10. A circuit board intelligent test management system, characterized in that: Used to execute the circuit board intelligent test management method according to claim 1, the circuit board intelligent test management system comprises: The initial abnormality monitoring module is used to continuously monitor the current conduction of the circuit board hole position; when the current conduction is detected to be lower than the preset current conduction threshold, it is determined to be an abnormal state of the hole current conduction, and the abnormal state time and the coordinates of the abnormal initial position are recorded; The hole image recognition module is used to obtain the hole image of the circuit board according to the coordinates of the abnormal initial position; identify the internal features of the hole in the hole image of the circuit board, extract the defect area of ​​the internal features of the hole, and mark it as the potential defect area of ​​the hole; The defect structure topology detection module is used to perform laser detection on the potential defect area of ​​the hole position if the abnormal state time is greater than the preset abnormal state duration, and generate defect laser detection data; perform structural topology recognition on the defect laser detection data to obtain defect structure topology data; and determine the circuit board defect optimization plan based on the defect structure topology data; The circuit board optimization and repair module is used to monitor the circuit board hole current value in real time. When the circuit board hole current value is lower than the preset current conduction threshold again, the real-time abnormal site coordinates are obtained; when the real-time abnormal site coordinates match the abnormal initial site coordinates, the circuit board is optimized and repaired according to the circuit board defect optimization plan.

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