Multi-device communication system and method, electronic device and storage medium

Abstract

The invention discloses a multi-device communication system and method, an electronic device and a storage medium, and the system comprises a first device which comprises a chip selection signal output end; the second device to the Nth device comprise chip selection signal input ends, signal output modules and redundant signal output ends which are connected in sequence, the chip selection signal input end of the second device is connected with any chip selection signal output end of the first device, and the chip selection signal input ends of the third device to the Nth device are correspondingly connected with the redundant signal output ends of the second device to the (N-1) th device; the signal output module outputs a low level or a high level; and after determining the accessed Mth equipment, the control module sets the chip selection signal input end of the Mth equipment to be low level and communicates with the Mth equipment. Therefore, the problems that if the number of access devices is increased, an expensive CPU or an IO expansion chip needs to be added, and the cost is increased in the scheme that the SPI controller is simulated through GPIO to access the devices are solved, more slave devices are supported by utilizing the attributes of the signal output ends of the slave devices, and the production cost is reduced.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a multi-device communication system and method, electronic equipment, and storage medium. Background Art

[0002] The Serial Peripheral Interface (SPI), an efficient, synchronous serial communication protocol, is widely used for data transmission between microcontrollers (MCUs) and their various peripherals. Due to its full-duplex communication capabilities, simple hardware connections, and low cost, the SPI protocol is the preferred method for connecting CPUs to peripherals such as electrically erasable programmable read-only memory (EEPROM), real-time clocks (RTCs), analog-to-digital converters (ADCs), digital-to-analog converters (DACs), liquid crystal displays (LCDs), audio integrated circuits (AICs), temperature sensors, pressure sensors, MMCs, and SD cards.

[0003] The SPI protocol uses a master-slave architecture, in which the master device (typically a CPU's built-in SPI controller or one emulated via GPIO (General Purpose Input / Output)) generates the clock signal (SCK) and exchanges data with slave devices (i.e., various peripherals) via the MOSI (Master Out Slave In) and MISO (Master In Slave Out) data lines. Furthermore, the CS (Chip Select) signal plays a key role in multi-slave configurations, selecting a specific slave device for communication.

[0004] However, with the increasing number of peripherals in modern electronic systems, a major challenge facing the SPI interface is the limited CS signal resources. Because each slave device requires an independent CS signal for identification and control, when the number of slave devices is large, the traditional SPI interface may experience a shortage of CS signal resources.

[0005] To solve the problem of insufficient CS signal resources, there are currently two main solutions: one is to increase the number of SPI controllers, but this usually requires the CPU to have more SPI controller resources or GPIO pins. Otherwise, it may be necessary to upgrade to a higher-end CPU, increasing hardware costs; the other is to use a dedicated expansion chip, but this also requires additional hardware investment and increases the overall cost of the system.

[0006] Therefore, how to effectively expand the CS signal resources of the SPI interface and improve the scalability and flexibility of the system without significantly increasing hardware costs has become an important issue in the current application of the SPI communication protocol. Summary of the Invention

[0007] The present application provides a multi-device communication system and method, an electronic device, and a storage medium to solve the problem in the related art of accessing devices through GPIO emulating SPI controllers. Each additional access device requires an independent chip select signal from the CPU. The increase in devices requires an expensive CPU or an additional IO expansion chip, which increases costs.

[0008] The present application provides a multi-device communication system, comprising: a first device, wherein the first device includes at least one chip select signal output terminal; second to Nth devices, wherein the second to Nth devices each include a chip select signal input terminal, a signal output module and at least one redundant signal output terminal connected in sequence, the chip select signal input terminal of the second device is connected to any chip select signal output terminal of the first device, and the chip select signal input terminals of the third to Nth devices are connected one-to-one with any redundant signal output terminals of the second to N-1th devices, the signal output module is used to output a first level or a second level, N≥2; a control module is used to, when the Mth device to be accessed is determined from the second to Nth devices, sequentially set the chip select signal input terminal of the Mth device to the first level through the chip select signal output terminal of the first device connected to the chip select signal input terminal of the second device and the redundant signal output terminals of all devices between the first device and the Mth device, and complete the operation on the Mth device within a preset time length, wherein 2≤M≤N.

[0009] Through the above technical solution, when the chip select signal of the master device is insufficient, the redundant signal output end of the slave device can be effectively utilized to expand the chip select signal capacity of the master device, thereby allowing the master device to access more slave devices without adding additional hardware resources.

[0010] Optionally, the control module includes: a first control unit, used to sequentially set the chip select signal output end of the first device and the redundant signal output ends of the second device to the M-1th device to the second level, and then set the redundant signal output end of the M-1th device to the first level, wherein the second level is opposite to the first level.

[0011] With the above technical solution, by controlling the level state of the chip select signal input terminal of the slave device, it is ensured that only one device to be accessed is activated at any time, thereby avoiding data conflicts and communication errors.

[0012] Optionally, the signal output module includes: a register unit for setting the preset duration; a counting unit for accumulating the first duration after the chip select signal input end of the Mth device is switched from the first level to the second level, and / or the second duration after the chip select signal input end of the Mth device is switched from the second level to the first level; a comparison unit for outputting a first switching signal when the first duration is equal to the signal duration, or outputting a second switching signal when the second duration is equal to the signal duration; a signal output unit for outputting a first level according to the first switching signal, or outputting a second level according to the second switching signal.

[0013] Through the above technical solution, by measuring the time through the signal output module, the chip select signal input terminal state of the Mth device can be accurately switched when needed, ensuring the correctness and integrity of data transmission and operation, avoiding communication errors or data loss due to improper state switching or delays, thereby enhancing the stability and reliability of the system.

[0014] Optionally, the control module further includes: a second control unit, which is used to set the redundant signal output end of the M-1 device to the second level after completing the operation of the Mth device within the preset time length, so that the chip select signal input end of the Mth device is the second level.

[0015] Through the above technical solution, the second control unit ensures that the Mth device is disabled after completing all operations within a preset time period, which helps prevent data conflicts between multiple devices.

[0016] Optionally, the control module further includes: a third control unit, configured to set the chip select signal output terminal of the first device to the second level after setting the redundant signal output terminal of the M-1th device to the second level.

[0017] With the above technical solution, by setting the chip select signal output terminal of the first device to the second level, the first device no longer communicates with any device and can freely prepare for the next access or perform other tasks.

[0018] Optionally, when the redundant signal output terminal of any device from the second to the Nth devices is at the first level, the chip select signal output terminal of the first device and the redundant signal output terminals of all remaining devices are at the second level.

[0019] Through the above technical solution, by ensuring that only one device to be accessed is activated at any given moment, the risk of data loss or error caused by multiple devices communicating simultaneously is reduced.

[0020] Optionally, all redundant signal output terminals of the second to Nth devices may be configured to switch between the first level and the second level based on a preset frequency.

[0021] Through the above technical solution, by utilizing the specific properties of the redundant signal output terminals of the second to Nth devices, it is possible to support communication between more devices and reduce the overall production cost of the product.

[0022] The present application also provides a multi-device communication method, which is applied to the above-mentioned multi-device communication system, and the method includes the following steps: determining a first device, and determining the Mth device to be accessed from the second to Nth devices; setting the chip select signal input end of the Mth device to a first level through the chip select signal output end of the first device connected to the chip select signal input end of the second device and the redundant signal output ends of all devices between the first device and the Mth device, and completing the operation on the Mth device within a preset time length, wherein 2≤M≤N.

[0023] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of the above-mentioned multi-device communication method when executing the computer program.

[0024] The present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of the above-mentioned multi-device communication method are implemented.

[0025] Through this application, when a control module determines the Mth device to be accessed from the second to Nth devices, it sequentially sets the chip select signal input of the Mth device to a first level through the chip select signal output of the first device connected to the chip select signal input of the second device, and through the redundant signal outputs of all devices between the first and Mth devices, completing the operation on the Mth device within a preset duration. This solves the existing problem of accessing devices through GPIO emulation of an SPI controller, where each additional accessed device requires a separate chip select signal from the CPU, and the increase in devices requires an expensive CPU or an IO expansion chip, which increases costs. When the chip select signal of the master device is insufficient, the specific properties of the slave device output signal terminal are utilized to support more slave devices, reducing the overall production cost of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0027] Figure 1 A one-to-one connection diagram of the SPI bus in the related art;

[0028] Figure 2 A schematic diagram of a one-to-three connection of an SPI bus in the related art;

[0029] Figure 3 A schematic diagram of a multi-device communication system provided according to an embodiment of the present application;

[0030] Figure 4 This is a connection diagram of using an LED control signal as a chip select signal according to one embodiment of the present application;

[0031] Figure 5 1 is a schematic diagram of internal control logic of the second to Nth devices according to one embodiment of the present application;

[0032] Figure 6 This is a flowchart of a driver accessing slave device 2 according to one embodiment of the present application;

[0033] Figure 7 Schematic diagram of a multi-device communication method according to an embodiment of the present application;

[0034] Figure 8 Schematic diagram of the structure of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0035] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0036] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0037] Before specifically introducing the embodiments of the present application, a brief introduction to the serial peripheral interface SPI is given.

[0038] The Serial Peripheral Interface (SPI) is a synchronous serial communication protocol that provides very high-speed, full-duplex communication. It is a master-slave type protocol that provides a simple and low-cost interface between a microcontroller and its peripherals. The SPI interface bus is commonly used to connect the CPU to peripherals such as EEPROMs, RTCs (real-time clocks), ADCs (analog-to-digital converters), DACs (digital-to-analog converters), LCDs, audio ICs, sensors such as temperature and pressure sensors, and MMC or SD cards.

[0039] For short-distance communication, synchronous serial communication will be a better choice, especially the serial peripheral interface (SPI) is the best choice. Short-distance communication usually refers to communication within a device or between devices on the same board (PCB).

[0040] SPI is a synchronous type of serial communication because it uses a dedicated clock signal to synchronize the transmitter and receiver or master and slave. The transmitter and receiver are connected via separate data and clock lines. The clock signal will help the receiver when to look for data on the bus.

[0041] The clock signal must be provided by the master to the slave device (or to all slave devices in a multi-slave setup). There are two types of triggering mechanisms on the clock signal that are used to cause the receiver to acquire data: edge-triggered and level-triggered. The most commonly used trigger is edge-triggered, which comes in two types: rising edge (low-to-high transition of the clock) and falling edge (high-to-low transition). Depending on how the receiver is configured, upon detecting an edge, the receiver will look for data on the data bus, starting with the next bit.

[0042] Since both the clock and data are sent by the master (or transmitter), there is no need to worry about the speed of data transmission. The reason why SPI is so popular among other synchronous serial communication protocols (or any serial communication for that matter) is that it provides high-speed secure data transmission and fairly simple hardware (such as shift registers) at a relatively low cost.

[0043] In the SPI protocol, there can be only one master device, but there can be multiple slave devices. The specific one-to-one connection method of the SPI bus is as follows: Figure 1 As shown, the SPI bus consists of four signals (pins), including:

[0044] MOSI: Master Out Slave In, the master device sends data and the slave device receives data.

[0045] MISO: Master In Slave Out, the slave device sends data and the master device receives data.

[0046] SCK: Serial Clock, that is, clock signal.

[0047] CS: Chip Select, chip select signal, used when there are multiple slave devices.

[0048] The clock (SCK) signal is generated by the master, controlling the data flow. During each clock cycle, one bit of data is transferred from the master to the slave and one bit from the slave to the master. Data transfer in both directions occurs simultaneously; after eight clock cycles, a byte (8 bits) of data has been transferred in both directions, making SPI full-duplex communication. If data can only be transmitted by one device, the other device must also send something (even garbage data). Whether the data transmitted is meaningful depends on the specific circumstances of the devices. This means that for every bit sent by one device, the opposing device must also send a bit of data. That is, the master simultaneously transmits data on the MOSI line and receives data from the slave on the MISO line. If the slave wants to send data, the master must know in advance when the slave is about to send data and generate the appropriate clock signals.

[0049] If you need to connect multiple slave devices to the master device, the SPI bus one-to-three connection method is as follows Figure 2 As shown in the figure, all slave devices share the MOSI, MISO, and SCK signals. To distinguish slave devices, the master device has a dedicated CS signal connection for each slave device. All CS signals are normally high. When the master device selects a slave device for data transmission, it sets the corresponding CS signal to a low level. After the data transmission is completed, it sets it back to a high level.

[0050] Slave devices are generally various peripherals, and the master device is generally the SPI controller in the CPU or an SPI controller simulated by GPIO. Since each slave device requires a CS signal, when there are many slave devices, there may be insufficient CS signals. In this case, there are two solutions:

[0051] ① Using more SPI controllers requires more SPI controllers (or more GPIO pins) on the CPU. If not, you need to choose a higher-end CPU, which increases the cost of use.

[0052] ② Using a dedicated expansion chip requires purchasing an additional chip, which also increases the cost of use.

[0053] The following example illustrates an existing solution for accessing a device by simulating an SPI controller through GPIO. The hardware connection method is as follows: Figure 2 shown.

[0054] All signals on the master device are emulated as GPIOs. Three drivers are required in the system: a GPIO driver, an SPI-GPIO driver, and a slave device driver. The GPIO driver controls the high and low levels of each GPIO, effectively implementing a GPIO controller. The SPI-GPIO driver uses the GPIO driver to control the high and low levels of the corresponding GPIOs, emulating signals that conform to the SPI protocol, including MOSI, MISO, SCK, and each CS pin. The slave device driver utilizes the SPI access signals sent by the SPI-GPIO driver to access the slave device's registers and control the slave device to perform its specific functions.

[0055] All drivers are included in the system by default, but to make these drivers work, you must include the corresponding configuration in the device tree source file (dts). The following is an example. The key information is commented. The connection method between the three physical devices and the CPU is the same as Figure 2 Similarly, slave device 0 corresponds to a network module, slave device 1 corresponds to an LED module, and slave device 2 corresponds to a sensor module.

[0056] gpio0:gpio@3f8019000{ / / Add a GPIO controller to the system

[0057] compatible = "snps,dw-apb-gpio"; / / compatible with and uses the GPIO driver named "snps,dw-apb-gpio"

[0058] reg = <0x3 0xf8019000 0x0 0x1000>; / / The physical address of the actual GPIO controller

[0059] #address-cells= <1> ;

[0060] #size-cells= <0> ;

[0061] porta:gpio-controller@0{ / / Add a GPIO port named porta, which actually manages 8 GPIO pins.

[0062] compatible="snps,dw-apb-gpio-port";

[0063] gpio-controller;

[0064] #gpio-cells= <2> ;

[0065] ngpios= <8> ; / / Use 8 GPIOs in total

[0066] reg= <0> ;

[0067] };

[0068] ctl_spi:spi{ / / Add an SPI controller to the system

[0069] compatible = "spi-gpio"; / / compatible and use the boot named "spi-gpio"

[0070] #address-cells= <1> ;

[0071] #size-cells= <0> ;

[0072] num-chipselects= <3> ; / / Support 3 chip select signals

[0073] cs0-gpios=<&porta 0 1>; / / Chip select 0 is GPIO pin 0 of porta, and the following 1 indicates that the low level is valid

[0074] cs1-gpios=<&porta 1 1>; / / Chip select 1 is GPIO pin 1 of porta

[0075] cs2-gpios=<&porta 2 1>; / / Chip select 2 is GPIO pin 2 of porta

[0076] sck-gpios = <&porta 3 0>; / / The clock signal uses porta's GPIO pin 3

[0077] miso - gpios = <&porta 4 0>; / / The MISO signal uses the 4th GPIO pin of porta

[0078] mosi - gpios = <&porta 5 0>; / / The MOSI signal uses the 5th GPIO pin of porta

[0079] eth_dev@0 { / / Add the 0th SPI slave device

[0080] compatible = "eth_dev"; / / Compatible with and use a certain network module driver

[0081] spi - max - frequency = <1000000>0>; / / The maximum SPI clock frequency supported by the device

[0082] };

[0083] led_dev@1 { / / Add the 1st SPI slave device

[0084] compatible = "led_dev"; / / Compatible with and use a certain LED module driver

[0085] led_num = <8>; / / Support controlling 8 LED lights

[0086] spi - max - frequency = <5000000>; / / The maximum SPI clock frequency supported by the device

[0087] };

[0088] sensor_dev@2 { / / Add the 2nd SPI slave device

[0089] compatible = "sensor_dev"; / / Compatible with and use a certain sensor module driver

[0090] spi - max - frequency = <8000000>; / / The maximum SPI clock frequency supported by the device

[0091] };

[0092] };

[0093] For example, let's access an LED module. Assuming this module supports eight LEDs, lighting LED0 requires an 8-bit register called the LED control register, located at address 0x10. Each bit in the LED control register corresponds to one LED. To light LED0, write a 1 to bit 0 of the register (leaving all other bits unchanged). To light LED1, write a 1 to bit 1 of the register (leaving all other bits unchanged). The same logic applies to the other LEDs.

[0094] The following briefly describes the SPI driver workflow during the process of lighting up LED0.

[0095] ① Define a delay according to the maximum SPI frequency supported by the LED module. After each delay, invert the level of GPIO 3, which is equivalent to sending a continuous SCK signal.

[0096] ② Set GPIO 1 to low level and select the LED module.

[0097] ③Control MISO and MOSI, that is, GPIO No. 4 and 5. First read the value of the LED control register, modify its 0th bit to 1, and then write it back to the LED control register.

[0098] ④ Set GPIO 1 to high level and deselect the LED module.

[0099] In summary, the main disadvantage of the existing technology is that each additional slave device requires the use of an independent chip select signal of the CPU. When there are more slave devices, a more expensive CPU (providing more SPI controllers or GPIO interfaces) is required, or additional IO expansion chips are added. These methods will increase production costs and need to be solved urgently.

[0100] To solve the above problems, an embodiment of the present application provides a multi-device communication system.

[0101] like Figure 3 As shown, the multi-device communication system 10 includes: a first device 100 , second to Nth devices 200 and a control module 300 .

[0102] Among them, the first device 100, the first device 100 includes at least one chip select signal output terminal; the second to Nth devices 200, the second to Nth devices 200 all include a chip select signal input terminal, a signal output module and at least one redundant signal output terminal connected in sequence, the chip select signal input terminal of the second device is connected to any chip select signal output terminal of the first device, and the chip select signal input terminals of the third to Nth devices are connected one-to-one with any redundant signal output terminals of the second to N-1th devices, the signal output module is used to output a first level or a second level, N≥2; the control module 300 is used to, when the Mth device to be accessed is determined from the second to Nth devices 200, sequentially set the chip select signal input terminal of the Mth device to the first level through the chip select signal output terminal of the first device 100 connected to the chip select signal input terminal of the second device and the redundant signal output terminals of all devices between the first device 100 and the Mth device, and complete the operation on the Mth device within a preset time length, wherein 2≤M≤N.

[0103] In which, in the embodiment of the present application, the first level is a low level, the Mth device is any device from the second to the Nth devices 200, referring to a device planned to communicate or operate, and the preset duration can be a threshold value pre-set by the user, a threshold value obtained through a limited number of experiments, or a threshold value obtained through a limited number of computer simulations, which is not specifically limited here.

[0104] For the sake of convenience, the present embodiment is described in detail with N=3 and M=3. Figure 4 As shown, Figure 4 The system includes a first device 100, a second device, a third device, and a device connected to the chip select signal output terminal CS0 of the first device 100 (for convenience of explanation, the device is referred to as slave device 0 hereinafter), wherein the third device is the Mth device to be accessed.

[0105] The first device 100 includes a MOSI terminal, a MISO terminal, an SCK terminal, a CS0 terminal, and a CS1 terminal. The chip select signal output terminals of the first device 100 are CS0 and CS1 (to avoid redundancy, this application describes the chip select signal output terminal of the first device 100 as CS1). The second device includes a MOSI terminal, a MISO terminal, an SCK terminal, and a CS terminal. The chip select signal input terminal of the second device is CS. The redundant signal output terminal of the second device is LED7 / CS2. The second device and the third device are cascaded, that is, the chip select signal input terminal CS of the second device is connected to the chip select signal output terminal CS1 of the first device, and the chip select signal input terminal of the third device is connected to the redundant signal output terminal LED7 / CS2 of the second device.

[0106] During the actual communication process, after determining that the third device is the Mth device to be accessed, the high and low level automatic switching frequency of the redundant signal output terminal of the second device is set, and the chip select signal output terminal CS1 of the first device 100 outputs a high level signal to the chip select signal input terminal CS of the second device. The redundant signal output terminal LED7 / CS2 of the second device switches from a high level to a low level. After the chip select signal input terminal CS of the Mth device receives a low level, the Mth device becomes a selected operation state and automatically switches the frequency according to the high and low levels within a preset time length to complete operations on the Mth device, such as data transmission, status query and other operations.

[0107] Through the above technical solution, when the chip select signal of the first device is insufficient, the redundant signal output end of the device can be effectively utilized to expand the chip select signal capacity of the first device, thereby allowing the first device to access more slave devices without adding additional hardware resources.

[0108] Optionally, in some embodiments, all redundant signal output terminals of the second to Nth devices may be configured to switch between a first level and a second level based on a preset frequency.

[0109] In the embodiment of the present application, the second level is a high level, and the preset frequency can be a threshold value pre-set by the user, a threshold value obtained through a limited number of experiments, or a threshold value obtained through a limited number of computer simulations, which is not specifically limited here.

[0110] It can be understood that all the redundant signal output terminals of the second to Nth devices have redundant signal output terminals that switch between a first level and a second level according to a preset frequency.

[0111] Specific as Figure 4 As shown, the redundant signal output terminal LED7 / CS2 of the second device and the chip select signal input terminal CS of the Mth device can both switch between a low level and a high level based on a preset frequency.

[0112] Through the above technical solution, by utilizing the specific properties of the redundant signal output terminals of the second to Nth devices, it is possible to support communication with more slave devices and reduce the overall production cost of the product.

[0113] Optionally, in some embodiments, the control module 300 includes: a first control unit, used to sequentially set the chip select signal output end of the first device and the redundant signal output ends of the second device to the M-1th device to the second level, and then set the redundant signal output end of the M-1th device to the first level, wherein the second level is opposite to the first level.

[0114] It is understandable that in actual communication, Figure 4For example, after determining the Mth device, the first control unit controls the chip select signal output terminal CS1 of the first device 100 to be high level, first sets the chip select signal output terminal of the first device 100 and the redundant signal output terminals of the second device to the M-1th device to be high level, and further sets the redundant signal output terminal of the M-1th device to a low level, so that the chip select signal input terminal of the Mth device is low level.

[0115] exist Figure 4 Specifically, after the chip select signal output terminal of the first device 100 outputs a high level, the second device first receives the high level, the redundant signal output terminal LED7 / CS2 of the second device is first set to a high level, and then the redundant signal output terminal LED7 / CS2 of the second device is switched to a low level, so that the chip select signal input terminal CS of the Mth device is a low level, ensuring that only one Mth device is selected for operation.

[0116] Through the above technical solution, by accurately controlling the level state of the chip select signal input terminal of each slave device, it is ensured that only one slave device is activated at any time, thereby avoiding data conflicts and communication errors.

[0117] Optionally, in some embodiments, the signal output module includes: a storage unit for setting a preset duration; a counting unit for accumulating a first duration after the chip select signal input terminal of the Mth device switches from the first level to the second level, and / or a second duration after the chip select signal input terminal of the Mth device switches from the second level to the first level; a comparison unit for outputting a first switching signal when the first duration is equal to the signal duration, or outputting a second switching signal when the second duration is equal to the signal duration; a signal output unit for outputting a first level according to the first switching signal, or outputting a second level according to the second switching signal.

[0118] Specifically, the preset time length is set through the register unit, that is, the chip select signal input terminal of the Mth device is set to switch after the preset time length.

[0119] The counting unit monitors the level state of the chip select signal input terminal of the Mth device. When the chip select signal input terminal switches from a low level to a high level, the counting unit begins to accumulate a first duration after the switch. Similarly, when the chip select signal input terminal switches from a high level back to a low level, the counting unit also accumulates a second duration of this process.

[0120] The comparing unit compares the first duration or the second duration accumulated by the counting unit with the preset duration in the register unit, and outputs a first switching signal when the first duration is equal to the signal duration, or outputs a second switching signal when the second duration is equal to the signal duration;

[0121] The signal output unit adjusts its output level according to the switching signal output by the comparison unit. If the first switching signal is received, the signal output unit outputs a low level. If the second switching signal is received, the signal output unit outputs a high level.

[0122] For example, the internal control logic diagrams of the second to Nth devices are as follows: Figure 5 As shown, the second through Nth devices primarily use a timer (the signal output module mentioned above) to automatically control the high and low voltage levels of external pins. The timer internally contains a counter (the counting unit) driven by an external crystal oscillator and a timeout setting register (the register unit). Software running in the first device (typically a processor) can configure or control these via the SPI interface. Assume the frequency of the external crystal oscillator is 100, meaning it can generate 100 clocks per second. Once the counter is cleared and enabled by software, it will continue to increment at a rate of 100 per second. If the software writes 200 to the timeout setting register in advance, the value in the counter will match the value in the timeout setting register after two seconds. Upon detecting this, the comparator (the comparison unit) will output a logic signal that is the opposite of the previous one (for example, a value originally 0 will be changed to 1), driving the subsequent level output control module (the signal output unit) to transmit the corresponding high and low voltage levels to the outside of the chip.

[0123] Through the above technical solution, by measuring the time through the signal output module, the chip select signal input terminal state of the Mth device can be accurately switched when needed, ensuring the correctness and integrity of data transmission and operation, avoiding communication errors or data loss due to improper state switching or delays, thereby enhancing the stability and reliability of the system.

[0124] Optionally, in some embodiments, the control module 300 further includes: a second control unit, configured to set the redundant signal output terminal of the M-1 device to the second level after completing the operation on the Mth device within a preset time period, so that the chip select signal input terminal of the Mth device is the second level.

[0125] It is understandable that if within the preset time period, if the second control unit detects that the first device 100 completes the operation on the Mth device, the chip select signal input terminal of the M-1th device is set to a high level. Figure 4 In the example, the chip select signal input terminal CS of the first device is set to a high level, and the redundant signal output terminal LED7 / CS2 of the second device is switched to a high level. At this time, the chip select signal to the Mth device is invalid, and the Mth device is not selected.

[0126] Through the above technical solution, the second control unit ensures that the Mth device is correctly disabled after completing all operations within a preset time period, which helps to prevent data conflicts between multiple devices.

[0127] Optionally, in some embodiments, the control module 300 further includes: a third control unit, configured to set the chip select signal output terminal of the first device to the second level after setting the redundant signal output terminal of the M-1th device to the second level.

[0128] It can be understood that after the redundant signal output terminal of the M-1th device is set to a high level, Figure 4 That is, after the redundant signal output terminal of the second device is changed to a high level, the chip select signal output terminal CS1 of the first device 100 is also set to a high level, and the operation of accessing other slave devices can be performed.

[0129] With the above technical solution, by setting the chip select signal output terminal of the first device to the second level, the first device no longer communicates with any slave device and can freely prepare for the next access or perform other tasks.

[0130] Optionally, in some embodiments, when the redundant signal output terminal of any device from the second to the Nth device is at the first level, the chip select signal output terminal of the first device and the redundant signal output terminals of all remaining devices are at the second level.

[0131] It can be understood that when the redundant signal output terminal of any device from the second to the Nth device is at a low level, for example, the redundant signal output terminal of the second device outputs a low level, then the chip select signal output terminal of the first device 100 connected to the chip select signal input terminal of the second device and the redundant signal output terminals of all remaining devices all output a high level.

[0132] by Figure 4 For example, if the redundant signal output terminal LED7 / CS2 of the second device is at a low level, it means that the first device 100 accesses the Mth device. If the redundant signal output terminal of the Mth device is also at a low level, it means that the first device 100 also accesses the M+1th device. If the Mth device and the M+1th device are accessed at the same time, the MOSI signal sent by the first device 100 will be received by both the Mth device and the M+1th device, which may easily cause signal communication confusion or loss. Therefore, it is necessary to output a high level from the chip select signal output terminal of the first device 100 and the redundant signal output terminal of the slave device 0.

[0133] With the above technical solution, by ensuring that only one slave device is activated at any given moment, the risk of data loss or error caused by multiple devices communicating simultaneously is reduced.

[0134] In order to make the purpose, technical solutions and advantages of this application clearer, the present application will be described in further detail below. Obviously, the embodiments described are only part of the embodiments of this application and do not represent all embodiments. Figure 4 and Figure 6shown.

[0135] There are one or more slave devices in the current system. The slave devices have independent pins that are not actually used and can be set to high level by default. They can automatically return to high level after being configured to maintain a low level for a period of time. The most typical one is the LED control device, which has 8 (LED0~LED7) output pins, which can control the on, off, and flashing of 8 LEDs respectively, and can control the flashing frequency. If only 7 (LED0~LED6) are actually used, then the remaining output pin (LED7) has the properties described above, that is, pin LED7 can switch between low level and high level based on the preset frequency. Therefore, pin LED7 can be used as the chip select signal of other slave devices, such as Figure 4 shown.

[0136] by Figure 4 For example, consider the second device (hereafter referred to as "slave 1") and the third device (hereafter referred to as "slave 2"). Each has its own LED controller chip, each accessed via the SPI bus from the first device. Each chip can control eight LEDs (LED0 through LED7). The master device has only two chip select signals (CS0 and CS1), but there are three slave devices (Slave 0, Slave 1, and Slave 2) that need to be connected. In this case, connect the chip select input CS of slave 2 to the redundant signal output LED7 / CS2 of slave 1. (Note: This signal is not actually connected to the LEDs; it serves as the chip select line for slave 2, so you only need to focus on its voltage level and not on how to drive the LEDs.) Set the LED7 / CS2 control signal to a default high level, making slave 2 unselected by default. Slave 2's other SPI signal terminals (MOSI, MISO, and SCK) are connected directly to the master device, just like the other slave devices.

[0137] Before accessing slave device 2, slave device 1 must be configured. Specifically, the automatic high-low switching frequency of the LED module's redundant signal output, LED7 / CS2, (i.e., the flashing frequency of the original controlled LED) must be set. LED7 / CS2 should be set high, and the flashing sequence should begin low-->high-->low. Assuming the LED is set to flash five times per second, there will be 10 high-low switchings per second. After LED7 / CS2 is set low, it automatically switches from low to high after 100ms. To access slave device 2, slave device 1 must be accessed first, setting the LED7 / CS2 control signal low. This activates the chip select input CS of slave device 2. Access to slave device 2 must be completed within 100ms. After 100ms, the LED7 / CS2 control signal automatically switches high, deactivating the chip select input of slave device 2. The master device then accesses slave device 1, disabling the flashing function of LED7 and restoring the high level.

[0138] In the embodiment of this application, Figure 4 The solution shown requires modifying the device tree source file. The modified code is as follows.

[0139] gpio0:gpio@3f8019000{ / / Add a GPIO controller to the system

[0140] compatible = "snps,dw-apb-gpio"; / / compatible and uses the GPIO driver named "snps,dw-apb-gpio"

[0141] reg = <0x3 0xf8019000 0x0 0x1000>; / / The physical address of the actual GPIO controller

[0142] #address-cells= <1> ;

[0143] #size-cells= <0> ;

[0144] porta:gpio-controller@0{ / / Add a GPIO port named porta, which actually manages 8 GPIO pins.

[0145] compatible="snps,dw-apb-gpio-port";

[0146] gpio-controller;

[0147] #gpio-cells= <2> ;

[0148] ngpios= <8> ; / / Use 8 GPIOs in total

[0149] reg= <0> ;

[0150] };

[0151] ctl_spi:spi{ / / Add an SPI controller to the system

[0152] compatible = "spi-gpio"; / / compatible and use the boot named "spi-gpio"

[0153] #address-cells= <1> ;

[0154] #size-cells= <0> ;

[0155] num-chipselects= <2> ; / / Support 2 native chip select signals

[0156] ext-num-chipselects= <1> ; / / Additionally support 1 extended chip select signal

[0157] cs0-gpios=<&porta 0 1>; / / Chip select 0 is GPIO pin 0 of porta, and the following 1 indicates that the low level is valid

[0158] cs1-gpios=<&porta 1 1>; / / Chip select 1 is GPIO pin 1 of porta

[0159] cs2-ext=<&led_dev 7 1>; / / Chip select 2 is the 7th LED control signal of the LED module, low level is valid

[0160] sck-gpios = <&porta 3 0>; / / The clock signal uses porta's GPIO pin 3

[0161] miso-gpios = <&porta 4 0>; / / MISO signal uses porta's GPIO pin 4

[0162] mosi-gpios = <&porta 5 0>; / / MOSI signal uses porta's GPIO pin 5

[0163] eth_dev@0{ / / Add the 0th SPI slave device

[0164] compatible="eth_dev"; / / compatible and using a certain network module driver

[0165] spi-max-frequency = <1000000>0>; / / Maximum SPI clock frequency supported by the device

[0166] };

[0167] led_dev@1 { / / Add the first SPI slave device

[0168] compatible = "led_dev"; / / Compatible with and use a certain LED module driver

[0169] led_num = <8>; / / Support controlling 8 LED lights

[0170] led7_twinkle_freq = <5>; / / Set the blinking frequency of LED7 to 5, that is, 10 high and low level switches per second

[0171] spi-max-frequency = <5000000>; / / Maximum SPI clock frequency supported by the device

[0172] };

[0173] sensor_dev@2 { / / Add the second SPI slave device

[0174] compatible = "sensor_dev"; / / Compatible with and use a certain sensor module driver

[0175] spi-max-frequency = <8000000>; / / Maximum SPI clock frequency supported by the device

[0176] };

[0177] };

[0178] In the device tree source file, the chip select signals directly supported by SPI are changed from 3 to 2, and a new extended chip select signal (cs2-ext) is added. In addition, the chip select signal of slave device 2 is set to the output signal of slave device 1 (LED7), and the automatic blinking frequency of LED7 is set to 5, that is, the high and low level switching frequency is 10, ensuring that after it becomes low level, it automatically becomes high level after 100 ms. All configurations in the device tree source file will be parsed and used by the driver, thereby enabling the driver to understand Figure 4 the hardware topology.

[0179] Next, the driver needs to be modified for the extended chip select signal. Figure 6 Shows the process of accessing slave device 2 in the driver. The logic of accessing the native chip select in the driver remains unchanged. Specifically:

[0180] Step S601: pull down the chip select signal CS1 of the first device, that is, the slave device 1 (ie, the LED module) is selected;

[0181] Step S602: Configure the LED module, set the flashing frequency of LED7, and set LED7 to a high level;

[0182] Step S603: Set LED7 to low level (equivalent to CS2 being valid) and start blinking, that is, slave device 2 is in selected state;

[0183] Step S604: Start a 100ms software timer;

[0184] Step S605: pull up the chip select signal CS1 of the first device, that is, no longer select the LED module;

[0185] Step S606: Control the MOSI and MISO terminals of the first device to communicate with the slave device 2;

[0186] Step S607: Wait for the software timer to count;

[0187] Step S608: At this time, the LED7 control signal becomes high, that is, CS2 automatically becomes high, and slave device 2 is not selected;

[0188] Step S609: pull down the chip select signal CS1 of the first device, that is, the slave device 1 is in the selected state, that is, the LED module is in the selected state;

[0189] Step S610: Configure the LED module, set LED7 to a high level, and stop the LED from flashing;

[0190] Step S611: pull up the chip selection signal CS1 of the first device, that is, the LED module is in the unselected state.

[0191] It can be expanded. Figure 4 The LED module in the circuit is not necessarily controlled by SPI signals, but can also be controlled by other signals such as I2C, as long as its output signal LED7 can be used as a chip select signal.

[0192] In addition, if Figure 4 Slave device 2 in the example also has pin properties similar to LED7 and can be used as a chip select signal again to expand more levels of slave devices. Theoretically, there is no upper limit on the number.

[0193] According to the multi-device communication system proposed in the embodiment of the present application, when the control module determines the Mth device to be accessed from the second to Nth devices, the chip select signal input of the Mth device is set to a first level through the chip select signal output of the first device connected to the chip select signal input of the second device and the redundant signal outputs of all devices between the first device and the Mth device, thereby completing the operation on the Mth device within a preset time. This solves the existing solution of accessing devices through GPIO emulation of SPI controllers, which requires an independent chip select signal from the CPU for each additional access device. The increase in devices requires an expensive CPU or an IO expansion chip, which increases costs. In the case where the chip select signal of the first device is insufficient, the present application utilizes the output signals of certain slave devices. By adding software timers, modifying device tree source files and drivers, and other methods, it supports more slave devices and reduces the overall production cost of the product.

[0194] Next, the multi-device communication method proposed in accordance with an embodiment of the present application will be described with reference to the accompanying drawings.

[0195] Figure 7 It is a flowchart of the multi-device communication method according to an embodiment of the present application.

[0196] like Figure 7 As shown, the multi-device communication method includes the following steps:

[0197] In step S701, a first device is determined, and an Mth device to be accessed is determined from the second to Nth devices.

[0198] In step S702, the chip select signal input terminal of the Mth device is set to the first level through the chip select signal output terminal of the first device connected to the chip select signal input terminal of the second device and the redundant signal output terminals of all devices between the first device and the Mth device, and the operation on the Mth device is completed within a preset time length, where 2≤M≤N.

[0199] It should be noted that, for the description of the features in the embodiment corresponding to the multi-device communication method, reference can be made to the relevant description of the embodiment corresponding to the above-mentioned multi-device communication system, and no further details will be given here.

[0200] Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. The electronic device may include:

[0201] A memory 801 , a processor 802 , and a computer program stored in the memory 801 and executable on the processor 802 .

[0202] When the processor 802 executes the program, the multi-device communication method provided in the above embodiment is implemented.

[0203] Furthermore, the electronic device further includes:

[0204] The communication interface 803 is used for communication between the memory 801 and the processor 802 .

[0205] The memory 801 is used to store computer programs that can be run on the processor 802.

[0206] The memory 801 may include a high-speed RAM memory, and may also include a non-volatile memory (non-volatile memory), such as at least one disk memory.

[0207] If the memory 801, processor 802, and communication interface 803 are implemented independently, the communication interface 803, memory 801, and processor 802 can be interconnected via a bus and communicate with each other. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 8 Only one thick line is used in the diagram, but this does not mean that there is only one bus or one type of bus.

[0208] Optionally, in a specific implementation, if the memory 801, the processor 802 and the communication interface 803 are integrated on a chip, the memory 801, the processor 802 and the communication interface 803 can communicate with each other through an internal interface.

[0209] The processor 802 may be a central processing unit (CPU), an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present application.

[0210] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above-mentioned multi-device communication method embodiments when run.

[0211] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0212] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0213] The above is a detailed introduction to a multi-device communication system and method, electronic device, and storage medium provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A multi-device communication system, characterized in that: include: a first device, the first device comprising at least one chip select signal output terminal; The second to Nth devices each include a chip select signal input terminal, a signal output module and at least one redundant signal output terminal connected in sequence, the chip select signal input terminal of the second device is connected to any chip select signal output terminal of the first device, and the chip select signal input terminal of the third to Nth devices is connected to any redundant signal output terminal of the second to N-1th devices in a one-to-one correspondence, and the signal output module is used to output a first level or a second level, N≥2; A control module, used for, when the Mth device to be accessed is determined from the second to Nth devices, setting the chip select signal input terminal of the Mth device to a first level in sequence through the chip select signal output terminal of the first device connected to the chip select signal input terminal of the second device and the redundant signal output terminals of all devices between the first device and the Mth device, and completing the operation on the Mth device within a preset time length, wherein 2≤M≤N.

2. The multi-device communication system according to claim 1, characterized in that: The control module comprises: A first control unit is used to sequentially set the chip select signal output end of the first device and the redundant signal output ends of the second device to the M-1th device to be at a second level, and then set the redundant signal output end of the M-1th device to the first level, wherein the second level is opposite to the first level.

3. The multi-device communication system according to claim 1, characterized in that: The signal output module comprises: A storage unit, used for setting the preset duration; a counting unit, configured to accumulate a first duration after the chip select signal input terminal of the Mth device switches from the first level to the second level, and / or a second duration after the chip select signal input terminal of the Mth device switches from the second level to the first level; a comparing unit, configured to output a first switching signal when the first duration is equal to the signal duration, or to output a second switching signal when the second duration is equal to the signal duration; A signal output unit is configured to output a first level according to the first switching signal, or to output a second level according to the second switching signal.

4. The multi-device communication system according to claim 1, characterized in that: The control module further includes: The second control unit is used to set the redundant signal output end of the M-1th device to the second level after completing the operation on the Mth device within the preset time period, so that the chip select signal input end of the Mth device is at the second level.

5. The multi-device communication system according to claim 4, characterized in that: The control module further includes: A third control unit is configured to set the chip selection signal output terminal of the first device to the second level after setting the redundant signal output terminal of the M-1th device to the second level.

6. The multi-device communication system according to claim 1, characterized in that: When the redundant signal output terminal of any device from the second to the Nth devices is at the first level, the chip selection signal output terminal of the first device and the redundant signal output terminals of all remaining devices are at the second level.

7. The multi-device communication system according to any one of claims 1 to 6, characterized in that: All redundant signal output terminals of the second to Nth devices may be configured to switch between the first level and the second level based on a preset frequency.

8. A multi-device communication method, characterized in that: The method is applied to a multi-device communication system according to any one of claims 1 to 7, wherein the method comprises the following steps: Determine a first device, and determine an Mth device to be accessed from the second to Nth devices; The chip select signal input terminal of the Mth device is set to the first level through the chip select signal output terminal of the first device connected to the chip select signal input terminal of the second device and the redundant signal output terminals of all devices between the first device and the Mth device, and the operation of the Mth device is completed within a preset time length, wherein 2≤M≤N.

9. An electronic device, characterized in that: The system comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the multi-device communication method as claimed in claim 8.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: The program is executed by a processor to implement the multi-device communication method according to claim 8.

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