Reset latch capable of resisting single event transient and single event upset

Abstract

The invention relates to an anti-single event transient and anti-single event upset reset latch, which can normally provide a reset signal required by a latch circuit when the reset signal end has no external transient pulse input by improving and designing the circuit structure of the reset signal end and introducing reset signal redundancy design into the latch circuit. When an external transient pulse is input at a reset signal end, the influence of the transient state on a subsequent reset signal is eliminated through the delay judgment redundant circuit, so that the influence of the transient state from the reset signal end on the storage state of the reset register is eliminated, and the reset precision of the reset register is improved. The external input transient of the reset signal end is effectively reinforced, and finally the single event transient and single event upset resistance of the reset latch is further improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit design, and relates to a reset latch for single event transient (SET) and single event upset (SEU) immunity. Background Art

[0002] In the space environment, various radiation particles (such as heavy ions, protons, neutrons, and electrons) and high-energy rays (such as γ-rays and x-rays) widely exist. Bombardment of semiconductor devices by high-energy particles or rays can cause various types of failures of the devices, seriously reducing the reliability of integrated circuits in spacecraft control systems, shortening the service life of spacecraft or even damaging the spacecraft, resulting in irreparable losses. Therefore, it is necessary to perform radiation hardening design on integrated circuits to improve their reliability in the space environment.

[0003] Standard cells are the basis of chip design. Strengthening the design of standard cells can effectively improve the reliability of space-grade chips. Among the standard cells, the sequential logic cell is the key to storing data, and the DICE (dual interlocked storage cell) hardening design is most commonly used for sequential logic cells. However, bombardment of sensitive nodes (such as the reset signal terminal) in the sequential logic cell itself by high-energy particles or rays can also cause abnormal sampling of the latch circuit, resulting in single event upset of the sequential logic cell. Therefore, how to perform hardening design for external input transients at the reset signal terminal has become a technical problem to be solved. Summary of the Invention

[0004] In view of the problems existing in the above-mentioned traditional technologies, the present invention proposes a reset latch for single event transient and single event upset immunity, which can effectively perform hardening design for external input transients at the reset signal terminal.

[0005] To achieve the above object, the embodiments of the present invention adopt the following technical solutions: Provide a reset latch for single event transient and single event upset immunity, including a reset input circuit, a latch circuit, and a clock redundancy circuit; The reset input circuit includes a delay module and a decision maker. The input terminal of the delay module and the first input terminal of the decision maker are both used to access the reset signal. The output terminal of the delay module is connected to the second input terminal of the decision maker. The first output terminal of the decision maker is used to output a second reset signal, and the second output terminal of the decision maker is used to output a first reset signal. The clock output terminal of the clock redundancy circuit is connected to the clock input terminal of the latch circuit; In the latch circuit, the inverter INVa in the latch circuit is connected to the first reset signal and the second reset signal through a first P-type transistor and a first N-type transistor respectively. The inverter INVb in the latch circuit is connected to the second reset signal and the first reset signal through a second P-type transistor and a second N-type transistor respectively.

[0006] In one embodiment, the delay module includes a delay BUF.

[0007] In one embodiment, the decision maker is a simple decision circuit based on a comparator, a re-threshold decision circuit, or a decision circuit based on Gaas.

[0008] In one embodiment, the clock redundancy circuit includes a first inverter INV1, a second inverter INV2, a third inverter INV3, and a fourth inverter INV4. The input terminals of the first inverter INV1 and the third inverter INV3 are both used to access the clock signal CK. The output terminal of the first inverter INV1 is connected to the input terminal of the second inverter INV2, and the output terminal of the third inverter INV3 is connected to the input terminal of the fourth inverter INV4; The output terminal of the first inverter INV1 is respectively connected to the first clock input terminal of the second data input circuit and the second clock input terminal of the second feedback circuit in the latch circuit. The output terminal of the fourth inverter INV4 is respectively connected to the second clock input terminal of the second data input circuit and the first clock input terminal of the second feedback circuit in the latch circuit; The output terminal of the second inverter INV2 is respectively connected to the second clock input terminal of the first data input circuit and the first clock input terminal of the first feedback circuit in the latch circuit. The output terminal of the third inverter INV3 is respectively connected to the first clock input terminal of the first data input circuit and the second clock input terminal of the first feedback circuit in the latch circuit.

[0009] One of the above technical solutions has the following advantages and beneficial effects: The above-mentioned reset latch for anti-single event transient and anti-single event upset can, by improving the circuit structure of the reset signal terminal and introducing a reset signal redundancy design in the latch circuit, normally provide the reset signal required by the latch circuit when there is no external transient pulse input at the reset signal terminal, realize the precise reset operation of different transmission branches, and when there is an external transient pulse input at the reset signal terminal, eliminate the influence of the transient on the subsequent reset signal through the delay decision redundancy circuit, thereby eliminating the influence of the transient from the reset signal R terminal on the storage state of the reset register, effectively realizing the reinforcement design for the external input transient of the reset signal R terminal, and ultimately further improving the performance of the reset latch against single event transient and single event upset. Description of the Drawings

[0010] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or in the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0011] Figure 1Schematic diagram of the circuit design of the existing reset signal terminal; Figure 2 Schematic diagram of the circuit module structure of the latch circuit of the reset latch for single event transient and single event upset resistance in one embodiment; Figure 3 Schematic diagram of the circuit module structure of the reset input circuit of the reset latch for single event transient and single event upset resistance in one embodiment; Figure 4 Schematic diagram of the circuit module of the clock redundancy circuit of the reset latch for single event transient and single event upset resistance in one embodiment; Figure 5 Schematic diagram of the circuit structure of the latch circuit of the reset latch for single event transient and single event upset resistance in another embodiment; Figure 6 Schematic diagram of the circuit structure of the clock redundancy circuit of the latch circuit of the reset latch for single event transient and single event upset resistance in another embodiment. Detailed implementation manners

[0012] In order to make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present invention belongs. The terms used in the description of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention.

[0013] It should be noted that referring to "embodiment" herein means that a specific feature, structure or characteristic described in combination with the embodiment may be included in at least one embodiment of the present invention. Displaying this phrase at various positions in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art can understand that the embodiments described herein can be combined with other embodiments. The term "and / or" used in the description and claims of the present invention refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0014] The following will describe the embodiments of the present invention in detail with reference to the accompanying drawings in the embodiments of the present invention.

[0015] Such as Figure 1The circuit design of the reset signal terminal shown cannot effectively shield the transient input from the outside of the reset signal terminal, so that when such a transient occurs, there will be a 010 pulse in the subsequent reset signal R1, causing the latch to be reset incorrectly and posing an irradiation risk. Among them, the P transistor represents a P-type MOS transistor, the N transistor represents an N-type MOS transistor, and R1 represents the reset signal after the reset signal R passes through two inverters (constituted by a pair of P transistors and N transistors). The same applies hereinafter. For example, Figure 1 Regarding the circuit design of the reset signal terminal shown, the present invention proposes a new reinforcement design for the reset signal terminal to eliminate the irradiation risk of the reset signal terminal and improve the radiation resistance of the reset latch at the same time, so as to enhance the reliability of the reset latch in a complex space environment and meet the application requirements of actual aerospace engineering.

[0016] In one embodiment, as Figures 2 to 4 shown, a reset latch that resists single-event transients and single-event upsets is provided, including a reset input circuit, a latch circuit 12, and a clock redundancy circuit. The reset input circuit includes a delay module and a decision maker. The input end of the delay module and the first input end of the decision maker are both used to access the reset signal R, and the output end of the delay module is connected to the second input end of the decision maker. The first output end of the decision maker is used to output the second reset signal R2, and the second output end of the decision maker is used to output the first reset signal R1. The clock output end of the clock redundancy circuit is connected to the clock input end of the latch circuit 12.

[0017] The inverter INVa in the latch circuit 12 is connected to the first reset signal R1 and the second reset signal R2 through the first P transistor 101 and the first N102 transistor respectively. The inverter INVb in the latch circuit 12 is connected to the second reset signal R2 and the first reset signal R1 through the second P transistor 103 and the second N transistor 104 respectively. The gate of the first P transistor 101 is connected to the second output end of the decision maker, the source of the first P transistor 101 is connected to the power supply voltage, and the drain of the first P transistor 101 is connected to the source of the P transistor in the inverter INVa in the latch circuit 12. The gate of the second P transistor 103 is connected to the first output end of the decision maker, the source of the second P transistor 103 is connected to the power supply voltage, and the drain of the second P transistor 103 is connected to the source of the P transistor in the inverter INVb in the latch circuit 12. The gate of the first N transistor 102 is connected to the first output end of the decision maker, the source of the first N transistor 102 is grounded, and the drain of the first N transistor 102 is connected to the output end of the inverter INVa in the latch circuit 12. The gate of the second N transistor 104 is connected to the second output end of the decision maker, the source of the second N transistor 104 is grounded, and the drain of the second N transistor 104 is connected to the output end of the inverter INVb in the latch circuit 12.

[0018] It can be understood that the latch circuit 12 can adopt the latch circuit part of various existing set latches with enhanced design in the art. The latch circuit 12 includes main structural parts such as a data input circuit 1, a data input circuit 2, an inverter INVa, an inverter INVb, an output circuit, a feedback circuit 1, and a feedback circuit 2. It is a latch circuit designed based on the DICE circuit structure. The inverter INVa and the inverter INVb in the latch circuit 12 together constitute a part of the existing DICE enhanced circuit structure of the latch, playing a key role in improving the radiation resistance and data processing reliability of the latch. The clock redundancy circuit can also adopt various existing clock circuits with enhanced design in the art. The clock redundancy circuit is used to provide various clock signals required for the normal operation of the latch circuit 12, and the inverters therein can be designed with various existing inverter structures in the art; the main improvement point of this embodiment lies in the design of the reset input circuit and its connection structure to the latch circuit 12. Transistors such as the first P transistor 101, the second P transistor 103, the first N transistor 102, and the second N transistor 104 can all adopt the P and N transistor devices used in the existing latch circuits in the art. The power supply voltage refers to the voltage provided to ensure the normal operation of each transistor device in the reset latch, such as the voltage VDD. D is the data terminal input of the latch circuit 12, and Q is the output terminal of the latch circuit 12.

[0019] Specifically, as Figure 2 shown is the schematic diagram of the circuit module structure of the latch circuit 12. As Figure 3 shown is the schematic diagram of the circuit module structure of the reset input circuit. The connection structure of the delay module and the decision maker constitutes a delay decision redundancy circuit structure. When there is no external transient pulse input at the reset signal terminal, this structure can normally generate two reset signals based on the reset signal R through decision-making. These two reset signals form reset redundancy and are used to be connected to the latch circuit 12 for use. At this time, the delay module can be configured to pass through the normal input reset signal R according to the set delay, and the decision maker makes a decision output based on the two reset signals with different delays input. When there is an external transient pulse input at the reset signal terminal, since the delay of the transient pulse input by the delay module becomes an unknown delay amount, the decision maker cannot judge the transient pulse, and thus will not generate an effective decision output. Finally, the state of the two reset signals that already exist at the output terminal of the decision maker is maintained unchanged, thereby isolating the influence when there is an external transient pulse input at the reset signal terminal from being transmitted to the subsequent circuit.

[0020] As Figure 2As shown, the reset latch has three input terminals and one output terminal. The three input terminals are the clock signal CK terminal, the data input signal D terminal, and the reset signal terminal respectively, and the output terminal is the Q terminal. The reset signal R undergoes delay and decision processing by the reset input circuit and outputs the first reset signal R1 and the second reset signal R2. The data D passes through the inverters controlled by the clock signal nclk, the clock signal nclk1, the clock signal bclk, and the clock signal bclk1 in the data input circuit to output the signal ND1 and the signal ND2, and the signal ND1 and the signal ND2 are output as Q through the inverters in the output circuit. In addition, the reset latch performs a reset operation when the reset signal R terminal is at a high level, or it can be set to perform a reset operation when the reset signal R terminal is at a low level according to application requirements. In this specification, the case where the reset signal R terminal is at a high level for the reset operation is taken as an example for elaboration.

[0021] When the clock signal CK is at a high level, the data D is output to the DICE circuit structure through the inverter, forming the signal ND1 and the signal ND2 in the same state, and the signal ND1 and the signal ND2 are then sent to the output Q terminal through one stage of inverter. When the clock signal CK is at a low level, the data D cannot be output to the DICE circuit structure through the inverter, but the feedback circuit of the DICE circuit structure is turned on, and the stored data is continuously output to the Q terminal. The reset signal R terminal is at a high level for the reset operation, and at this time Q is at a low level.

[0022] When a transient pulse is input to the reset signal R terminal, due to the existence of the delay decision redundancy circuit, the influence of the transient on the storage state of the latch circuit 12 can be eliminated. In addition, as Figure 2 and Figure 3 shown, the reset signal R also has a redundant connection design inside the reset latch. The redundant connection design inside the reset latch helps to avoid single event upsets caused by an error in one of the reset signals. For example, assume that the reset signal R1 (reset release is at a low level) generates a transient pulse (010) due to being bombarded by a single particle, causing the N transistor connected to the reset signal R1 inside the DICE to turn on and set low (i.e., Figure 5 the potential at point B in

[0023] When the clock signal CK is at a low level, a storage cycle is performed inside the reset latch. Assume that the voltages of node A (i.e., the output terminal of inverter INVa) and node B (i.e., the output terminal of inverter INVb) are both at a high level. Although the reset signal R is at a low level (the reset latch is in a reset release state), the reset signals R1 and R2 are at a low level state, but the drains of the P transistors connected to the reset signals R1 and R2 are sensitive points. When this sensitive point is bombarded (assuming the drain of the first P transistor 101 connected to the reset signal R1 is bombarded), the state of the reset signal R1 changes from low level to high level, forming a 010 transient. This transient forces the second N transistor 104 connected to the reset signal R1 to turn on, so node B is pulled low to a low level, but the first P transistor 101 connected to the reset signal R1 turns off, so the voltage of node A remains at the correct high level. Due to the competition between node A and node B, the Q terminal is in an indeterminate state.

[0024] After the error caused by the above transient is removed, the level state of node B automatically returns to a high level through the feedback circuit. Finally, the Q terminal returns to the normal high level state. Therefore, the reset latch can effectively improve the single-event transient and single-event upset resistance through the reinforcement design of the reset signal R terminal.

[0025] For the above single-event transient and single-event upset resistant reset latch, by improving the circuit structure of the reset signal terminal and introducing a reset signal redundancy design in the latch circuit 12, it can normally provide the reset signal required by the latch circuit 12 when there is no external transient pulse input at the reset signal terminal, realizing the precise reset operation of different transmission branches. When there is an external transient pulse input at the reset signal terminal, the influence of this transient on the subsequent reset signal is eliminated through the delay decision redundancy circuit, thereby eliminating the influence of the transient from the reset signal terminal on the storage state of the reset register, effectively realizing the reinforcement design for the external input transient at the reset signal terminal, and finally further improving the performance of the reset latch against single-event transients and single-event upsets.

[0026] In one embodiment, as Figure 4As shown, the clock redundancy circuit may include a first inverter INV1, a second inverter INV2, a third inverter INV3, and a fourth inverter INV4. The input terminals of the first inverter INV1 and the third inverter INV3 are both used to receive a clock signal CK. The output terminal of the first inverter INV1 is connected to the input terminal of the second inverter INV2, and the output terminal of the third inverter INV3 is connected to the input terminal of the fourth inverter INV4. The output terminal of the first inverter INV1 is respectively connected to the first clock input terminal of the second data input circuit and the second clock input terminal of the second feedback circuit in the latch circuit 12. The output terminal of the fourth inverter INV4 is respectively connected to the second clock input terminal of the second data input circuit and the first clock input terminal of the second feedback circuit in the latch circuit 12. The output terminal of the second inverter INV2 is respectively connected to the second clock input terminal of the first data input circuit and the first clock input terminal of the first feedback circuit in the latch circuit 12. The output terminal of the third inverter INV3 is respectively connected to the first clock input terminal of the first data input circuit and the second clock input terminal of the first feedback circuit in the latch circuit 12.

[0027] It can be understood that in this embodiment, the data input circuit 1 of the latch circuit 12 may adopt the circuit structure shown in circuit module C1, the data input circuit 2 may adopt the circuit structure shown in circuit module C2, the inverter INVa may adopt Figure 5 the circuit structure shown in, and the inverter INVb may adopt Figure 5 the circuit structure shown in. The output circuit may adopt the circuit structure shown in circuit module C7, the feedback circuit 1 may adopt the circuit structure shown in circuit module C5, and the feedback circuit 2 may adopt the circuit structure shown in circuit module C6. The circuit connections between the circuit modules may be understood by analogy with the existing same latch circuit 12 in the art. Correspondingly, each inverter of the clock redundancy circuit may adopt a common structure such as Figure 6 shown. The structures of the latch circuit 12 and the clock redundancy circuit have also been strengthened. Therefore, when combined with the strengthened reset input circuit, the anti-single event transient and single event upset performance of the reset latch can be significantly improved.

[0028] Among them, the first data input circuit is the data input circuit 1 (i.e., Figure 5 C1 in), the second data input circuit is the data input circuit 2 (i.e., Figure 5 C2 in), the first feedback circuit is the feedback circuit 1 (i.e., Figure 5 C5 in), and the second feedback circuit is the feedback circuit 2 (i.e., Figure 5 C6 in).

[0029] In one embodiment, the delay module includes a common delay BUF circuit.

[0030] It can be understood that in this embodiment, various existing ordinary delay BUF circuits in the art can be used to provide the required precise delay, and the circuit structure is simple and the applicability is good.

[0031] In one embodiment, the decision maker is a simple decision circuit based on a comparator, a multi-threshold decision circuit, or a decision circuit based on Gaas.

[0032] It can be understood that in this embodiment, any of the previous decision circuits can be used. Among them, the simple decision circuit based on a comparator is composed of a comparator, which compares the input signal with a reference voltage (threshold voltage). When the input signal voltage is higher than the reference voltage, the comparator outputs a high level; when the input signal voltage is lower than the reference voltage, the comparator outputs a low level, so as to realize the decision output of the input signal.

[0033] The multi-threshold decision circuit includes n*(k - 1) groups of comparators and n*(k - 1) - 1 groups of multiplexers. Each group of comparators includes m comparators, and each group of multiplexers includes m multiplexers. The input ends of the n*(k - 1) groups of comparators respectively input the flip function values of m bit positions. One of the two input ends of each group of multiplexers is connected to the output end of a group of comparators, and the other is connected to the output end of another group of multiplexers. The output end of the first group of multiplexers outputs data. The two input ends of the last group of multiplexers are respectively connected to the output ends of the last two groups of comparators, which can realize the decision of multiple thresholds. Therefore, it can also be used to realize the decision output required by this embodiment.

[0034] The decision circuit based on Gaas is composed of a comparator circuit and a latch circuit. The basic device is a 1μm depletion-mode Gaas MESFET transistor. The comparator circuit adopts a cascode differential circuit form to obtain a higher circuit gain. The latch circuit adopts a dual-clock D flip-flop, and the output of each stage of the circuit adopts a source follower form, which plays the role of level shift and enhanced driving ability. In this embodiment, in some scenarios where the circuit volume of the reset signal R terminal can be allowed to increase, this Gaas-based decision circuit can also be used to realize the decision output required by this embodiment.

[0035] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combinations of these technical features do not conflict, they should all be considered to be within the scope described in this specification.

[0036] The above embodiments merely represent several implementation manners of the present invention. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the protection scope of the invention. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, which all fall within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the appended claims.

Claims

1. A reset latch resistant to single-particle transient and single-particle upset, characterized in that: It includes a reset input circuit, a latch circuit and a clock redundancy circuit; The reset input circuit includes a delay module and a decision device, the input end of the delay module and the first input end of the decision device are both used to access the reset signal, the output end of the delay module is connected to the second input end of the decision device, the first output end of the decision device is used to output the second reset signal, the second output end of the decision device is used to output the first reset signal, and the clock output end of the clock redundancy circuit is connected to the clock input end of the latch circuit; The inverter INVa in the latch circuit is connected to the first reset signal and the second reset signal through the first P transistor and the first N transistor respectively, and the inverter INVb in the latch circuit is connected to the second reset signal and the first reset signal through the second P transistor and the second N transistor respectively.

2. The single-event transient and single-event upset resistant reset latch according to claim 1, characterized in that: The delay module includes a delay BUF circuit.

3. The single-event transient and single-event upset resistant reset latch according to claim 1 or 2, characterized in that: The decision device is a simple decision circuit based on a comparator, a heavy threshold decision circuit or a decision circuit based on Gaas.

4. The single-event transient and single-event upset resistant reset latch according to claim 3, characterized in that: The clock redundancy circuit comprises a first inverter, a second inverter, a third inverter and a fourth inverter, the input end of the first inverter and the input end of the third inverter are both used to access the clock signal CK, the output end of the first inverter is connected to the input end of the second inverter, and the output end of the third inverter is connected to the input end of the fourth inverter; The output end of the first inverter is respectively connected to the first clock input end of the second data input circuit in the latch circuit and the second clock input end of the second feedback circuit, and the output end of the fourth inverter is respectively connected to the second clock input end of the second data input circuit in the latch circuit and the first clock input end of the second feedback circuit; The output end of the second inverter is respectively connected to the second clock input end of the first data input circuit in the latch circuit and the first clock input end of the first feedback circuit, and the output end of the third inverter is respectively connected to the first clock input end of the first data input circuit in the latch circuit and the second clock input end of the first feedback circuit.

Images