Feedback control high-speed transmitter

Abstract

The differential signaling transmitter circuitry (300) includes upper and lower driver stacks (220HU, 220HL, 220LU, 220LL), and first and second control loops (340, 345). The first control loop (340) generates a first bias voltage (NBIASREF) from a replica of a transistor in one of first and second drive stacks (220HL, 220LL) for a first pre-driver (330L) associated with the first and second drive stacks (220HL, 220LL). The second control loop (345) generates a second bias voltage (PBIASREF) from a replica of a transistor in one of third and fourth drive stacks (220HU, 220LU) based on the first bias voltage (NBIASREF) for a second pre-driver (330H) associated with the third and fourth drive stacks (220HU, 220LU). First and second switching circuitry (320U, 320L) couple outputs of the first and second pre-drivers (320, 330) to corresponding upper and lower driver stacks in response to a data signal (DATA).

Description

BACKGROUND OF THE INVENTION

[0001] This specification relates to data communications, and more particularly, to a transmitter circuit system for high-speed balanced differential signaling in a high-voltage environment.

[0002] Modern vehicles may contain up to fifty or more computing devices, such as microprocessors and microcontrollers, for monitoring and controlling various functions. These functions include sophisticated engine control to achieve desired performance levels, fuel economy, and environmental emissions compliance, as well as advanced diagnostics, safety systems, comfort and convenience features, and the like. Electric and hybrid vehicles may also include processors and logic devices in motor drive and charging subsystems. The distributed computing architecture implemented by these numerous computing devices significantly reduces the number of wires in the vehicle, thereby reducing the vehicle's weight.

[0003] The computing devices and subsystems within each vehicle communicate with each other to coordinate their operations. The Controller Area Network (CAN) standard (ISO 11898) and corresponding specifications promulgated by the International Organization for Standardization (ISO) and adopted in the industry (all of which are incorporated herein by reference in their entirety) define the format and protocol for digital information communication between vehicle modules. The CAN standard defines a multi-master serial broadcast communication protocol in which the vehicle's integrated wiring harness is replaced by a two-wire bus. Since many of the messages transmitted within the vehicle (e.g., measurements of temperature, RPM, etc.) are relatively short, communication under the CAN standard takes the form of short messages broadcast across the network, rather than point-to-point transmission of large blocks of data under the supervision of a central bus master.

[0004] The CAN standard implements balanced differential signaling when transmitting binary data signals over the network, e.g., at data rates up to 8 Mbps in the CAN FD standard ISO 11898-2 (incorporated herein by reference). This differential signaling prevents external coupling of noise because the signals on each side of the differential pair (referred to as CANH and CANL) change symmetrically, such that combined noise causes destructive interference. The high immunity to electrical interference provided by this signaling scheme, as well as the CAN standard's ability to self-diagnose and correct data errors, enables the implementation of CAN networks in applications outside of the automotive domain. For example, CAN networks are now also popular in various industries including building automation, medical systems, and manufacturing operations.

[0005] Recently, a higher data rate version of the CAN standard, called CAN XL, has been proposed, with an expected data rate of up to or greater than 15 Mbps. To achieve these higher data rates, many of the electrical specifications of CAN XL have been significantly tightened compared to the CAN FD standard. These specifications include more stringent limits on differential signaling voltages, including limits on high and low voltage levels, differential signaling voltages, and symmetry specifications.

[0006] In addition, since CAN networks are typically implemented in automotive applications, CAN transceivers must be able to withstand high DC voltages (e.g., ±58 V) on the CANH and CANL buses. Some CAN FD half-bridge drivers, such as the TCAN1044 and TCAN1062 CAN FD transceivers available from Texas Instruments Incorporated, include high-voltage blocking transistors in the driver stack to provide protection against these high DC bus voltages. CAN XL transceivers also need to withstand these possible high DC bus voltages.

[0007] In addition to these strict specifications, compared to CAN FD which only drives differential bus signals in the dominant phase (bus CANH is driven high and bus CANL is driven low), the current draft specifications of CAN XL require differential signaling for both dominant and recessive signal phases. Therefore, CAN XL requires a full H-bridge driver architecture to drive high and low voltage levels on both buses (CANH and CANL). Although H-bridge driver architectures, such as the THVD24XX series RS-485 transceivers available from Texas Instruments, are known in the industry, the DC electrical specification limits of these devices are significantly relaxed compared to the expectations of CAN XL transmissions. For example, the RS-485 communication standard does not specify driver symmetry V SYM specification limits as strict as the CAN standard.

[0008] The examples described herein have arisen in this context. Summary of the Invention

[0009] In one example, a transmitter circuit system includes upper and lower driver stacks, each upper and lower driver stack having at least one upper blocking transistor and a bias transistor, and the transmitter circuit system further includes first and second control loops. The first control loop includes a replica stack that includes replicas of the bias and blocking transistors of the first of the driver stacks, and the second control loop includes a replica stack, where one replica stack has replicas of the bias and blocking transistors of the upper driver stack and where one replica stack has replicas of the bias and blocking transistors of the lower driver stack. One of the replica stacks in the second control loop receives an output from the first control loop. First and second switch circuit systems couple the outputs of the first and second control loops to the gates of the bias transistors in the upper and lower driver stacks, respectively, in response to data signals.

[0010] In another example, a differential signaling transmitter circuit system includes: a first that includes a first bias transistor having a source / drain path coupled in series with a source / drain path of at least one first blocking transistor in a first driver stack to a first terminal; and a second that includes a second bias transistor having a source / drain path coupled in series with a source / drain path of at least one second blocking transistor to a second terminal. The circuit system further includes a first replica circuit system adapted to generate a first bias reference voltage by controlling the gate voltage of a replica of the first bias transistor in a first replica stack that further includes replicas of the at least one first blocking transistor in the first driver stack such that the current conducted through the first replica stack matches the current conducted through a first resistor. A second replica circuit system is adapted to generate a second bias reference voltage by controlling the gate voltage of a replica of the second bias transistor in a second replica stack that includes the replica of the second bias transistor and replicas of the at least one second blocking transistor in the second driver stack, the second replica stack being coupled in series with a third replica stack that includes a replica of the first bias transistor and replicas of the at least one first blocking transistor in the first driver stack, the gate of the replica of the first bias transistor in the third replica stack receiving the gate voltage controlled by the first replica circuit system such that the current conducted through the second replica stack matches the current conducted through first and second resistors connected in series. First and second switch circuit systems are provided to couple first and second gate voltages corresponding to the first and second bias reference voltages, respectively, to the first and second bias transistors, respectively, in response to data signals.

[0011] In another example, a network node includes a microcontroller unit, a receiver circuitry, and a transmitter circuitry, wherein the transmitter circuitry includes upper and lower driver stacks, each upper and lower driver stack having at least one upper blocking transistor and a bias transistor, and the network node further includes first and second control loops. A first control loop in the transmitter circuitry includes a replica stack that includes replicas of the bias transistor and the blocking transistor of the first of the driver stacks, and a second control loop includes a replica stack, where one replica stack has replicas of the bias and blocking transistors of the upper driver stack and where one replica stack has replicas of the bias and blocking transistors of the lower driver stack. One of the replica stacks in the second control loop receives an output from the first control loop. First and second switch circuitry in the transmitter circuitry couple the outputs of the first and second control loops to the gates of the bias transistors in the upper and lower driver stacks, respectively, in response to data signals from the microcontroller unit.

[0012] Technical advantages achieved by one or more of these examples include the ability to transmit high-data-rate differential signaling of dominant and recessive phases with a high level of stability and symmetry in the presence of manufacturing process parameters, voltage, and temperature variations. Tolerance for a high DC level can be provided on the bus while there is little increase in bus capacitance.

[0013] Other technical advantages achieved by the examples will be apparent to those of ordinary skill in the art upon reference to the following specification and its accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1A is an electrical block diagram of a Controller Area Network (CAN) in an example.

[0015] Figure 1B is a timing diagram showing data phases at the bus in a CANXL network.

[0016] Figure 2 is in an example Figure 1A of an electrical block diagram of a data driver circuitry in a transceiver of a network node in a CANXL network.

[0017] Figure 3 is in an example Figure 1A of an electrical block diagram of a transmitter circuitry in a transceiver of a network node in a CANXL network.

[0018] Figure 4 is in an example Figure 3 of an electrical schematic of a pair of driver stacks in a transmitter circuitry.

[0019] Figure 5A is an electrical schematic diagram of a first control loop in the transmitter circuit system in the example. Figure 3

[0020] Figure 5B is an electrical schematic diagram of a second control loop in the transmitter circuit system in the example. Figure 3

[0021] Figure 6A is an electrical block diagram of the architecture of a switch circuit system in the transmitter circuit system in the example. Figure 3

[0022] Figure 6B is a timing diagram showing the switching control signal transitioning in response to the data level to be transmitted in this example.

[0023] Figure 6C is a timing diagram showing the application of a bias voltage to bias the transistors in the upper drive stack in response to Figure 6B the data transition in the example.

[0024] Figure 7 is an electrical schematic diagram of a pre-driver circuit system in the transmitter circuit system in the example. Figure 3

[0025] Figure 8A is an electrical schematic diagram of an upper switch circuit system in the transmitter circuit system in the example. Figure 3

[0026] Figure 8B is an electrical schematic diagram of a lower switch circuit system in the transmitter circuit system in the example. Figure 3

[0027] The same reference numerals or other reference indicators are used in the figures to denote features that are the same or similar (functionally and / or structurally). DETAILED DESCRIPTION

[0028] The example described in this specification is implemented in a Controller Area Network (CAN) transceiver, for example, it can be implemented in an automotive or other vehicle, as it is considered that such an implementation is particularly advantageous in this case. However, it is also considered that aspects of these examples can be beneficially applied to other applications, such as other CAN implementations and other physical layer protocols using similar signaling. Therefore, the following description is provided only as an example.

[0029] Figure 1AShows the general architecture of a Controller Area Network (CAN), for example, which can be implemented in the draft specification CiA 610-3 promulgated by the CAN in Automation (CiA) Association, which is incorporated herein by reference and is commonly referred to as the CAN XL standard for in-vehicle communication. As Figure 1A shown, the bus CANBus is a two-wire bus including lines CANH and CANL, through which data signals are serially transmitted between network nodes 102a, 102b, 102c (collectively referred to as nodes 102). Nodes 102 correspond to sensors, controllers, and / or other electronic subsystems within a vehicle and can be distributed throughout the vehicle. Each node 102 may include one or both of digital circuitry containing, for example, custom or programmable computing logic and analog circuitry arranged in a desired architecture. In this example, each of nodes 102a, 102b, 102c includes a corresponding Microcontroller Unit (MCU) 104a, 104b, 104c. Each of the MCUs 104a, 104b, 104c (referred to individually or collectively as MCU 104) is coupled to a corresponding transceiver 110a, 110b, 110c (referred to individually or collectively as transceiver 110) in its node 102. As shown in FIG. 1, each of the transceivers 110a, 110b, 110c is coupled to the lines CANH, CANL of the bus CANBus. Each node 102 includes one or more voltage regulators 106 that generate a supply voltage V CC for internal use within the node from an external voltage on line VBAT. In some cases, as shown in FIG. 1 for node 102c, if different supply voltages V CC are to be supplied to different functions within the node (e.g., when transceiver 110c is biased at V CC = 3V and MCU 104c is biased at V CC = 5V), then multiple voltage regulators 106 may be included.

[0030] Each transceiver 110 is configured and operative to transmit signals to and receive signals from other nodes 102 in the network via their transceivers 110 (e.g., data, command signals, control signals, and / or instructions). In this example, data and control signals are transmitted between each of the transceivers 110a, 110b, 110c and their corresponding MCUs 104a, 104b, 104c, such data and control signals including signals from the MCU 104 for controlling its associated transceiver 110 to transmit a corresponding dominant or recessive state on the bus CANBus, and including signals from the transceiver 110 to its associated MCU 104 indicating the sensing of a dominant or recessive state at the bus CANBus.

[0031] In some embodiments, other functions may also reside on the CANBus. For example, in some vehicles, a gateway (not shown in Figure 1A ) may be provided on the CANBus for communicating with an external system, for example, via an on-board diagnostic (OBD) port. In the CiA 610-3 draft standard, the CAN network functions as a multi-master message broadcast system, where any one of the network nodes 102a, 102b, 102c can act as a bus master communicating with one or more of the other nodes 102 using broadcast messaging.

[0032] Figure 1B Shown applied to Figure 1A the physical layer data signaling protocol in the current CAN XL specification for the CANBus in Figure 1B . The CAN XL draft standard CiA 610-3 implements balanced differential signaling, where the CANH and CANL buses are driven to differential voltages with a selected polarity to indicate "dominant" and "recessive" differential states, corresponding to the binary digital values "0" and "1", respectively. As

[0033] Figure 2 shown, the dominant phase (data state "0") under CAN XL is transmitted on the CANBus by a differential voltage with one polarity, where the CANH bus is at a higher voltage than the CANL wire, while the recessive phase (data state "1") is transmitted by a differential voltage with the opposite polarity, where the CANL bus is at a higher voltage than the CANH wire. This differential signaling under CAN XL is different from the differential signaling of the CAN FD standard, where the recessive (data level "1") state is transmitted on the CANBus by the driver circuitry, presenting a high impedance to the CANH and CANL wires, and the common-mode voltage buffers in the receiver circuitry of each node bias both the CANH and CANL wires to the common-mode voltage.

[0033] Figure 2 Shows the general architecture of an H-bridge driver 200 suitable for CAN XL differential signaling in which an example may be implemented. As Figure 2 shown, the CANH bus is driven by an upper stack 220HU and a lower stack 220HL, and the CANL bus is driven by an upper stack 220LU and a lower stack 220LL. The upper stack 220HU is coupled between a supply node configured to receive a power supply voltage V CC and the CANH bus, and the lower stack 220HL is coupled between the CANH bus and a common node or potential (e.g., a ground circuit). Similarly, the upper stack 220LU is coupled between the power supply voltage V CCBetween the bus CANL, and the lower stack 220LL is coupled between the bus CANL and the common potential. In operation, the dominant phase is driven onto the bus CANbus by turning on both the upper stack 220HU and the lower stack 220LL and turning off the lower stack 220HL and the upper stack 220LU. Conversely, the recessive phase is driven by turning on both the upper stack 220LU and the lower stack 220HL and turning off the lower stack 220LL and the upper stack 220HU.

[0034] To achieve higher data rates under the CAN XL standard, many electrical specifications have been significantly tightened. Table 1 shows some differences in certain electrical standards between the CAN FD standard (ISO 11898-2) and the draft CAN XL standard (CiA 610-3).

[0035] Table 1

[0036]

[0037] As Figure 1B shown, V OD refers to the differential voltage between the CANH and CANL buses in each of the two data states. V CANH_DOM refers to the voltage at the bus CANH in the dominant phase, while V CANL_DOM refers to the voltage at the bus CANL in the dominant phase; for the bus voltages V CANH_REC and V CANH_REC in the recessive phase, these same voltage limits apply conversely. The specification V OD indicates the required driver symmetry in both the dominant and recessive phases, defined as the ratio of the sum of the voltages driven at the bus CANH and CANL to the supply voltage V CC :

[0038] (V O(CANH) +V O(CANL) ) / V CC (1)

[0039] This driver symmetry specification will be met in both the dominant and recessive phases. As indicated in Table 1, these specifications for CAN XL are much more restrictive than the corresponding specifications in the CAN FD standard.

[0040] Especially in automotive applications, the CAN transceiver needs to withstand high DC voltages on the differential signaling lines (CANH, CANL), such as a bus voltage V BUS from -58V to +58V, and a maximum differential voltage V DIFF on the lines CANH, CANL from -45V to +45V.Therefore, CAN transceivers typically include high-voltage blocking diodes, implemented as, for example, high-voltage metal-oxide semiconductor (MOS) transistors, to protect switching transistors from high DC voltages of both polarities. However, the on-resistance (R on ) of these high-voltage MOS transistors varies with manufacturing process parameters, supply voltage, and temperature (such variations are commonly referred to as "PVT"). This variation of the on-resistance R on with PVT renders some drive stack designs, such as those currently used for single-stack CAN FD drivers, unable to meet the more stringent CAN XL specification requirements within the specified voltage and temperature ranges and the expected process variation ranges.

[0041] CAN transceivers with CAN XL capabilities are expected to operate under both the CAN XL standard and the CAN FD standard, as CAN FD signals are used for the bus arbitration phase under CAN XL. Additionally, it would be useful for transceivers supporting CAN XL to be backward compatible with traditional CAN FD networks. Therefore, it is contemplated that the transceiver will incorporate an H-bridge transmit driver for CAN XL communication, in parallel with the single-ended stacked transmit driver available for CAN FD communication. However, the CAN standard specifies a maximum bus capacitance of 50 pF for each network node, which applies to the sum of the drive capacitances of parallel CAN FD and CAN XL transceivers. Considering that some CAN FD drivers may present a bus capacitance of approximately 40 pF, this severely limits the design of CAN XL transceivers.

[0042] Figure 3 Illustrates the architecture of a transceiver circuit system 300 suitable for differential signaling on buses CANH, CANL and constructed in an example. In the Figure 1A network architecture, the transceiver circuit system 300 (and the corresponding receiver circuit system) will be implemented in the transceiver 110 of a given network node 102. As described above with respect to Figure 2 , the H-bridge driver 200 of the transceiver circuit system 300 has outputs at buses CANH, CANL. The upper drive stack 220HU has an input coupled to the upper switch circuit system 320U to receive a bias voltage PBIASD in the dominant phase, while the lower drive stack 220LL has an input coupled to the lower switch circuit system 320L to receive a bias voltage NBIASD in the dominant phase as well. Conversely, the upper drive stack 220LU has an input coupled to the upper switch circuit system 320U to receive a bias voltage PBIASR in the recessive phase, and the lower drive stack 220HL has an input coupled to the lower switch circuit system 320L to receive a bias voltage NBIASR in the recessive phase as well.

[0043] For the application of the transmitter circuit system 300 in a CAN XL network, the applicable symmetry specification requires that the high bus voltages V CANH_DOM and V CANL_REC in the dominant and recessive phases are substantially equal to each other and that the low bus voltages V CANL_DOM and V CANH_REC in the dominant and recessive phases are also substantially equal to each other. Accordingly, the bias voltages PBIASD and PBIASR generated from the upper switch circuit system 320U are substantially equal to each other, and the bias voltages NBIASD and NBIASR generated from the lower switch circuit system 320L are also substantially equal to each other.

[0044] The upper switch circuit system 320U and the lower switch circuit system 320L each receive a data signal on the line DATA from the MCU 104 in their network node 102 and are used to generate and forward appropriate bias voltages PBIASD, PBIASR, NBIASD, NBIASR to the driver 200, depending on the data state to be driven. In this example, these bias voltages PBIASD, PBIASR, NBIASD, NBIASR are at levels controlled by the bias control loop 340 and the VSYM control loop 345. In Figure 3 the example, the bias control loop 340 generates a bias reference voltage NBIAS_REF, and the VSYM control loop 345 generates a bias reference voltage PBIAS_REF based in part on the bias reference voltage NBIAS_REF from the bias control loop 340.

[0045] Alternatively, the positions of the bias control loop 340 and the VSYM control loop 345 can be opposite to Figure 3 the positions shown. In this alternative embodiment, the bias control loop 340 generates a bias reference voltage PBIAS_REF, and the VSYM control loop 345 generates a bias reference voltage NBIAS_REF based in part on the bias reference voltage PBIAS_REF generated by the bias control loop 340 in this example.

[0046] In Figure 3In the example shown, where the bias control loop 340 generates a bias reference voltage NBIAS_REF, the output of the bias control loop 340 is coupled to the input of the bias reference voltage NBIAS_REF of the lower pre-driver 330L, and the output of the VSYM control loop 345 is coupled to the input of the upper pre-driver 330U. The upper pre-driver 330U buffers the bias reference voltage PBIAS_REF to a bias voltage PBIAS at its output, and the output is coupled to the input of the upper switch circuitry 320U. Similarly, the lower pre-driver 330L buffers the bias reference voltage NBIAS_REF to a bias voltage NBIAS at its output, and the output is coupled to the input of the lower switch circuitry 320L. In this example, as will be described below, the pre-drivers 330U, 330L are configured as unity-gain amplifiers, arranged as voltage followers, for example having a "class AB" output stage, so that the bias voltages output by the pre-drivers 330U, 330L are respectively at the same voltage as the bias reference voltages PBIAS_REF, NBIAS_REF generated by the VSYM control loop 345 and the bias control loop 340. Alternatively, if desired, the pre-drivers 330U and 330L can be configured to apply a gain other than unity.

[0047] In the example, the bias voltages NBIASR, NBIASD applied by the lower switch circuitry 320L to the lower drive stacks 220HL, 220LL are controlled by the bias control loop 340 to compensate for the on-resistance R on of the transistors in the lower drive stacks 220HL, 220LL. In this example, the bias control loop 340 generates this compensated bias reference voltage NBIAS_REF based on its configuration, which includes a copy of the devices in the lower drive stacks 220HL, 220LL. Similarly, the bias voltages PBIASR, PBIASD applied to the upper drive stacks 220HU, 220LU are controlled by the VSYM control loop 345 to compensate for the on-resistance R on of the transistors in the entire drive stacks of the upper drive stack 220HU and the lower drive stack 220HL and the upper drive stack 220LU and the lower drive stack 220LL. The VSYM control loop 345 is configured to include a copy of the devices in the upper drive stack 220HU and the lower drive stack 220HL (matching the devices in the drive stacks 220LU and 220LL respectively).

[0048] Figure 4Shows the construction of the upper drive stack 220HU and the lower drive stack 220LL in the example. As mentioned above, the upper drive stack 220HU and the lower drive stack 220LL are respectively used to drive the voltages on the buses CANH and CANL in the dominant phase of the differential signaling output by the transmitter circuit system 300. In this embodiment, the construction of the upper drive stack 220LU and the lower drive stack 220HL that drive the buses CANH and CANL respectively in the recessive phase is similar to Figure 4 as shown.

[0049] In this example, the upper drive stack 220HU includes a p-channel metal oxide semiconductor (PMOS) transistor 402, whose source is coupled to the V CC power supply node, and whose gate receives the bias voltage PBIASD from the upper switch circuit system 320U. In this example, the PMOS transistor 402 is configured as a low-voltage (e.g., 5V) transistor and operates in the dominant phase in response to the level of the bias voltage PBIASD that controls the voltage appearing at the bus CANH. In the recessive phase, as will be described below, the bias voltage PBIASD will be at a level that turns off the PMOS transistor 402 (e.g., V CC ).

[0050] The drain of the PMOS transistor 402 is coupled to the source of a high-voltage n-channel MOS (NMOS) transistor 404. The gate of the NMOS transistor 404 is coupled to the V CC power supply node. In this example, the NMOS transistor 404 is configured to withstand the high voltage that appears across its drain-to-source path, for example, as specified by the CAN XL standard (e.g., ±58V). For example, the NMOS transistor 404 can be configured as a laterally diffused MOS (LDMOS) transistor. The drain of the NMOS transistor 404 is coupled to the source of a PMOS transistor 406. The gate of the PMOS transistor 406 is biased at the ground circuit, and its drain is coupled to the bus CANH. In this example, the PMOS transistor 404 is configured to withstand the high voltage that appears across its drain-to-source path, for example, as a drain-extended PMOS (DEPMOS) transistor. The body node is source-connected in each of the transistors 402, 404, 406.

[0051] In this arrangement and gate biasing of the high-voltage NMOS transistor 404 and the high-voltage PMOS transistor 406 in the upper drive stack 220HU in this example, the conduction between the bus CANH and the V CC power supply node is blocked for both positive and negative high voltages, thereby protecting the PMOS transistor 402. As Figure 4As shown, the drain and source of the NMOS transistor 404 respectively form the anode and cathode of the blocking diode 414. This blocking diode 414 is reverse-biased when there is a positive high voltage at the bus CANH. Conversely, the drain and source of the PMOS transistor 406 respectively form the anode and cathode of the blocking diode 416. This blocking diode 416 is reverse-biased when there is a negative high voltage at the bus CANH. In this embodiment, the transmitter circuitry 300 is fabricated at the surface of a p-type substrate (Psub) such that a p-n junction exists between the n-type drain of the NMOS transistor 404 and the p-type substrate Psub. This forms the substrate diode 415, as Figure 4 shown, whose anode is at the substrate Psub and whose cathode is at the drain of the NMOS transistor 404. Since the NMOS transistor 404 is coupled to the bus CANH through the PMOS transistor 406, the blocking diode 416 blocks conduction from the high negative voltage at the bus CANH to the power supply node V CC and to the substrate Psub. The substrate diode 415 is reverse-biased when there is a high positive voltage at the bus CANH, preventing conduction to the substrate.

[0052] Conversely, in this example, the lower drive stack 220LL includes an NMOS transistor 422 whose source is coupled to a ground circuit and whose gate receives a bias voltage NBIASD from the lower switch circuitry 320L. Similar to the case of the PMOS transistor 402, the NMOS transistor 422 is also configured as a low-voltage (e.g., 5V) transistor and operates in the dominant phase to control the voltage that appears at the bus CANL. In the recessive phase, the bias voltage NBIASD will be at a level (e.g., the ground circuit) that turns off the NMOS transistor 422.

[0053] The drain of the NMOS transistor 422 is coupled to the source (and body node) of a high-voltage NMOS transistor 426, and the gate of the high-voltage NMOS transistor is coupled to V CC power supply node. Similarly, similar to the high-voltage NMOS transistor 404, the NMOS transistor 424 is configured as a high-voltage device, e.g., configured as an LDMOS transistor. The drain of the NMOS transistor 424 is coupled to the source (and body node) of a high-voltage PMOS transistor 426. Compared to the upper drive stack 220HU, the gate (and body node) of the PMOS transistor 426 is coupled to the source at the drain of the NMOS transistor 426. The gate of the PMOS transistor 426 is floating otherwise. Thus, the PMOS transistor 426 is "diode-connected", and thus its electrical behavior is similar to that of a diffusion diode or other diode. The drain of the PMOS transistor 426 is coupled to the bus CANL. The PMOS transistor 426 is configured as a high-voltage device, e.g., configured as a DEPMOS transistor.

[0054] As in the upper drive stack 220HU, the conduction between the bus CANH and the common potential (e.g., ground circuit) is blocked for both positive and negative high voltages in the lower drive stack 220LL, thereby protecting the NMOS transistor 422. The diode-connected PMOS transistor 426 establishes a negative high voltage blocking diode 436, whose anode is at the bus CANL and whose cathode is at the drain of the NMOS transistor 424. This blocking diode 436 is reverse-biased when there is a positive high voltage at the bus CANL. The NMOS transistor 434 establishes a positive high voltage blocking diode 434, whose cathode is at the source of the diode-connected PMOS transistor 426, and whose anode is at the drain of the NMOS transistor 422. Thus, this blocking diode 434 is reverse-biased when there is a negative high voltage at the bus CANH. Similarly, as in the upper drive stack 220HU, in this embodiment, there is a substrate diode 435 at the p-n junction between the n-type drain and the p-type substrate Psub of the NMOS transistor 424. This substrate diode 435 is reverse-biased when there is a high positive voltage at the bus CANL, preventing conduction to the substrate, but is not forward-biased when there is a high negative voltage at the bus CANL due to the blocking action of the PMOS transistor 426.

[0055] In this example, the diode-connected configuration of the PMOS transistor 426 in the lower drive stack 220LL reduces the variation of the resistance of the drive stack with temperature in the H-bridge driver 200. In particular, since the PMOS transistor 426 is diode-connected, the on-resistance R presented by the diode-connected PMOS transistor 426 on is complementary to the absolute temperature (CTAT). This CTAT characteristic of the PMOS transistor 426 is used to compensate for the on-resistance R of the NMOS transistor 424 on that is proportional to the absolute temperature (PTAT), where the NMOS transistor is configured as a "switch" (e.g., configured to receive a gate voltage V CC ). In the upper drive stack 220HU, the drain-to-source voltage (V CC ) of the NMOS transistor 404 acting as a diode at its gate with V ds is CTAT, counteracting the PTAT characteristic of the on-resistance R of the PMOS transistor 406 on . In this example, the compensation provided by this CTAT characteristic of the diode-connected PMOS transistor 426 in the lower drive stack 220LL is thus used to limit the variation of the differential voltage V OD with temperature.

[0056] In the example, the lower copy stack 520 in the bias control loop 340 is configured to contain copies of the devices in the lower drive stack 220LL (and the devices in the lower drive stack 220HL with a similar configuration). Based on these copies, the bias control loop 340 generates and adjusts the bias reference voltage NBIAS_REF, thereby reducing the on-resistance R of the devices in the lower drive stacks 220HL and 220LL. on Variations in the voltages driven on the buses CANH and CANL as a function of PVT.

[0057] Figure 5A Illustrates an example configuration of the bias control loop 340. The bias control loop 340 includes a reference branch that includes a current source 502 and a resistor 504 serially coupled between a power supply node V CC and a ground circuit. In this example, the resistor 504 can be configured as a polysilicon resistor, or some other such configuration, to provide a low temperature coefficient. The resistance value of the resistor 504 can be selected to correspond to the load resistance at the bus CANL (e.g., approximately 250 Ω). The current source 502 is configured and controlled to provide a current (I = V CC / R) that follows the variation of the power supply voltage to minimize the variation of the operation of the lower copy stack 520 with respect to the variation of V CC . The operational amplifier ("op amp") 510, configured as a differential amplifier in this example, has a negative input coupled to the node between the current source 502 and the resistor 504. CC

[0058] The second branch of the bias control loop 340 includes a current source 512 connected in series with the lower copy stack 520 between a power supply node V CC and a ground circuit. The lower copy stack 520 includes copies of the transistors in the lower drive stack 220LL (and 220HL) in the form of PMOS transistor 526, NMOS transistor 524, and NMOS transistor 522, whose source / drain paths are serially coupled. More specifically, the drain of the PMOS transistor 526 is coupled to the current source 512 and the positive input of the op amp 510. The PMOS transistor 526 is diode-connected, and its gate is connected to its source (and body node) at the drain of the NMOS transistor 524. The gate of the NMOS transistor 524 is biased at V CC , and its source is coupled to the drain of the NMOS transistor 522. The source of the NMOS transistor 522 is at a common potential. The op amp 510 in the bias control loop 340 generates the bias reference voltage NBIAS_REF at its output, which is coupled to the gate of the NMOS transistor 522 and the input of the pre-driver 330L ( Figure 3 ).

[0059] The diode-connected PMOS transistor 526 in the lower copy stack 520 can be configured as a copy of the diode-connected PMOS transistor 426 in the lower drive stack 220LL, e.g., configured as a drain-extended PMOS transistor, to match the configuration of the PMOS transistor 426 described above. Similarly, the NMOS transistor 524 in the lower copy stack 520 can be configured as a copy of the NMOS transistor 424 in the lower drive stack 220LL, e.g., configured as the laterally-diffused NMOS transistor described above for the NMOS transistor 424. The NMOS transistor 522 can be configured as a low-voltage transistor, being a copy of the low-voltage NMOS transistor 422 in the lower drive stack 220LL, as described above. To save chip area and considering the high impedance present at the positive input of the op amp 510, at least the high-voltage copy transistors 524, 526 in the lower copy stack 520 can be significantly smaller in size than the corresponding transistors 424, 426 in the lower drive stack 220LL, e.g., about 1 / 10 the size of the latter.

[0060] In operation, the op amp 510 in the bias control loop 340 drives the bias reference voltage NBIAS_REF at the gate of the NMOS transistor 522 such that the voltage at its positive input at the drain of the PMOS transistor 526 matches the voltage at its negative input in the reference branch at the node between the current source 502 and the resistor 504. When the on-resistances R on of the high-voltage transistors 424 and 426 in the lower drive stacks 220LL and 220HL vary with PVT, the on-resistances R on of the transistors 524 and 526 in the lower copy stack 520 vary in a similar manner, thereby modulating the voltage at the positive input of the op amp 510. The op amp 510 responds by modulating the bias reference voltage NBIAS_REF at its output, thereby changing the gate bias of the transistor 522 to compensate for the R on variation in the transistors 524 and 526. For example, if the on-resistances R on of the transistors 524 and 526 increase, then the op amp 510 will increase the bias reference voltage NBIAS_REF to turn on the NMOS transistor 522 more difficultly, reducing its on-resistance R onto maintain the voltage at the positive input of op amp 510 at the same voltage as that generated by resistor 504 at the negative input of op amp 510. In the example, since transistors 522, 524, 526 are copies of the devices in the lower drive stack 220LL, the modulation of the bias reference voltage NBIAS_REF from op amp 510 also appears at the gates of NMOS transistors 422 in the lower drive stack 220LL during the dominant phase. The reduction of the R on of transistors 424, 426 in the lower drive stack 220LL (and lower drive stack 220HL) will have the opposite effect, causing opamp 510 in the bias control loop 340 to reduce the bias reference voltage NBIAS_REF, thereby reducing the gate bias at transistors 422 and 522.

[0061] Figure 5B shows the configuration of the VSYM control loop 345 in the example. As will be described below, the VSYM control loop 345 includes copies of the devices in both the upper drive stack 220HU and the lower drive stack 220HL (and thus includes copies of the devices in the upper drive stack 220LU and the lower drive stack 220LL having a similar configuration). The VSYM control loop 345 generates and adjusts the bias reference voltage PBIAS_REF to reduce the on-resistance R on of the devices in the upper drive stacks 220HU, 220LU as the PVT varies and the variation of the voltages driven on the buses CANH, CANL. Additionally, as will also be described below, the VSYM control loop 345 also includes copies of the devices in the lower drive stack 220HL (and stack 220LL), which are biased at the bias reference voltage NBIAS_REF generated by the bias control loop 340 to maintain driver symmetry across PVT.

[0062] The VSYM control loop 345 includes a reference branch that includes resistors 534 and 536 serially coupled between a power supply node V CC and a ground circuit. Resistors 534 and 536 can be configured as polysilicon resistors or made of such other materials to have a low temperature coefficient. The resistance value of each of resistors 534 and 536 can be selected to match each other and correspond to the load resistance at bus CANH (e.g., approximately 250 Ω each). In this example, opamp 535 configured as a differential amplifier has a negative input coupled to the node between resistors 534 and 536. In this example where the resistance values of resistors 534 and 536 are equal to each other, the voltage at this negative input will be substantially at the midpoint voltage between V CC and ground.

[0063] The second branch of the VSYM control loop 345 includes an upper replica stack 540 and a lower replica stack 550 coupled in series between a power supply node V CC and a ground circuit. The upper replica stack 540 includes a PMOS transistor 542 having its source at the power supply node V CC and its drain coupled to the source of an NMOS transistor 544. The PMOS transistor 542 can be configured as a low-voltage transistor and be a replica of the low-voltage PMOS transistor 402 in the upper drive stack 220HU. The drain of the PMOS transistor 542 is coupled to the source of an NMOS transistor 546, and the gate of the NMOS transistor is coupled to the power supply node V CC . The NMOS transistor 544 in the replica stack 540 of the VSYM control loop 345 can be configured as a replica of the NMOS transistor 404 in the upper drive stack 220HU, for example, configured as a laterally diffused NMOS transistor. The drain of the NMOS transistor 544 is coupled to the source (and body node) of a PMOS transistor 546, and the gate of the PMOS transistor is coupled to ground. The PMOS transistor 546 can be configured as a replica of the PMOS transistor 406 in the upper drive stack 220HU, for example, configured as a drain-extended PMOS transistor. The drain of the PMOS transistor 546 is coupled to node N1 at the positive input of the op amp 535 through a resistor 548. For example, the resistor 548 is configured as a polysilicon resistor to match the 10X resistance value (e.g., 50 Ω) of an external load resistor. The gate of the PMOS transistor 542 is coupled to the output of the opamp 535.

[0064] Similarly, as in the lower replica stack 520 of the bias control loop 340, the sizes of at least the high-voltage replica transistors 544, 546 in the upper replica stack 540 in the VSYM control loop 345 can be significantly smaller than the corresponding transistors 404, 406 in the upper drive stack 220HU, for example, about 1 / 10 of the latter's size.

[0065] The VSYM control loop 345 further includes a lower replica stack 550. In this example, the lower replica stack 550 includes a resistor 558 coupled in series with the source / drain paths of a PMOS transistor 556, an NMOS transistor 554, and an NMOS transistor 552 between node N1 and the ground circuit. For example, the resistor 558 is configured as a polysilicon resistor to match the 10X resistance value (e.g., 50 Ω) of an external load resistor. The transistors 552, 554, 556 in the lower replica stack 550 are replicas of the corresponding transistors 422, 424, 426 in the lower drive stack 220LL, and in this example, respectively match the configurations and sizes of the transistors 522, 524, 526 in the lower replica stack 520. AsFigure 5B As shown, the PMOS transistor 556 has its drain coupled to the resistor 558 and is diode-connected, with its gate connected to its source (and body node) at the drain of the NMOS transistor 524. The gate of the NMOS transistor 554 is biased at V CC and its source is coupled to the drain of the NMOS transistor 552. The source of the NMOS transistor 522 is at a common potential. The gate of the NMOS transistor 522 receives a bias reference voltage NBIAS_REF from the output of the bias control loop 340.

[0066] In operation, the op amp 535 in the VSYM control loop 345 drives a bias reference voltage PBIAS_REF at the gate of the PMOS transistor 542 such that the voltage at its positive input at node N1 matches the voltage at its negative input between the resistors 534, 536. In this example where the resistors 534 and 536 have the same resistance value, the op amp 535 controls the bias reference voltage PBIAS_REF such that the voltage at node N1 between the replica stacks 540 and 550 is at the midpoint between V CC and ground. Since the lower replica stack 550 contains replica transistors 552, 554, 556 corresponding to the transistors in the lower replica stack 520, where the gate of the replica NMOS transistor 552 receives the bias reference voltage NBIAS_REF, the on-resistance R on of the high-voltage devices in the lower drive stack 220LL is reflected at node N1 in the VSYM control loop 345. And when the on-resistances R on of the high-voltage transistors 404 and 406 in the upper drive stacks 220HU and 220LU vary with PVT, the on-resistances R on of the transistors 544 and 546 in the upper replica stack 540 of the VSYM control loop 345 vary in a similar manner, thereby modulating the voltage at node N1 such that the op amp 535 modulates the bias reference voltage PBIAS_REF. The gate bias at the replica transistor 542 is thus adjusted to compensate for the R on variations.

[0067] Since the reference branches of the resistors 534 and 536 set the midpoint at the negative input of the op amp 535 (e.g., V CC / 2) voltage, and since the NMOS transistor 552 in the lower copy stack 550 receives the bias reference voltage NBIAS_REF from the bias control loop 340, the VSYM control loop 345 controls the generation of the bias reference voltage PBIAS_REF around the midpoint voltage to achieve driver symmetry. In the context of a CAN XL network, this control of the bias reference voltages PBIAS_REF and NBIAS_REF enables the transmitter circuitry 300 to meet strict driver symmetry and V OD specification limits.

[0068] As an alternative to the arrangement described above with respect to Figure 5A and Figure 5B the arrangement of the VSYM control loop 345 and the bias control loop 340 can be reversed. In such an alternative arrangement, the bias control loop 340 would include an upper copy stack (e.g., in the form of a single copy stack arrangement similar to the Figure 5A lower copy stack 520 but with complementary devices) configured to include a copy device of the upper drive stack 220HU to generate the bias reference voltage PBIAS_REF. The VSYM control loop 345 would be constructed in a manner similar to Figure 5B as shown, but would include a copy PMOS transistor 542 that receives the bias reference voltage PBIAS_REF from the bias control loop 340 at its gate to generate the bias reference voltage NBIAS_REF from the op amp 535.

[0069] As described above with respect to Figure 3 the bias reference voltage PBIAS_REF is applied to the pre-driver 330U, which is configured to drive the corresponding bias voltage PBIAS applied to the upper switch circuitry 320U. Similarly, the bias reference voltage NBIAS_REF is applied to the pre-driver 330L, which is configured to drive the corresponding bias voltage NBIAS applied to the lower switch circuitry 320L. Figure 6A Shows a general form of the arrangement of the pre-drivers 330U, 330L and switches 320U, 320L and the H-bridge driver 200 in the example, the H-bridge driver including upper drive stacks 220HU, 220LU and lower drive stacks 220HL, 220LL.

[0070] As Figure 6A shown, the drive stacks 220HU, 220HL, 220LU and 220LL respectively include high voltage blocking transistors 602HU, 602HL, 602LU and 602LL, each of which includes the above with respect to Figure 3The described positive and negative high-voltage blocking transistors and diodes. Thus, each of the high-voltage blocking transistors 602HU and 602HL includes a PMOS transistor 404 and an NMOS transistor 406 in series with the PMOS transistor 402, as described above. Each of the high-voltage blocking transistors 602HL and 602LL includes a diode-connected PMOS transistor 426 and an NMOS transistor 424 in series with the NMOS transistor 422, as described above.

[0071] Figure 6A The upper pre-driver 330U shown receives a bias reference voltage PBIAS_REF from the VSYM control loop 345 at its positive input and couples its output to its negative input. In this voltage follower configuration, the upper pre-driver 330 is essentially a unity-gain amplifier and outputs a bias voltage PBIAS to the upper switch circuitry 320U based on the bias reference voltage PBIAS_REF. Similarly, the lower pre-driver 330L receives a bias reference voltage NBIAS_REF from the bias control loop 340 at its positive input and couples its output to its negative input in a voltage follower configuration. Thus, the lower pre-driver 330L essentially acts as a unity-gain amplifier and outputs a bias voltage NBIAS to the lower switch circuitry 320L based on the bias reference voltage NBIAS_REF.

[0072] In Figure 6A a general arrangement, the upper switch circuitry 320U includes a set of switches for selectively turning on and off the PMOS transistors 402 in the upper drive stacks 220HU and 220LU in response to the data states driven at the buses CANH, CANL. In the upper switch circuitry 320U, a switch 611 is coupled between the output of the pre-driver 330U and a node PBIASD at the gate of the PMOS transistor 402 of the upper drive stack 220HU, and a switch 612 is coupled between the power supply node V CC and the node PBIASD. The upper switch circuitry 320U also includes a switch 613 coupled between the power supply node V CC and a node PBIASR at the gate of the PMOS transistor 402 of the upper drive stack 220LU, and a switch 614 coupled between the output of the pre-driver 330U and the node PBIASR. The switches 611 and 613 are closed by a signal S in an active state, and the switches 612 and 614 are closed by a signal S' in an active state. In this embodiment, the signals S and S' are complementary to each other such that the switches 611 and 613 are open while the switches 612 and 614 are closed, and vice versa.

[0073] Similarly, the lower switch circuit system 320L includes a switch 615 coupled between a common potential (ground circuit) and a node NBIASR at the gate of the NMOS transistor 422 of the lower drive stack 220HL, and a switch 616 coupled between the output of the pre-driver 330L and the node NBIASR. The lower switch circuit system 320L further includes a switch 617 coupled between the output of the pre-driver 330L and a node NBIASD at the gate of the NMOS transistor 422 of the lower drive stack 220LL, and a switch 618 coupled between the ground circuit and the node PBIASD. The switches 615 and 617 are closed by the signal S in the active state, and the switches 616 and 618 are closed by the signal S' in the active state. In this embodiment, the signals S and S' are complementary to each other such that the switches 615 and 617 are open while the switches 616 and 618 are closed, and vice versa.

[0074] Figure 6B Illustrates the relationship between the data states "0" and "1" to be transmitted, for example, forwarded by the MCU 104 in the corresponding network node 102, and the S and S' signals applied to the upper switch 320U and the lower switch 320L. In this example, as Figure 6B shown, for the transmission of the data state "0", the signal S is driven to the active state (e.g., high logic level) and the signal S' is driven to the inactive state (e.g., low logic level). Conversely, for the transmission of the data state "1", the signal S is driven to the inactive state and the signal S' is driven to the active state. Although Figure 6B the data states "0" and "1" are shown as alternating cycle by cycle, the specific pattern of the data states "0" and "1" depends on the data transmitted from the transmitter circuit system 300 at any particular time.

[0075] Figure 6C Illustrates the operation of the upper switch circuit system 320U of the bias nodes PBIASD and PBIASR at the gates of the transistors 402 in the upper drive stacks 220HU, 220LU respectively. In this CAN XL example, as described above with respect to Figure 1B the dominant phase (e.g., bus CANH is at a higher voltage than bus CANL) corresponds to the transmission of a "0" data bit, and the recessive phase (e.g., bus CANL is at a higher voltage than bus CANH) corresponds to the transmission of a "1" data bit. In Figure 6C the example of, at time T0, in the CAN XL protocol, the data state "1" is transmitted in the recessive phase. In this phase (refer to Figure 6B) In this case, signal S is in an inactive state and signal S' is in an active state. When signal S' is in its active state, switch 612 is closed, thus closing switch 612 to couple node PBIASD to V CC , such that the transistor 402 in the upper drive stack 220HU is turned off, thereby turning off the high-side drive to bus CANH. Similarly, when signal S' is in the active state, switch 614 in the upper switch 302U is closed to couple node PBIASD to the bias voltage PBIAS, such that the PMOS transistor 402 in the upper drive stack 220LU is turned on, enabling the upper drive stack 220LU to actively drive bus CANL. During this recessive phase, switch 616 in the lower switch 230L will be closed, thereby biasing node NBIASR to the bias voltage NBIAS and turning on the NMOS transistor 422 in the lower drive stack 220HL to drive bus CANH; the lower drive stack 220LL will be turned off by closing switch 618 during this recessive phase, enabling bus CANL to be driven by the upper drive stack 220LU, as mentioned above.

[0076] When transitioning from the recessive phase to the dominant phase, as Figure 6C shown, signal S transitions to the active state (e.g., high logic level), closing switches 611 and 613 in the upper switch circuit system 320U, while signal S' transitions to the inactive state (e.g., low logic level), opening switches 612 and 614. For example, the closing of switch 611 begins to charge the gate of transistor 402 in the upper drive stack 220HU to the bias voltage PBIAS, as Figure 6C shown at time T1 in. Transistor 402 turns on when node PBIASD is charged to voltage PBIAS, enabling the upper drive stack 220HU to drive bus CANH. Conversely, the closing of switch 613 in the upper switch circuit system 320U begins to discharge the gate of the PMOS transistor 402 in the upper drive stack 220LU to the power supply node V CC , also at time T1, thereby turning off the PMOS transistor 402. Therefore, switches 611 and 614 in the upper switch circuit system 320U can be referred to as "charging switches", and switches 612 and 613 can be referred to as "discharging switches".

[0077] Similarly, for the transition from the dominant phase to the recessive phase, the charging switches 614 and the discharging switch 612 will be closed (signal S' turns to the active state). During the transition including Figure 6C time T2 in, the gate of the PMOS transistor 402 in the upper drive stack 220LU will be charged to the bias voltage PBIAS, while the gate of the PMOS transistor 402 will be discharged to the power supply node V CCAccordingly, the upper drive stack 220LU will drive the bus CANL in the recessive phase while the upper drive stack 220HU will be turned off (such that the lower drive stack 220HL drives the bus CANH).

[0078] The lower switch circuitry 320L will operate in the dominant and recessive phases in the same manner as described above for the upper switch circuitry 320U, but in a complementary manner such that the lower drive stack 220HL is able to drive the bus CANH when the upper drive stack 220HU is deactivated (by turning off its transistors 402), and the lower drive stack 220LL is able to drive the bus CANL when the upper drive stack 220LU is deactivated.

[0079] In the example, each of the pre-drivers 330U, 330L (referred to individually or collectively as pre-driver 330) is configured as a high-speed amplifier with a "class AB" output stage. Figure 7 Showing in the example Figure 6A the construction of one embodiment of the pre-driver 330U in the architecture of; the pre-driver 330L can be constructed in a similar manner. Although Figure 7 a transistor-level diagram is included, the following description will describe the pre-driver 330U with reference to the various sub-circuits in which those transistors are arranged. Figure 7 The particular embodiment shown is only an example, and the pre-driver 330 can be implemented in other circuit arrangements (including different transistor-level circuits and sub-circuits). The nominal currents conducted by the particular transistors in the pre-driver 330U are shown as an example in Figure 7 These current levels can be different as required in different embodiments and applications.

[0080] In Figure 7 the example of, the pre-driver 330U includes a differential input stage 702, constructed from complementary NMOS differential stage 703N and PMOS differential stage 703P. For the case of the pre-driver 330U, the differential stages 703N and 703P receive a bias reference voltage PBIAS_REF at one input (the positive input in this example), and a bias voltage PBIAS from the output of the pre-driver 330U itself at the other input (the negative input). The NMOS differential stage 703N and PMOS differential stage 703P receive bias voltages NBIAS2 and PBIAS2 respectively; Figure 7 these and other bias voltages shown in correspond to various bias voltages that can be generated by reference voltage circuitry (not shown) elsewhere in the transceiver 110, at levels suitable for the particular embodiment. In Figure 7In the example of, this configuration of the differential input stage 702 provides a rail-to-rail input voltage range to the pre-driver 330 to accommodate the on-resistance R of the high-voltage device in the driver stage 220 on Large shifts in the bias reference voltages PBIAS and NBIAS (as appropriate) from the VSYM control loop 345 and the bias control loop 340, respectively, across PVT variations.

[0081] In this embodiment, the pre-driver 330U further includes a level shifter stage 704 coupled to the differential input stage 702. The level shifter stage 704 receives differential currents from the NMOS differential stage 703N and the PMOS differential stage 703P based on the differential input voltage applied to the differential input stage 702, and in response, generates output gate voltages PMOS_G and NMOS_G that are applied to the gates of the output driver transistors 710 and 712, respectively.

[0082] The pull-up output transistor 710 is a PMOS transistor whose source is at the power supply node V CC and whose drain is coupled to the drain of the pull-down output transistor 712 at the output of the pre-driver 330U. The pull-down output transistor 712 is an NMOS transistor whose source is at a common potential (e.g., a ground circuit). Thus, the output transistors 710 and 712 are arranged as a push-pull output stage of the pre-driver 330U and drive the bias voltage PBIAS at their common drain node in response to the gate voltages PMOS_G and NMOS_G output by the level shifter stage 704, respectively. The bias voltage PBIAS at the output of the pre-driver 330U is fed back to the negative input of the pre-driver 330U at the input differential stage 702, as mentioned above. This direct feedback causes the pre-driver 330U to provide unity gain, such that the bias voltage PBIAS output by the pre-driver 330U substantially matches the bias reference voltage PBIAS_REF generated by the VSYM control loop 345.

[0083] A Miller compensation network 706, including a parallel capacitor and a series resistor, is coupled between the output (PMOS_G and NMOS_G) of the level shifter stage 704 and the output (PBIAS) of the pre-driver 330U to compensate for the Miller effect on the amplifier performance.

[0084] In this embodiment, output transistors 710 and 712 are configured to support a high drive current (e.g., having a relatively large channel width / length ratio) sufficient to drive H-bridge driver 200 via upper switch circuitry 320U at a desired high speed (e.g., data rate ≥ 15 Mbps) in two phases. Additionally, in this configuration, the output stages of output transistors 710 and 712 in pre-driver 330U function as "class AB" output stages, which in the present application have a low output resistance on both the high side and the low side to address coupling issues with a low-voltage gate network during direct power injection (DPI).

[0085] As also mentioned above, pre-driver 330L can be configured to be substantially the same as Figure 7 pre-driver 330U to generate bias voltage NBIAS based on bias reference voltage NBIAS_REF generated by bias control loop 340. The close matching between pre-drivers 330L and 330U reduces the likelihood of upper and lower signal path mismatches, thereby promoting symmetry of the signals output by transmitter circuitry 300.

[0086] In an example, each of upper switch 320U and lower switch 320L is configured such that the charging and discharging currents applied to the gates of the operable transistors in drive stacks 220HU, 220HL, 220LU, 220LL are symmetric. More specifically, upper switch circuitry 320U is arranged to charge the gates of PMOS transistors 402 in upper drive stacks 220HU, 220LU with bias voltage PBIAS output from pre-driver 330U and to discharge the gates of those PMOS transistors 402 with a current based on the gate voltage NMOS_G applied to output driver transistor 712 in pre-driver 330U. Additionally, upper switch circuitry 320U is configured to include temperature variation compensation when controlling the discharge current. Lower switch circuitry 320L is arranged in a similar manner to charge NMOS transistors 422 in lower drive stacks 220HL, 220LL with bias voltage NBIAS output from pre-driver 330L and to discharge the gates of those NMOS transistors 422 with a current based on the gate voltage PMOS_G applied to output driver transistor 710 in pre-driver 330L, the current having been temperature compensated.

[0087] Figure 8A Illustrates the construction of upper switch circuitry 320U in the example. As Figure 8A shown, pre-driver 330U receives bias reference voltage PBIAS_REF at its positive input and generates bias voltage PBIAS at its output, which is applied to switch 611. Switch 611 responds to the data signal to be transmitted through transmitter circuitry 300 (e.g., which can beFigure 1A is provided by the MCU 104) and is opened and closed, and when closed, couples the bias voltage PBIAS at the node PBIAS_D to the gate of the PMOS transistor 402 in the upper drive stack 220HU. In Figure 8A The switch 612, which is included as part of the discharge circuit 800 in the example of, is also coupled to the node PBIAS_D at the gate of the transistor 402 in the upper drive stack 220HU. Although for clarity in Figure 8A not shown, the switches 613 and 614 are coupled in parallel with the switches 611 and 612, respectively, as shown in FIG. 6, so as to charge and discharge the gate of the PMOS transistor 402 in the upper drive stack 220LU in a similar manner. In this configuration, the parallel switch 614 may also be included as part of the discharge circuit 800.

[0088] In this embodiment, the discharge circuit 800 includes two current mirrors for shunting the discharge current from the gate of the transistor 402 through the switch 612 to V CC In the first of these current mirrors, the source of the NMOS transistor 802 is at the ground circuit, and its gate receives the gate voltage NMOS_G from the pre-driver 330U. The drain of the transistor 802 is coupled to the gate and drain of the PMOS transistor 804 and to the gate of the PMOS transistor 806. The sources of the PMOS transistors 804 and 806 are coupled to the power supply node V CC , and the drain of the transistor 806 is coupled to the switch 612. In this example, the PMOS transistor 806 is sized larger (e.g., has a larger W / L ratio) than the transistor 804, for example, six times larger.

[0089] The second current mirror in the discharge circuit 800 includes a current source 812, which is coupled between the ground circuit and the gate and drain of the PMOS transistor 814 and the gate of the PMOS transistor 816. The current source 812 is configured to have characteristics proportional to the absolute temperature (PTAT). The drain of the PMOS transistor 814 is coupled to the switch 612, and its source is at the power supply node V CC In this example, the transistor 814 is configured to have the same size as the transistor 804, and the transistor 816 is larger than the transistor 814 (e.g., has a larger W / L), for example, four times larger.

[0090] In operation, the closing of the switch 612 is used to couple the PMOS transistor 402 to V CCA power supply (coupled to the source of transistor 402) discharges the gate-to-source capacitance of the PMOS transistor. The discharge current through switch 612 is shunted by transistors 806 and 816 to currents set by NMOS transistors 802 and current source 812, respectively, and in the relative sizes of PMOS transistors 804, 806, 814, 816. In the example described above with respect to Figure 8A where transistors 804 and 814 are of the same size, and transistor 806 is 6X the size of transistor 804 and transistor 816 is 4X the size of transistor 814, approximately 60% of the discharge current through switch 612 will conduct through transistor 806 and 40% will conduct through transistor 816.

[0091] This configuration of the upper switch circuit system 320U provides important advantages in terms of temperature stability and symmetry of the transmitter circuit system 300. In this example, the current that charges (depending on the data state) the gate-to-source capacitance of PMOS transistor 402 in the upper drive stack 220HU or 220LU is mainly driven by NMOS output drive transistor 712 in pre-driver 330U. The same gate voltage NMOS_G applied to transistor 712 is applied to the gate of NMOS transistor 802 of the upper switch circuit system 320L, such that the discharge current of the gate-to-source capacitance of PMOS transistor 402 matches the charging current from pre-driver 330U. Additionally, in the Figure 8A example, PTAT current source 812 is also a factor in controlling the discharge current through switch 612, reducing the temperature-related variation of the discharge current. Further, it has been observed that the presence of the second current mirror based on PTAT current source 812 also compensates for the effect of any drain-to-source voltage mismatch between the output stage of pre-driver 330U and discharge circuit 800 on the discharge current.

[0092] The lower switch circuit system 320L is constructed in a similar manner but is complementary to the upper switch circuit system 320U in that it is used to charge and discharge the gates of NMOS transistors 422 (instead of PMOS transistor 402) in the lower drive stacks 220HL, 220LL. Figure 8B An example of the construction of the lower switch circuit system 320L in this complementary arrangement is shown. Pre-driver 330U receives a bias reference voltage NBIAS_REF at its positive input and generates a bias voltage NBIAS at its output to switch 617, which responds to data to be transmitted through transmitter circuit system 300 (e.g., by Figure 1Ais turned on and off in response to a data signal provided by the MCU 104. When closed, switch 617 couples the bias voltage NBIAS at node NBIAS_D to the gate of NMOS transistor 422 in the lower drive stack 220LL, thereby charging the gate-to-source capacitance of transistor 422. The discharge circuit 850 includes a switch 618 coupled to node NBIAS_D and thus to the gate of NMOS transistor 422 in the upper drive stack 220LL. Similarly, switches 616 and 615 (not shown in Figure 8B are coupled in parallel with switches 617 and 618, respectively, as shown in FIG. 6, to charge and discharge the gate of NMOS transistor 422 in the lower drive stack 220LL in a similar manner. In this configuration, parallel switch 616 may also be included as part of the discharge circuit 850.

[0093] The discharge circuit 850 shown in FIG. 9B includes two current mirrors for splitting the discharge current from the gate of transistor 422 through switch 618 to ground. In one current mirror, the source of PMOS transistor 852 is at the power supply node V CC and its gate receives the gate voltage PMOS_G from the pre-driver 330L. The drain of transistor 852 is coupled to the gate and drain of NMOS transistor 854 and to the gate of PMOS transistor 856. The sources of NMOS transistors 854 and 856 are coupled to ground, and the drain of transistor 856 is coupled to switch 618. In this example, NMOS transistor 806 is sized larger than transistor 854 (e.g., having a larger W / L ratio), e.g., six times larger.

[0094] The second current mirror in the discharge circuit 850 includes a current source 862 coupled between V CC and the gate and drain of NMOS transistor 864 and the gate of NMOS transistor 866. The current source 862 is configured to have characteristics proportional to absolute temperature (PTAT). The drain of NMOS transistor 864 is coupled to switch 618 and its source is at ground, and in this example, NMOS transistor 864 is configured to be the same size as transistor 854. NMOS transistor 866 is configured to be larger than transistor 864 (e.g., having a larger W / L), e.g., four times larger.

[0095] In the operation of the discharge circuit 850, the closing of switch 618 discharges the gate-to-source capacitance of the NMOS transistor by coupling the NMOS transistor 422 to the ground circuit. The discharge current through switch 618 is shunted by transistors 856 and 866 to currents set by PMOS transistor 852 and current source 862, respectively, and in the relative sizes of PMOS transistors 854, 856, 864, 866. In this example, where transistors 854 and 864 are the same size, and transistor 856 is 6X the size of transistor 854 and transistor 866 is 4X the size of transistor 864, approximately 60% of the discharge current through switch 618 will conduct through transistor 856 and 40% will conduct through transistor 866.

[0096] From the perspective of temperature stability and symmetry, this configuration of the lower switch circuit system 320L provides similar advantages as described above in connection with the upper switch circuit system 320U. As described above, the charging current provided by pre-driver 330L matches the discharge current through switch 618, which is biased based on the gate bias voltage PMOS_G of PMOS transistor 852 from pre-driver 330L. Additionally, the PTAT characteristic of current source 812 reduces the temperature-related variation of this discharge current and compensates for the effect of the drain-to-source voltage mismatch between the output stage of pre-driver 330L and the discharge circuit 850.

[0097] Various features of the transmitter circuit system according to the examples described above can achieve many benefits. By controlling the bias voltage applied to the drive stack based on a copy of the drive stack, the on-resistance R on of the drive stack high-voltage blocking device can be compensated, thus avoiding the need for a larger driver blocking transistor and therefore reducing the capacitive load on the bus. In the example described above, this bias voltage control can achieve good stability and tight driver symmetry across PVT, enabling the transmitter to meet strict specification limits, such as those of the CAN XL standard.

[0098] As used herein, the terms "terminal", "node", "interconnect", and "pin" may be used interchangeably. Unless specifically stated to the contrary, these terms generally refer to the interconnect or its ends between device elements, circuit elements, integrated circuits, devices, or other electronic or semiconductor elements.

[0099] Unless otherwise specified, "about", "substantially", or "essentially" before a value means + / - 10% of the stated value. The examples described may be modified, and other examples are possible within the scope of the claims.

[0100] A device “configured to” perform a task or function can be configured (e.g., programmed and / or hardwired) by a manufacturer at the time of manufacture to perform the function, and / or can be configured (or reconfigured) by a user after manufacture to perform the function and / or other additional or alternative functions. The configuration can be performed by firmware and / or software programming of the device, by construction and / or arrangement of hardware components and interconnection of the device, or by a combination of these operations.

[0101] A circuit or device described herein as including certain components can actually be adapted to be coupled to those components to form the described circuitry or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage source and / or current source) can actually include only semiconductor elements within a single physical device (e.g., semiconductor die and / or integrated circuit (IC) package), and can be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure at the time of manufacture or after manufacture, e.g., by an end user and / or a third party. While in some examples certain elements are included within an integrated circuit and other elements are external to the integrated circuit, in other examples additional or fewer features can be incorporated into the integrated circuit. Additionally, some or all of the features shown as external to the integrated circuit can be included within the integrated circuit, and / or some of the features shown as internal to the integrated circuit can be incorporated external to the integrated circuit. As used herein, the term “integrated circuit” refers to one or more circuits that: (i) are incorporated in / on a semiconductor substrate; (ii) are incorporated in a single semiconductor package; (iii) are incorporated into the same module; and / or (iv) are incorporated in / on the same printed circuit board.

[0102] The circuits described herein can be reconfigured to include replacement components to provide a function that is at least partially similar to the function available prior to the component replacement. Unless otherwise specified, a component shown as a resistor generally represents any one or more elements coupled in series and / or parallel to provide the amount of impedance represented by the shown resistor. For example, a resistor or capacitor shown and described herein as a single component can be, respectively, multiple resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component can be, respectively, multiple resistors or capacitors coupled in series between the same two nodes as the single resistor or capacitor.

[0103] The use of the phrase “ground” in the foregoing description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable to or suitable for the teachings of this specification.

[0104] Within the scope of the claims, modifications to the described embodiments are possible, and other embodiments are possible.

Claims

1. A transmitter circuit system for differential signaling, comprising: first and second terminals adapted to be coupled to first and second lines of a network bus; an upper drive stack comprising: an upper bias transistor having a source / drain path and a gate, the source / drain path being coupled to a supply node; at least one upper blocking transistor serially coupled to the source / drain path of the upper bias transistor; a lower drive stack comprising: a lower bias transistor having a source / drain path and a gate; at least one lower blocking transistor serially coupled to the source / drain path of the lower bias transistor and coupled to a common node; a first control loop comprising: a first replica stack containing replicas of the bias transistor and at least one blocking transistor in a first one of the upper and lower drive stacks, the replicas being serially coupled; a first reference branch coupled between the supply node and the common node; and a first differential amplifier having a first input coupled to the first replica stack, a second input coupled to the first reference branch, and an output coupled to the gate of the replica bias transistor in the first replica stack; a second control loop comprising: a second replica stack containing replicas of the bias transistor and at least one blocking transistor in a second one of the upper and lower drive stacks, the replicas being serially coupled; a third replica stack containing replicas of the bias transistor and at least one blocking transistor in the first one of the upper and lower drive stacks, the third replica stack being coupled to the second replica stack at an output node and in series with the second replica stack, the replica bias transistor in the third replica stack having a gate coupled to the output of the first differential amplifier; a second reference branch coupled between the supply node and the common node; and a second differential amplifier having a first input coupled to the output node, a second input coupled to the output node, and an output coupled to the gate of the replica bias transistor in the second replica stack; a first switch circuit system configured to couple the output of the first differential amplifier to the gate of the bias transistor in the first one of the upper and lower drive stacks in response to a data signal; and a second switch circuit system configured to couple the output of the second differential amplifier to the gate of the bias transistor in the second one of the upper and lower drive stacks in response to the data signal.

2. The transmitter circuit system according to claim 1, wherein the source / drain path of the upper bias transistor is coupled to the supply node; wherein the at least one upper blocking transistor comprises: an upper positive voltage blocking transistor of a first conductivity type; and an upper negative voltage blocking transistor of a second conductivity type serially connected to the upper positive blocking transistor; wherein the source / drain path of the lower bias transistor is coupled to the common node; And wherein said at least one lower blocking transistor comprises: A lower positive voltage blocking transistor of said first conduction type; and A lower negative voltage blocking transistor of said second conduction type, which is connected in series with said lower positive blocking transistor.

3. The transmitter circuit system according to claim 2, wherein said lower positive blocking transistor comprises a metal oxide semiconductor (MOS) transistor having a drain coupled to said second terminal and a source and a gate both coupled to said source / drain path of said lower negative voltage blocking transistor; And wherein said first conduction type is p-channel and said second conduction type is n-channel.

4. The transmitter circuit system according to claim 3, wherein each of said blocking transistors comprises a high voltage MOS transistor.

5. The transmitter circuit system according to claim 4, wherein each of said replica bias transistors comprises a MOS transistor smaller in size than its corresponding bias transistor, and each of said replica blocking transistors comprises a MOS transistor smaller in size than its corresponding blocking transistor.

6. The transmitter circuit system according to claim 1, wherein each of said first and third replica stacks contains replicas of said lower bias transistors of said lower drive stack and at least one lower blocking transistor; And wherein said second replica stack contains replicas of said upper bias transistors of said upper drive stack and at least one upper blocking transistor.

7. The transmitter circuit system according to claim 6, wherein said first switch circuit system Comprises: A first upper charging switch coupled between the output of said second differential amplifier and the gate of said upper bias transistor; And A first upper discharging switch coupled between said supply node and the gate of said upper bias transistor; And wherein said second switch circuit system comprises: A first lower charging switch coupled between the output of said first differential amplifier and the gate of said lower bias transistor; and A first lower discharging switch coupled between said supply node and the gate of said lower bias transistor; Wherein said first upper and first lower charging and discharging switches are coupled to a data circuit system to open and close in response to a transmitted data signal.

8. The transmitter circuit system according to claim 7, further Comprises: An upper output stage amplifier having an input coupled to the output of said second differential amplifier and an output coupled to the output of said first upper charging switch; And A lower output stage amplifier having an input coupled to the output of said lower differential amplifier and an output coupled to the output of said first lower charging switch.

9. The transmitter circuit system according to claim 8, wherein said upper output stage amplifier Comprises: A first pull-up transistor having a source / drain path coupled between said supply node and the output of said upper output stage amplifier and having a gate; A first pull-down transistor having a source / drain path coupled between the common node and the output of the upper output stage amplifier and having a gate; A first amplifier stage having an input coupled to the output of the second differential amplifier and configured to bias the gates of the first pull-up and pull-down transistors; And wherein the first switching circuitry includes: A discharge circuit coupled between the supply node and the first upper discharge switch and configured to control a discharge current to the gate of the first upper bias transistor in response to a bias applied by the first amplifier stage to the first pull-down transistor of the upper output stage amplifier.

10. The transmitter circuitry of claim 1, wherein the upper drive stack is a first upper drive stack and the lower drive stack is a first lower drive stack; The circuitry further includes: A second upper drive stack including: An upper bias transistor having a source / drain path and a gate, the source / drain path coupled to the supply node; At least one upper blocking transistor coupled in series with the source / drain path of the upper bias transistor; and A second lower drive stack including: A lower bias transistor having a source / drain path and a gate; At least one lower blocking transistor coupled in series with the source / drain path of the lower bias transistor; Wherein the first switching circuitry is configured to couple the output of the first differential amplifier to the gates of the bias transistors of the first upper and second lower drive stacks in response to the data signal; And wherein the second switching circuitry is configured to couple the output of the second differential amplifier to the gates of the bias transistors of the second upper and first lower drive stacks in response to the data signal.

11. The transmitter circuitry of claim 1, wherein each of the first and third replica stacks includes a replica of the upper bias transistor of the upper drive stack and at least one upper blocking transistor; And wherein the second replica stack includes a replica of the lower bias transistor of the lower drive stack and at least one lower blocking transistor.

12. A differential signaling transmitter circuitry comprising: A first drive stack including a first bias transistor having a source / drain path coupled to a first terminal in series with the source / drain path of at least one first blocking transistor in the first drive stack; A second drive stack including a second bias transistor having a source / drain path coupled to a second terminal in series with the source / drain path of at least one first blocking transistor in the second drive stack; A first replica circuitry adapted to generate a first bias reference voltage by controlling a gate voltage of a replica of the first bias transistor in a first replica stack, the first replica stack including a replica of the first bias transistor and a replica of the at least one first blocking transistor in the first drive stack; and A second replica circuit system adapted to generate a second bias reference voltage by controlling a gate voltage of a replica of the second bias transistor in a second replica stack, the second replica stack including the replica of the second bias transistor and replicas of the at least one second blocking transistor in the second drive stack, the second replica stack being coupled in series with a third replica stack including replicas of the first bias transistor and the at least one first blocking transistor in the first drive stack, the gate of the replica of the first bias transistor in the third replica stack receiving the gate voltage controlled by the first replica circuit system; A first switch circuit system adapted to couple, in response to a data signal, a first gate voltage corresponding to the first bias reference voltage to the gate of the first bias transistor in the first drive stack; and A second switch circuit system adapted to couple, in response to the data signal, a second gate voltage corresponding to the second bias reference voltage to the gate of the second bias transistor in the second drive stack.

13. The transmitter circuit system of claim 12, wherein the first and second switch circuit systems are adapted to couple the first and second gate voltages to the gates of the first and second bias transistors, respectively, in response to the data signal being at a first level; wherein the first switch circuit system is adapted to couple the first gate voltage to the gate of a third bias transistor in a third drive stack in response to the data signal being at a second level, the third bias transistor having a source / drain path coupled in series between the first terminal and the source / drain path of at least one third blocking transistor in the third drive stack; and wherein the second switch circuit system is adapted to couple the second gate voltage to the gate of a fourth bias transistor in a fourth drive stack in response to the data signal being at the second level, the fourth bias transistor having a source / drain path coupled in series between the second terminal and the source / drain path of at least one fourth blocking transistor in the fourth drive stack.

14. The transmitter circuit system of claim 13, wherein each of the first and third drive stacks is coupled between the first terminal and a power supply node; and wherein each of the second and fourth drive stacks is coupled between the second terminal and a common potential node.

15. The transmitter circuit system of claim 12, wherein the at least one first blocking transistor includes: A first positive blocking transistor formed of a p-channel metal oxide semiconductor (MOS) transistor and having a drain coupled to the first terminal and a source and a gate; A first negative blocking transistor formed of an n-channel MOS transistor and having a drain coupled to the source of the first positive blocking transistor and a source coupled to the source / drain path of the first bias transistor; and wherein the at least one second blocking transistor includes: A second negative-blocking transistor formed of a p-channel MOS transistor and having a drain coupled to the second terminal and a source and a gate coupled together; A second positive-blocking transistor formed of an n-channel MOS transistor and having a drain coupled to the source and the gate of the first negative-blocking transistor and a source coupled to the source / drain path of the second biasing transistor.

16. The transmitter circuit system according to claim 12, wherein the first and second switch circuit systems are adapted to couple the first and second gate voltages to the gates of the first and second biasing transistors respectively in response to the data signal being at a first level; The transmitter circuit system further comprises: A first pre-driver including a first push-pull output stage, the first pre-driver being adapted to output the first gate voltage in response to the first biasing reference voltage; A second pre-driver including a second push-pull output stage, the second pre-driver being adapted to output the second gate voltage in response to the second biasing reference voltage; wherein the first switch circuit system is further adapted to discharge the gate of the first biasing transistor in response to the data signal being at a second level, using a discharge current corresponding to a pull-down current conducted in the first push-pull output stage; and wherein the second switch circuit system is further adapted to discharge the gate of the second biasing transistor in response to the data signal being at a second level, using a discharge current corresponding to a pull-down current conducted in the second push-pull output stage.

17. A network node, comprising: A microcontroller unit (MCU); First and second terminals adapted to be coupled to first and second lines of a network bus; A receiver circuit system coupled to the first and second terminals and configured to receive signals on the network bus for forwarding to the MCU; and A transmitter circuit system coupled to the first and second terminals and configured to transmit signals onto the network bus in response to data signals from the MCU, the transmitter circuit system comprising: An upper drive stack including: An upper biasing transistor having a source / drain path and a gate, the source / drain path being coupled to a supply node; At least one upper blocking transistor coupled in series with the source / drain path of the upper biasing transistor; A lower drive stack including: A lower biasing transistor having a source / drain path and a gate; At least one lower blocking transistor coupled in series with the source / drain path of the lower biasing transistor and coupled to a common node; A first control loop including: A first replica stack including replicas of the biasing transistor and at least one blocking transistor in the first of the upper and lower drive stacks, the replicas being coupled in series; A first reference branch coupled between the supply node and the common node; and A first differential amplifier having a first input coupled to the first replica stack, a second input coupled to the The second input of the first reference branch, and an output coupled to the gate of the replica bias transistor in the first replica stack; A second control loop, comprising: A second replica stack, which contains replicas of the bias transistors and at least one blocking transistor in the second of the upper and lower drive stacks, the replicas being coupled in series between a bias supply node and the common node; A third replica stack, which contains replicas of the bias transistors and at least one blocking transistor in the first of the upper and lower drive stacks, the third replica stack being coupled to the second replica stack at an output node and being in series with the second replica stack between the supply node and the common node, the gate of the replica bias transistor in the third replica stack being coupled to the output of the first differential amplifier; A second reference branch, which is coupled between the supply node and the common node; and A second differential amplifier, which has a first input coupled to the output node, a second input coupled to the output node, and an output coupled to the gate of the replica bias transistor in the second replica stack; A first switching circuitry, configured to couple the output of the first differential amplifier to the gate of the bias transistor in the first of the upper and lower drive stacks in response to a data signal; and A second switching circuitry, configured to couple the output of the second differential amplifier to the gate of the bias transistor in the second of the upper and lower drive stacks in response to the data signal.

18. The network node according to claim 17, wherein the source / drain path of the upper bias transistor is coupled to the supply node; wherein the at least one upper blocking transistor comprises: An upper positive high-voltage blocking metal-oxide semiconductor (MOS) transistor of a first conduction type; and An upper negative high-voltage blocking MOS transistor of a second conduction type, which is connected in series with the upper positive blocking transistor between the first terminal and the source / drain path of the upper bias transistor; wherein the source / drain path of the lower bias transistor is coupled to the common node; and wherein the at least one lower blocking transistor comprises: The lower positive high-voltage blocking MOS transistor of the first conduction type; and The lower negative high-voltage blocking MOS transistor of the second conduction type, which is connected in series with the lower positive blocking transistor between the second terminal and the source / drain path of the lower bias transistor.

19. The network node according to claim 18, wherein the lower positive high-voltage blocking MOS transistor has a drain coupled to the second terminal and a source and a gate both coupled to the source / drain path of the lower negative high-voltage blocking MOS transistor; and wherein the first conduction type is p-channel and the second conduction type is n-channel.

20. The network node according to claim 17, wherein each of the replica biasing transistors includes a MOS transistor having a size smaller than that of its corresponding biasing transistor, and each of the replica blocking transistors includes a MOS transistor having a size smaller than that of its corresponding blocking transistor.

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