Readout circuit for image sensing, readout system and solid-state imaging device

Abstract

The invention discloses a readout circuit and a readout system for image sensing and solid-state imaging equipment, and relates to the technical field of image sensing readout, and the readout circuit comprises a pixel array unit which is used for photoelectric signal conversion; a current mirror circuit unit; wherein the current mirror circuit unit comprises a cascode current mirror or two N-channel field effect transistors; a negative impedance conversion unit; and a charging and discharging acceleration unit. According to the invention, the negative impedance conversion unit and the charging and discharging acceleration unit are utilized, and the negative impedance generated by the negative impedance conversion unit is counteracted with the parasitic impedance influencing the VSL establishment speed, so that the small signal establishment speed is accelerated; the charging and discharging acceleration unit is used for selectively providing charging and discharging current in the VSL descending establishment process or the VSL ascending establishment process, so that the large signal establishment speed is accelerated. In this way, corresponding response cooperation can be carried out for the VSL descending establishment process or the VSL ascending establishment process.

Description

Technical Field

[0001] The present invention relates to the field of image sensor readout technology, and in particular to a readout circuit, a readout system and a solid-state imaging device for image sensing. Background Art

[0002] The ADC (A / D Converter) in the existing CMOS image sensor is composed of a load current source array, a comparator array and a counter array. Among them, the load current source array is responsible for providing a constant current for the source follower of the pixel array; during the signal readout process of the pixel array, the charge in the PD (Photon Diode) needs to be transferred to the FD (Floating Diffusion) to reduce the FD voltage; further, the pixel array output signal VSL (Vertical Signal Line) is reduced through the pixel SF (Source Follower).

[0003] In the above readout process, since the VSL drop process is affected by the parasitic resistance and capacitance of the metal wiring and the equivalent output impedance of SF, the VSL drop process will be slowed down, so that the entire image sensor needs to spend time waiting for VSL to completely drop to a stable level during the readout process. The time consumed in this process is called the VSL settling time.

[0004] In the current image sensor structure, if the VSL settling time is to be accelerated, the bias current of the load current source is often increased: on the one hand, the transconductance of the SF of the pixel array is increased to reduce its equivalent output impedance; on the other hand, during the large signal establishment period, increasing the bias current of the load current source can speed up the large signal establishment speed.

[0005] However, increasing the bias current of the load current source can usually only accelerate the process of the pixel array output signal VSL (Vertical Signal Line) falling and building up, and may not respond when the pixel array output signal VSL builds up from a low level. Summary of the invention

[0006] The purpose of the present invention is to solve the defect in the prior art that the pixel array output signal VSL cannot respond when it is built up from a low level, and to propose a readout circuit, a readout system and a solid-state imaging device for image sensing.

[0007] In order to achieve the above object, the present invention adopts the following technical solutions:

[0008] A first aspect of the present invention provides an image sensing readout circuit, comprising:

[0009] A pixel array unit, wherein the pixel array unit is used for photoelectric signal conversion;

[0010] A current mirror circuit unit, the current mirror circuit unit is electrically connected to the pixel array unit, and the current mirror circuit unit is used to provide a bias current;

[0011] Wherein, the current mirror circuit unit comprises: a common-source common-gate current mirror or two N-channel field effect transistors;

[0012] A negative impedance conversion unit, the negative impedance conversion unit is electrically connected to the current mirror circuit unit, and the negative impedance conversion unit is used to generate negative impedance to offset the parasitic impedance of VSL itself;

[0013] A charge and discharge acceleration unit is used to provide charge and discharge current during the VSL drop establishment process or the VSL rise establishment process.

[0014] In some feasible solutions, the charge and discharge acceleration unit includes:

[0015] A rising voltage-current conversion circuit, one end of which is connected to a drain power supply voltage, and the rising voltage-current conversion circuit is used to perform voltage-current conversion in a VSL rising establishment process;

[0016] A falling voltage-current conversion circuit, wherein the falling voltage-current conversion circuit is used for performing voltage-current conversion in a VSL falling establishment process;

[0017] A switch circuit is electrically connected to the rising voltage-current conversion circuit and the falling voltage-current conversion circuit respectively, and the switch circuit is used to selectively connect the rising voltage-current conversion circuit and the falling voltage-current conversion circuit.

[0018] In some feasible solutions, the step-down voltage-current conversion circuit includes:

[0019] A first P-channel field effect transistor, one end of which is connected to a drain power supply voltage, and the first P-channel field effect transistor is used to provide a current source;

[0020] a second P-channel field effect transistor, one end of which is also connected to a drain power supply voltage, and the second P-channel field effect transistor is used to provide a bias current;

[0021] A capacitor, the capacitor is arranged at one side of the second P-channel field effect transistor, the capacitor is electrically connected to the second P-channel field effect transistor, and the capacitor is a bypass capacitor of the second P-channel field effect transistor;

[0022] a third P-channel field effect transistor, wherein a gate of the third P-channel field effect transistor is connected to a vertical signal line signal output node, and a source of the third P-channel field effect transistor is connected to the second P-channel field effect transistor;

[0023] A first N-channel field effect transistor, wherein the first N-channel field effect transistor is connected to the second P-channel field effect transistor, and the first N-channel field effect transistor is connected to a drain of the third P-channel field effect transistor;

[0024] A second N-channel field effect transistor, wherein the second N-channel field effect transistor and the first N-channel field effect transistor form a current mirror.

[0025] In some feasible solutions, the rising voltage-current conversion circuit includes:

[0026] a fifth N-channel field effect transistor, wherein the fifth N-channel field effect transistor is used for voltage-current conversion;

[0027] a sixth N-channel field effect transistor, the sixth N-channel field effect transistor being electrically connected to the fifth N-channel field effect transistor, a gate of the sixth N-channel field effect transistor being connected to a bias voltage, and the sixth N-channel field effect transistor being used as a bias current source for the fifth N-channel field effect transistor;

[0028] a fourth P-channel field effect transistor, the fourth P-channel field effect transistor being electrically connected to the fifth N-channel field effect transistor;

[0029] a fifth P-channel field effect transistor, the fifth P-channel field effect transistor being electrically connected to the fourth P-channel field effect transistor, the fifth P-channel field effect transistor and the fourth P-channel field effect transistor forming a current mirror;

[0030] a seventh N-channel field effect transistor, the seventh N-channel field effect transistor being electrically connected to the fifth P-channel field effect transistor, a gate of the seventh N-channel field effect transistor being connected to a bias voltage, and the seventh N-channel field effect transistor being used as a bias current source for the fifth P-channel field effect transistor;

[0031] A second capacitor, wherein the second capacitor is electrically connected to the fifth N-channel field effect transistor, and the second capacitor is used as a bypass capacitor of the fifth N-channel field effect transistor.

[0032] In some feasible solutions, the switch circuit includes:

[0033] A sixth P-channel field effect transistor, wherein a gate of the sixth P-channel field effect transistor is connected to CTRL, and the sixth P-channel field effect transistor is electrically connected to a drain of the second N-channel field effect transistor and a drain of the fifth P-channel field effect transistor, respectively.

[0034] In some feasible solutions, the negative impedance conversion unit includes:

[0035] A first capacitor, wherein the first capacitor is electrically connected to the pixel array unit;

[0036] a third N-channel field effect transistor, wherein a gate of the third N-channel field effect transistor is electrically connected to a bias voltage;

[0037] a fourth N-channel field effect transistor, wherein a gate of the fourth N-channel field effect transistor is electrically connected to the pixel array unit, a drain of the fourth N-channel field effect transistor is connected to a power source, and a source of the fourth N-channel field effect transistor is electrically connected to a drain of the third N-channel field effect transistor;

[0038] One end of the first capacitor is electrically connected to the source of the fourth N-channel field effect transistor, and the other end of the first capacitor is electrically connected to the current mirror circuit unit.

[0039] In some feasible solutions, the current mirror circuit unit further includes:

[0040] The two N-channel field effect transistors are connected via a common source and a common gate, the gates of the N-channel field effect transistors connected via a common source and a common gate are connected to a bias voltage, and the sources of the N-channel field effect transistors connected via a common source and a common gate are electrically connected to the pixel array unit, the negative impedance conversion unit, and the charge and discharge acceleration unit, respectively.

[0041] In some feasible solutions, the charge and discharge acceleration unit includes:

[0042] A rising voltage-current conversion circuit and / or a falling voltage-current conversion circuit.

[0043] A second aspect of the present invention provides an image sensing readout system, which uses an image sensing readout circuit described in any one of the first aspects, and the readout system further includes:

[0044] A pixel driving module, wherein the pixel driving module comprises: a plurality of pixel array units;

[0045] A pixel noise detection module, the pixel noise detection module is electrically connected to the pixel driving module, and the pixel noise detection module is used to detect the pixel array unit in the pixel driving module;

[0046] A reference slope generating module, wherein the reference slope generating module is electrically connected to the pixel driving module;

[0047] A comparator, the comparator being electrically connected to the readout circuit and the reference ramp generating module respectively;

[0048] a counter, the counter being electrically connected to the comparator;

[0049] A data transmission module is electrically connected to the counter.

[0050] A third aspect of the present invention provides a solid-state imaging device, which uses an image sensing readout circuit described in any one of the first aspects or uses an image sensing readout system described in the second aspect.

[0051] The beneficial effects of the present invention are:

[0052] The present invention utilizes a negative impedance conversion unit and a charge-discharge acceleration unit, and utilizes the negative impedance conversion unit to generate negative impedance to offset the parasitic impedance that affects the VSL establishment speed, so as to accelerate the small signal establishment speed; and utilizes the charge-discharge acceleration unit to selectively cooperate with the VSL decline establishment process or rise establishment process to provide charge-discharge current, so as to accelerate the large signal establishment speed. That is, in the present application, corresponding response coordination can be performed for the VSL decline establishment process or rise establishment process. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1 A schematic diagram of the working connection of an image sensing readout circuit provided in an embodiment of the present invention;

[0054] Figure 2 A schematic diagram of the structure of a pixel array unit in a pixel driving module provided in an embodiment of the present invention;

[0055] Figure 3 A schematic diagram of the connection between an image sensing readout circuit and a pixel array provided in an embodiment of the present invention;

[0056] Figure 4 A schematic diagram of the connection of a current mirror circuit unit of an image sensing readout circuit provided in an embodiment of the present invention;

[0057] Figure 5 A schematic diagram of a negative impedance conversion circuit for generating a negative resistance in a readout circuit for image sensing provided in an embodiment of the present invention;

[0058] Figure 6 A schematic diagram of a VSL establishment process in an image sensing readout circuit provided in an embodiment of the present invention;

[0059] Figure 7The present invention is a schematic diagram of the connection of a charge-discharge conversion unit in an image sensing readout circuit provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0060] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0061] It should be noted that all directional indications in the embodiments of the present invention (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0062] In the present invention, unless otherwise clearly specified and limited, the terms "connection", "fixation", etc. should be understood in a broad sense. For example, "fixation" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0063] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the meaning of "and / or" appearing in the full text includes three parallel schemes. Taking "A and / or B" as an example, it includes scheme A, or scheme B, or a scheme that satisfies both A and B. In addition, the technical solutions between the various embodiments can be combined with each other, but it must be based on the ability of ordinary technicians in the field to implement. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0064] Reference Figures 1 to 7The present invention aims to solve the problem that the prior art cannot respond to the pixel array output signal VSL when it is established from a low level to an upward level. In the first aspect, a readout circuit for image sensing is provided. The readout circuit uses a negative impedance conversion unit 1062 and a charge and discharge acceleration unit 1063. The negative impedance generated by the negative impedance conversion unit 1062 is offset by the parasitic capacitance 1102 that affects the VSL establishment speed, so as to accelerate the small signal establishment speed; and the charge and discharge acceleration unit 1063 is used to selectively cooperate with the VSL falling establishment process or the rising establishment process to provide a charge and discharge current, so as to accelerate the large signal establishment speed. That is, in the present application, a corresponding response can be coordinated with the VSL falling establishment process or the rising establishment process.

[0065] Reference Figure 4 , Figure 5 Specifically, the first aspect of the present invention provides a readout circuit for image sensing, comprising: a pixel array unit 100, a current mirror circuit unit 1061, a negative impedance conversion unit 1062 and a charge and discharge acceleration unit 1063, wherein the pixel array unit 100 is used for photoelectric signal conversion; the current mirror circuit unit 1061 is electrically connected to the pixel array unit 100, and the current mirror circuit unit 1061 is used for providing a bias current; wherein the current mirror circuit unit 1061 may include: a common source and common gate current mirror or two N-channel field effect transistors; The current mirror circuit 1061 includes: a cascode current mirror or two N-channel field effect transistors; specifically, the current mirror circuit 1061 can be composed of two N-channel field effect transistors (i.e., including: N-channel field effect transistor 10611 and N-channel field effect transistor 10612) connected by cascode, the gate of the N-channel field effect transistor connected by cascode is connected with a bias voltage, and the source of the N-channel field effect transistor connected by cascode is electrically connected to the pixel matrix unit 100, the negative impedance conversion unit 1062, and the charge and discharge acceleration unit 1063. That is, the gates of the two N-channel field effect transistors connected by cascode are respectively connected with VB2 and VB1 as the bias voltage of the cascode current mirror. Then the vertical signal line output node VSL_OUT1103 is connected to the negative impedance conversion unit 1062 and the charge and discharge acceleration unit 1063. It should be noted that the negative impedance conversion unit 1062 and the charge and discharge acceleration unit 1063 can be connected to the vertical signal line output node VSL_OUT1103 at the same time, or can be connected to the vertical signal line output node VSL_OUT1103 separately when only one of them is provided. The negative impedance conversion unit 1062 is electrically connected to the current mirror circuit unit 1061, and the negative impedance conversion unit 1062 is used to generate negative impedance to offset the parasitic impedance of VSL itself (such as parasitic capacitor 1101); the charge and discharge acceleration unit 1063 is used to provide charge and discharge current during the VSL drop establishment process or rise establishment process.

[0066] Reference Figure 2 and Figure 3 In this embodiment, the pixel array unit 100 may be provided with a plurality of pixels, and the pixel array unit 100 includes: a photodiode 1001, an N-channel field effect transistor 1002, an N-channel field effect transistor 1003, an N-channel field effect transistor 1004, and an N-channel field effect transistor 1005. When exposed to light, the photodiode 1001 completes the photoelectric conversion, and generates photogenerated electrons. When resetting, the gate connection signal RST of the N-channel field effect transistor 1003 is set high, the N-channel field effect transistor 1003 is turned on, and the potential of the floating diffusion point FD (Floating Diffusion) 1006 is reset to a level slightly lower than the power supply VDD, and then the RST signal is set low to end the reset operation. When reading a signal, the gate connection signal TX of the N-channel field effect transistor 1002 is set high, and the N-channel field effect transistor 1002 is turned on. Since the potential of the floating diffusion point FD1006 is higher than the positive end of the photodiode 1001, the photogenerated electrons generated by the photodiode 1001 move to the floating diffusion point FD1006 through the N-channel field effect transistor 1002, causing its voltage to drop. At this time, if the pixel row where the pixel unit 1000 is located is in the readout state, the gate connection signal SEL of the N-channel field effect transistor 1005 is set high, and the N-channel field effect transistor 1004 is in the source follower working state when the N-channel field effect transistor 1005 is turned on. When the potential of the floating diffusion point FD1006 drops, it causes the vertical signal line node VSL1007 to drop a voltage slightly less than the voltage change of the floating diffusion point FD1006; at this time, the voltage change of the vertical signal line node VSL1007 corresponds to the signal amount brought by the photogenerated electrons. In addition, the metal routing parasitic resistance 1101 of the vertical signal line node VSL1007 can be represented by resistor R0, its metal routing parasitic capacitance 1102 can be represented by capacitor C0, the load current source can be represented by an ideal current source 1104, and the vertical signal line output node connected to the load current source 1104 is VSL_OUT1103.

[0067] Reference Figure 5In this embodiment, in order to facilitate understanding of how to use the negative impedance conversion unit 1062 to generate negative impedance and offset the parasitic impedance during the rise or fall of VSL, the following description is given here. In this embodiment, the negative impedance conversion unit 1062 also includes: a first capacitor 10621, a third N-channel field effect transistor 10622, and a fourth N-channel field effect transistor 10623. The first capacitor 10621 is electrically connected to the pixel array unit 100; the gate of the third N-channel field effect transistor 10622 is electrically connected to the pixel array unit 100; A bias voltage is connected; the gate of the fourth N-channel field effect transistor 10623 is electrically connected to the pixel array unit, the drain of the fourth N-channel field effect transistor 10623 is connected to a power supply, and the source of the fourth N-channel field effect transistor 10623 is electrically connected to the drain of the third N-channel field effect transistor 10622; wherein one end of the first capacitor 10621 is electrically connected to the source of the fourth N-channel field effect transistor 10623, and the other end of the first capacitor 10621 is electrically connected to the current mirror circuit unit 1061. That is, in the negative impedance conversion unit 1062 of the present embodiment, the third N-channel field effect transistor 10622 is used as a bias current source for the fourth N-channel field effect transistor 10623; the fourth N-channel field effect transistor 10623 is used as a source follower, the gate of the fourth N-channel field effect transistor 10623 is connected to the vertical signal line output node VSL_OUT1103, the drain of the fourth N-channel field effect transistor 10623 is connected to the power supply, and the source of the fourth N-channel field effect transistor 10623 is connected to the drain of the third N-channel field effect transistor 10622 and one end of the first capacitor 10621. The other end of the first capacitor 10621 is connected to the source of an N-channel field effect transistor 10611 in the common source and common gate current mirror circuit unit 1061. Therefore, in this embodiment, when the vertical signal line output node VSL_OUT1103 drops Vin=V1, assuming that the input current is Iin and ignoring the body effect of the fourth N-channel field effect transistor 10623 (for example, connecting its substrate to the source), it can be considered that the transfer gain of the source follower is approximately equal to 1 at this time. At this time, for the negative impedance conversion unit in this embodiment, the transconductance of an N-channel field effect transistor 10611 in the common source and common gate current mirror circuit unit 1061 is gm1, and its source voltage change is Vx, the source voltage change of the fourth N-channel field effect transistor 10623 is Vy, the output impedance of the third N-channel field effect transistor 10622 is Ro, and the transconductance of the fourth N-channel field effect transistor 10623 is gm2. According to Kirchhoff's current-voltage theorem, it can be obtained that:

[0068] gm2*(Vin-Vy)+(Vx-Vy) / (1 / (s*C_NI))=Vy / Ro;

[0069] Iin=-gm1*Vx=(Vx-Vy) / (1 / (s*C_NI));

[0070] After transforming and simplifying the above equations, we can get approximately:

[0071] Zin=Vin / Iin=[gm1+gm1*gm2*Ro+s*C_NI*(gm2*Ro+gm1*Ro)] / gm1*gm2*Ro*s*C_NI;

[0072] In the formula, C_NI is the first capacitor. It can be seen from the above formula that at this time, the equivalent input impedance of the negative impedance conversion unit 1062 at low frequency is expressed as the sum of negative resistance and negative capacitance, and the equivalent input impedance at high frequency is expressed as negative resistance, but the resistance value is small; therefore, gm2 and Ro can be reasonably designed according to actual conditions, so that the negative impedance conversion unit 1062 can have a negative capacitance that can offset the parasitic capacitance 1102, thereby accelerating the speed of small signal establishment.

[0073] Reference Figure 6 and Figure 7 In this embodiment, in order to facilitate understanding of how the charge and discharge acceleration unit 1063 can provide charge and discharge currents respectively for the VSL rising establishment process or the falling establishment process, the following description is given here. Specifically, the charge and discharge acceleration unit 1063 includes: a rising voltage-current conversion circuit, a falling voltage-current conversion circuit, and a switching circuit. One end of the rising voltage-current conversion circuit is connected to a drain power supply voltage. The rising voltage-current conversion circuit is used to perform voltage-current conversion in the VSL rising establishment process; the falling voltage-current conversion circuit is used to perform voltage-current conversion in the VSL falling establishment process; the switching circuit is electrically connected to the rising voltage-current conversion circuit and the falling voltage-current conversion circuit respectively, and the switching circuit is used to select the rising voltage-current conversion circuit and the falling voltage-current conversion circuit to be connected. That is, in this embodiment, a switching circuit, a falling voltage-current conversion circuit and a rising-falling voltage-current conversion circuit are provided in the charge and discharge acceleration unit 1063, and the gate of the switching circuit is externally connected to CTRL, and the switching circuit is electrically connected to the rising voltage-current conversion circuit and the falling voltage-current conversion circuit respectively, so that when the vertical signal line node VSL1007 falls, the switching circuit is turned on; when the vertical signal line node VSL1007 rises, the switching circuit is turned off.

[0074] Reference Figure 7Specifically, the falling voltage-current conversion circuit includes: a first P-channel field effect transistor 10636, a second P-channel field effect transistor 10631, a capacitor 10632, a third P-channel field effect transistor 10633, a first N-channel field effect transistor 10634 and a second N-channel field effect transistor 10635. One end of the first P-channel field effect transistor 10636 is connected to a drain power supply voltage, and the first P-channel field effect transistor 10636 is used to provide a current source; one end of the second P-channel field effect transistor 10631 is also connected to a drain power supply voltage, and the second P-channel field effect transistor 10631 is used to provide a bias current; the capacitor 10632 is arranged on one side of the second P-channel field effect transistor 10631, and the capacitor 10632 is electrically connected to the second P-channel field effect transistor 10631. The capacitor 10632 is a bypass capacitor of the second P-channel field effect transistor 10631 (i.e., reducing the second P-channel field effect transistor 106 31 generated noise and voltage fluctuation); the gate of the third P-channel field effect transistor 10633 is connected to the vertical signal line signal output node VSL_OUT1103, and the source of the third P-channel field effect transistor 10633 is connected to the second P-channel field effect transistor 10631; the first N-channel field effect transistor 10634 is connected to the second P-channel field effect transistor 10631, and the first N-channel field effect transistor 10634 is connected to the drain of the third P-channel field effect transistor 10633; the second N-channel field effect transistor 10635 and the first N-channel field effect transistor 10634 form a current mirror. In this embodiment, the first P-channel field effect transistor 10636 and the second P-channel field effect transistor 10631 can act as a current source, and the capacitor 10632 can be used as a bypass capacitor of the second P-channel field effect transistor 10631. The second P-channel field effect transistor 10631 is a third P-channel field effect transistor 10633 and a first N-channel field effect transistor 10634. The gate of the third P-channel field effect transistor 10633 is connected to the vertical signal line output node VSL_OUT1103, and the drain of the third P-channel field effect transistor 10633 and the first N-channel field effect transistor 10634, the first N-channel field effect transistor 10634 and the second N-channel field effect transistor 10635 form a current mirror, and the current mirror ratio is determined by the ratio of the width-to-length ratio of the second N-channel field effect transistor 10635 to the width-to-length ratio of the first N-channel field effect transistor 10634. The current of the first P-channel field effect transistor 10636 as a current source is set to be slightly equal to the saturation current of the second N-channel field effect transistor 10635.During the falling establishment process of the vertical signal line output node VSL_OUT1103, the gate voltage of the third P-channel field effect transistor 10633 drops by ΔV. At this time, the third P-channel field effect transistor 10633 acts as a source follower, and its source voltage will drop. At this time, the capacitor 10632, which acts as a bypass capacitor, acts as a current source to provide a transient current ΔI=C1*dΔV / dt for the second P-channel field effect transistor 10631. The transient current is amplified by the current mirror composed of the first N-channel field effect transistor 10634 and the second N-channel field effect transistor 10635, and its amplification factor is as described above, which is the ratio of the width-to-length ratio of the second N-channel field effect transistor 10635 to the first N-channel field effect transistor 10634:.

[0075] K=(W / L)_10635 / (W / L)_10634.

[0076] Therefore, it can be known that the transient output current generated by the drain of the second N-channel field effect transistor 10635 is K*ΔI. Since the first P-channel field effect transistor 10636 is set to a constant current working state, the transient current K*ΔI will be provided by the load capacitor through the vertical signal line output node VSL_OUT1103; if the current of the current source is set to I, then in this embodiment, the current flowing out of the load capacitor during the large signal establishment period can be expressed as I+K*ΔI, and its size can be adjusted by adjusting the capacitance value of the capacitor and the current mirror ratio K. Therefore, in this embodiment, the charge and discharge acceleration circuit 1063 speeds up the large signal establishment speed of the vertical signal line output node VSL_OUT1103 by increasing the transient current flowing out of the load capacitor during the large signal establishment period. It should be noted that under this working condition, all field effect transistors operate in a saturated state.

[0077] Specifically, the rising voltage-current conversion circuit includes: a fifth N-channel field effect transistor 10637, a sixth N-channel field effect transistor 106371, a fourth P-channel field effect transistor 106373, a fifth P-channel field effect transistor 106374, a seventh N-channel field effect transistor 106372, and a second capacitor 106376, wherein the fifth N-channel field effect transistor 10637 is used for voltage-current conversion; the sixth N-channel field effect transistor 106371 is electrically connected to the fifth N-channel field effect transistor 10637, the gate of the sixth N-channel field effect transistor 106371 is connected to a bias voltage, and the sixth N-channel field effect transistor 106371 is used as a bias current source for the fifth N-channel field effect transistor 10637; the fourth P-channel field effect transistor 106373 is electrically connected to the fifth N-channel field effect transistor 106374, the seventh N-channel field effect transistor 106372, and a second capacitor 106376. The fifth P-channel field effect transistor 106374 is electrically connected to the fourth P-channel field effect transistor 106373, and the fifth P-channel field effect transistor 106374 and the fourth P-channel field effect transistor 106373 form a current mirror; the seventh N-channel field effect transistor 106372 is electrically connected to the fifth P-channel field effect transistor 106374, and the gate of the seventh N-channel field effect transistor 106372 is connected to a bias voltage, and the seventh N-channel field effect transistor 106372 is used as a bias current source for the fifth P-channel field effect transistor 106374; the second capacitor 106376 is electrically connected to the fifth N-channel field effect transistor 10637, and the second capacitor 106376 is used as a bypass capacitor for the fifth N-channel field effect transistor 10637. That is, in this embodiment, the fifth N-channel field effect transistor 10637 is used as a voltage-current converter in the charge and discharge acceleration circuit 1063; the sixth N-channel field effect transistor 106371 is used as a bias current source for the fifth N-channel field effect transistor 10637, and its gate is connected to the bias voltage VB5; the fourth P-channel field effect transistor 106373 and the fifth P-channel field effect transistor 106374 form a current mirror, and the current flowing through the fifth N-channel field effect transistor 10637 also flows through the fourth P-channel field effect transistor 106373. The seventh N-channel field effect transistor 106372 is used as a bias current source for the fifth P-channel field effect transistor 106374, and its gate is connected to the bias voltage VB6, and VB6 is designed so that the DC current of the seventh N-channel field effect transistor 106372 is approximately equal to that of the fifth P-channel field effect transistor 106374.In the above-mentioned charge and discharge acceleration unit, the switch circuit includes: a sixth P-channel field effect transistor 106375, the gate of the sixth P-channel field effect transistor is connected with CTRL, and the sixth P-channel field effect transistor is respectively electrically connected with the drain of the second N-channel field effect transistor and the drain of the fifth P-channel field effect transistor 106374. That is, the gate of the sixth P-channel field effect transistor can be connected with CTRL to realize the selective switching of the rising voltage-current conversion circuit or the falling voltage-current conversion circuit according to the actual situation of the establishment of VSL.

[0078] In this embodiment, a rising voltage-current conversion circuit is adopted. When the vertical signal line node VSL1007 rises, so that the vertical signal line node VSL_OUT1103 rises, the fifth N-channel field effect transistor 10637 works as a source follower. When its source voltage rises by ΔV, the voltage difference between the two plates of the second capacitor 106376 increases. At this time, the charging current change of the second capacitor 106376 is: ΔI = C2*dΔV / dt, C2 is the second capacitor 106376, and this part ΔI also flows through the fourth P-channel field effect transistor 106373 constituting the current mirror. The transient current is amplified by the current mirror composed of the fourth P-channel field effect transistor 106373 and the fifth P-channel field effect transistor 106374, and its amplification factor is the ratio of the width-to-length ratio of the fourth P-channel field effect transistor 106373 to the fifth P-channel field effect transistor 106374:

[0079] K=(W / L)_106374 / (W / L)_106373;

[0080] As can be seen from the above, the transient output current generated by the drain of the fifth P-channel field effect transistor 106374 is K*ΔI. Since the seventh N-channel field effect transistor 106372 is set to a constant current working state, the transient current K*ΔI will charge the load capacitor through the vertical signal line node VSL_OUT1103; if the current flowing through the N-channel field effect transistor 1004 of the pixel array unit 100 is I, then in this embodiment, the current flowing into the load capacitor during the rise establishment period of the vertical signal line node VSL_OUT1103 can be expressed as I+K*ΔI, and its size can be adjusted by adjusting the capacitance of the bypass capacitor (i.e., the second capacitor 106376) and the current mirror ratio K. Therefore, in this embodiment, the charge and discharge acceleration circuit 1602 accelerates the establishment speed of the vertical signal line node VSL_OUT1103 during the rise establishment period by increasing the transient current charged to the load capacitor during the rise establishment period of the vertical signal line VSL_OUT1103.

[0081] Reference Figure 1According to a second aspect of the present invention, there is provided an image sensing readout system, which adopts an image sensing readout circuit 106 described in any one of the first aspects, and the readout system further comprises: a pixel driving module 101, a pixel noise detection module 102, and a reference slope generating module 103, wherein the pixel driving module 101 comprises: a plurality of pixel array units 100, and the pixel array units 100 are used for photoelectric conversion; the pixel noise detection module 102 is electrically connected to the pixel driving module 101, and the pixel noise detection module 102 is used for detecting the pixel array units 100 in the pixel driving module 101; the reference slope generating module 103 is electrically connected to the pixel driving module 101; the comparator 107 is electrically connected to the readout circuit 106 and the reference slope generating module 103 respectively; the counter 108 is electrically connected to the comparator 107; and the data transmission module 109 is electrically connected to the counter 108. The readout system is equipped with a charge and discharge acceleration unit that can be used for the VSL rising establishment process and / or the VSL falling establishment process, so that the establishment time of the vertical signal line node VSL1007 can be accelerated regardless of whether it is a rising establishment process or a falling establishment process.

[0082] It should be noted that in the present readout system, the rising voltage-current conversion circuit and the falling voltage-current conversion circuit may both exist in the readout system at the same time or may exist separately, that is, the rising voltage-current conversion circuit and / or the falling voltage-current conversion circuit in the readout system.

[0083] In some embodiments, the readout system can communicate using any currently known or future developed network protocol such as HTTP (HyperTextTransferProtocol), and can be interconnected with digital data communication (e.g., communication network) of any form or medium. Examples of communication networks include local area networks ("LAN"), wide area networks ("WAN"), internets (e.g., the Internet), and peer-to-peer networks (e.g., adhoc peer-to-peer networks), as well as any currently known or future developed networks. The functions described above herein can be performed at least in part by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that can be used include: field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), and the like.

[0084] The third aspect of the present invention provides a solid-state imaging device, which adopts an image sensing readout circuit described in any one of the first aspects or an image sensing readout system described in the second aspect. That is, in the solid-state imaging device, the signal establishment of VSL can be performed by using the above-mentioned current mirror circuit unit 1061, negative impedance conversion unit, and charge and discharge acceleration unit 1063, and at the same time, the rising voltage-current conversion circuit and the falling voltage-current conversion circuit can respectively accelerate the establishment time of the vertical signal line node VSL1007 whether it is a rising establishment process or a falling establishment process, so as to meet the imaging requirements.

[0085] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some implementations as replacements, the functions marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two square boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0086] The above descriptions are only some preferred embodiments of the present disclosure and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the embodiments of the present disclosure is not limited to the technical solutions formed by a specific combination of the above-mentioned technical features, but should also cover other technical solutions formed by any combination of the above-mentioned technical features or their equivalent features without departing from the above-mentioned inventive concept. For example, the above-mentioned features are replaced with the technical features with similar functions disclosed in the embodiments of the present disclosure (but not limited to) and the technical solutions formed.

Claims

1. A readout circuit for image sensing, characterized in that: include: A pixel array unit, wherein the pixel array unit is used for photoelectric signal conversion; A current mirror circuit unit, the current mirror circuit unit is electrically connected to the pixel array unit, and the current mirror circuit unit is used to provide a bias current; Wherein, the current mirror circuit unit comprises: a common-source common-gate current mirror or two N-channel field effect transistors; A negative impedance conversion unit, the negative impedance conversion unit is electrically connected to the current mirror circuit unit, and the negative impedance conversion unit is used to generate negative impedance to offset the parasitic impedance of VSL itself; A charge and discharge acceleration unit is used to provide charge and discharge current during the VSL drop establishment process or the VSL rise establishment process.

2. The image sensing readout circuit according to claim 1, characterized in that: The charge and discharge acceleration unit comprises: A rising voltage-current conversion circuit, one end of which is connected to a drain power supply voltage, and the rising voltage-current conversion circuit is used to perform voltage-current conversion in a VSL rising establishment process; A falling voltage-current conversion circuit, wherein the falling voltage-current conversion circuit is used for performing voltage-current conversion in a VSL falling establishment process; A switch circuit is electrically connected to the rising voltage-current conversion circuit and the falling voltage-current conversion circuit respectively, and the switch circuit is used to selectively connect the rising voltage-current conversion circuit and the falling voltage-current conversion circuit.

3. The image sensing readout circuit according to claim 2, characterized in that: The step-down voltage-current conversion circuit comprises: A first P-channel field effect transistor, one end of which is connected to a drain power supply voltage, and the first P-channel field effect transistor is used to provide a current source; a second P-channel field effect transistor, one end of which is also connected to a drain power supply voltage, and the second P-channel field effect transistor is used to provide a bias current; A capacitor, the capacitor is arranged at one side of the second P-channel field effect transistor, the capacitor is electrically connected to the second P-channel field effect transistor, and the capacitor C1 is a bypass capacitor of the second P-channel field effect transistor; a third P-channel field effect transistor, wherein a gate of the third P-channel field effect transistor is connected to a vertical signal line signal output node, and a source of the third P-channel field effect transistor is connected to the second P-channel field effect transistor; A first N-channel field effect transistor, wherein the first N-channel field effect transistor is connected to the second P-channel field effect transistor, and the first N-channel field effect transistor is connected to a drain of the third P-channel field effect transistor; A second N-channel field effect transistor, wherein the second N-channel field effect transistor and the first N-channel field effect transistor form a current mirror.

4. The image sensing readout circuit according to claim 3, characterized in that: The rising voltage-current conversion circuit comprises: a fifth N-channel field effect transistor, wherein the fifth N-channel field effect transistor is used for voltage-current conversion; a sixth N-channel field effect transistor, the sixth N-channel field effect transistor being electrically connected to the fifth N-channel field effect transistor, a gate of the sixth N-channel field effect transistor being connected to a bias voltage, and the sixth N-channel field effect transistor being used as a bias current source for the fifth N-channel field effect transistor; a fourth P-channel field effect transistor, the fourth P-channel field effect transistor being electrically connected to the fifth N-channel field effect transistor; a fifth P-channel field effect transistor, the fifth P-channel field effect transistor being electrically connected to the fourth P-channel field effect transistor, the fifth P-channel field effect transistor and the fourth P-channel field effect transistor forming a current mirror; a seventh N-channel field effect transistor, the seventh N-channel field effect transistor being electrically connected to the fifth P-channel field effect transistor, a gate of the seventh N-channel field effect transistor being connected to a bias voltage, and the seventh N-channel field effect transistor being used as a bias current source for the fifth P-channel field effect transistor; A second capacitor, wherein the second capacitor is electrically connected to the fifth N-channel field effect transistor, and the second capacitor is used as a bypass capacitor of the fifth N-channel field effect transistor.

5. The image sensing readout circuit according to claim 4, characterized in that: The switch circuit comprises: A sixth P-channel field effect transistor, wherein a gate of the sixth P-channel field effect transistor is connected to CTRL, and the sixth P-channel field effect transistor is electrically connected to a drain of the second N-channel field effect transistor and a drain of the fifth P-channel field effect transistor, respectively.

6. The image sensing readout circuit according to claim 5, characterized in that: The negative impedance conversion unit comprises: A first capacitor, wherein the first capacitor is electrically connected to the pixel array unit; a third N-channel field effect transistor, wherein a gate of the third N-channel field effect transistor is electrically connected to a bias voltage; a fourth N-channel field effect transistor, wherein a gate of the fourth N-channel field effect transistor is electrically connected to the pixel array unit, a drain of the fourth N-channel field effect transistor is connected to a power source, and a source of the fourth N-channel field effect transistor is electrically connected to a drain of the third N-channel field effect transistor; One end of the first capacitor is electrically connected to the source of the fourth N-channel field effect transistor, and the other end of the first capacitor is electrically connected to the current mirror circuit unit.

7. The image sensing readout circuit according to claim 6, characterized in that: The current mirror circuit unit also includes: The two N-channel field effect transistors are connected via a common source and a common gate, the gates of the N-channel field effect transistors connected via a common source and a common gate are connected to a bias voltage, and the sources of the N-channel field effect transistors connected via a common source and a common gate are electrically connected to the pixel array unit, the negative impedance conversion unit, and the charge and discharge acceleration unit, respectively.

8. The image sensing readout circuit according to claim 2, characterized in that: The charge and discharge acceleration unit comprises: A rising voltage-current conversion circuit and / or a falling voltage-current conversion circuit.

9. A readout system for image sensing, characterized in that: An image sensing readout circuit according to any one of claims 1 to 8 is used, wherein the readout system further comprises: A pixel driving module, wherein the pixel driving module comprises: a plurality of pixel array units; A pixel noise detection module, the pixel noise detection module is electrically connected to the pixel driving module, and the pixel noise detection module is used to detect the pixel array unit in the pixel driving module; A reference slope generating module, wherein the reference slope generating module is electrically connected to the pixel driving module; A comparator, the comparator being electrically connected to the readout circuit and the reference ramp generating module respectively; a counter, the counter being electrically connected to the comparator; A data transmission module is electrically connected to the counter.

10. A solid-state imaging device, characterized in that An image sensing readout circuit according to any one of claims 1 to 8 or an image sensing readout system according to claim 9 is used.

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