Transistor designed to reduce leakage

Abstract

Embodiments of the present disclosure provide devices, apparatuses, and methods related to leakage reduced FETs. In some embodiments, a device on a silicon-on-insulator substrate may include a silicon layer; a gate structure at least partially overlaid on the silicon layer; and an oxide layer disposed between the silicon layer and the partial overlay of the gate structure, wherein: the oxide layer includes a first portion and a second portion; the first portion of the oxide layer is thicker than the second portion of the oxide layer; and the first part of the oxide layer covers at least one part of the first edge of the partially overlapped silicon layer.

Description

Technical Field

[0001] The description herein relates to the field of integrated circuit (IC) field effect transistor (FET) design and, more particularly, to FETs designed for reduced leakage. Background Art

[0002] In the fabrication of integrated circuit (IC) field effect transistors (FETs), a silicon-on-insulator (SOI) substrate can be used instead of over a bulk silicon substrate because the SOI substrate results in higher speed, lower power consumption, improved radio frequency (RF) performance, and improved radiation resistance. The FET can have different voltage domains and logics that operate between wide voltage ranges. Summary of the Invention

[0003] Embodiments of the present disclosure provide devices, apparatuses, and methods related to FETs with reduced leakage. In some embodiments, a device on a silicon-on-insulator substrate can include a silicon layer; a gate structure that at least partially overlaps the silicon layer; and an oxide layer disposed between the silicon layer and the partial overlap of the gate structure, wherein: the oxide layer includes a first portion and a second portion; the first portion of the oxide layer is thicker than the second portion of the oxide layer; and the first portion of the oxide layer covers at least a portion of a first edge of the silicon layer in the partial overlap.

[0004] In some embodiments, a method of forming a device on a silicon-on-insulator substrate can include: providing a silicon layer; providing an oxide layer; and providing a gate structure that at least partially overlaps the silicon layer, wherein: the oxide layer is disposed between the silicon layer and the partial overlap of the gate structure; the oxide layer includes a first portion and a second portion; the first portion of the oxide layer is thicker than the second portion of the oxide layer; and the first portion of the oxide layer covers at least a portion of a first edge of the silicon layer in the partial overlap.

[0005] In some embodiments, a silicon-on-insulator substrate can include a silicon layer; an oxide layer for receiving a portion of a gate structure, wherein: the oxide layer includes a first portion and a second portion; the first portion of the oxide layer is thicker than the second portion of the oxide layer; and the first portion of the oxide layer covers at least a portion of a first edge of the silicon layer.

[0006] In some embodiments, a device on a silicon-on-insulator substrate may include silicon islands formed in a silicon layer; a first gate structure formed in an active region on the silicon island, the first gate structure including a first gate oxide layer having a first gate oxide layer thickness; and a second gate structure and a third gate structure, the second gate structure and the third gate structure each formed above an edge of the silicon island and each extending from the first gate structure, the second gate structure including a second gate oxide layer having a second gate oxide layer thickness, and the third gate structure including a third gate oxide layer having a third gate oxide layer thickness, wherein the first gate oxide layer thickness is less than the second gate oxide layer thickness and less than the third gate oxide layer thickness.

[0007] In some embodiments, a method of forming a device on a silicon-on-insulator substrate may include: providing a silicon layer; providing an active region in the silicon layer; providing a first gate oxide layer above at least a portion of a central region of the active region; providing a second gate oxide layer above at least one edge of the active region; providing a conductive gate material above the first gate oxide layer and the second gate oxide layer; and forming a gate structure in the silicon layer that overlaps the active region, wherein: the gate structure extends across the active region, covering at least two edges and at least a portion of the central region; and the first gate oxide layer is thinner than the second gate oxide layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a top view of a layout of a transistor on an SOI substrate consistent with an embodiment of the present disclosure.

[0009] Figure 2 is a cross-sectional view of an edge region of a transistor fabricated on an SOI substrate consistent with an embodiment of the present disclosure.

[0010] Figure 3 is a top view of a layout of a transistor fabricated on an SOI substrate consistent with an embodiment of the present disclosure.

[0011] Figure 4 shows a flowchart representing an exemplary method of forming a transistor on an SOI substrate consistent with an embodiment of the present disclosure. DETAILED DESCRIPTION

[0012] Reference will now be made in detail to exemplary embodiments, which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings, where like numbers in different drawings represent the same or similar elements unless otherwise noted. The implementations set forth in the following description of the exemplary embodiments do not represent all implementations consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with aspects related to the subject matter recited in the appended claims. Other features, objects, and advantages of the invention will be apparent from the specification, the drawings, and from the claims.

[0013] Although terms such as "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, without departing from the scope of the embodiments, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0014] As used herein, unless otherwise specifically stated, the term "or" encompasses all possible combinations, unless infeasible. For example, if it is specified that a component may include A or B, then unless otherwise specifically stated or infeasible, the component may include A, or B, or A and B. As a second example, if it is specified that a component may include A, B, or C, then unless otherwise specifically stated or infeasible, the component may include A, or B, or C, or A and B, or A and C, or B and C, or A and B and C.

[0015] Devices with an SOI substrate can use thin silicon to obtain better switching performance, but thin silicon has limitations in the following aspects: it tends to reduce the threshold voltage of the device, thereby increasing current leakage. These effects increase towards the edge region of the thin silicon, where the thin silicon forms a "tip" (also known as a "bird's beak"), which is formed during manufacturing by an oxidation or shallow trench isolation (STI) process and is particularly thin. This tip of the thin silicon has a particularly low threshold voltage, thereby increasing the current leakage of the device, which is commonly referred to as "edge leakage". In some cases, the threshold voltage of the thin silicon tip can be as low as zero volts (V). The thickness of the thin silicon can also be reduced due to the oxygen diffusion path at the edge of the thin silicon and under the thin silicon. This oxygen diffusion may cause or form the tip or bird's beak of the thin silicon. In addition, due to the oxidation of the thin silicon by the gate oxide, the thickness of the thin silicon can be further reduced, thereby reducing the threshold voltage and increasing the current leakage.

[0016] If any current leakage occurs during the operation of the device, the FET may suffer performance limitations. For example, increased current leakage can increase the power consumption of the device. Therefore, solutions that meet the speed and current leakage requirements of transistors operating in a wide voltage range are needed to address the long-term need to reduce current leakage in SOI, including, for example, radio frequency silicon-on-insulator (RFSOI) technology and complementary metal oxide semiconductor (CMOS) transistors (e.g., bulk CMOS transistors).

[0017] These devices can be fabricated with a thicker gate oxide to improve switching performance. However, using a thicker gate oxide also has the disadvantage of degrading the transistor.

[0018] In addition, oxidation from the gate oxide still reduces the thickness of the thin silicon. For example, in an n-channel MOSFET (NMOSFET), the oxidation process that reduces the thickness of the thin silicon layer can deplete the dopants in the thin silicon, thereby further reducing the threshold voltage. The depletion of dopants in the thin silicon reduces the threshold voltage due to the downward bandgap bending at the edge region of the thin silicon. In a p-channel MOSFET (PMOSFET), the oxidation process can further thin the thin silicon, thereby reducing the threshold voltage.

[0019] In some cases, the threshold voltage can be adjusted by adjusting the doping type and dopant concentration under the gate to help suppress current leakage. However, there are some limitations in adjusting the doping type: a thick gate oxide can be used to reduce current leakage from the doping adjustment, but a device with a thin gate oxide may not be able to operate at the desired voltage. In addition, while using a thin gate oxide increases the drive current in the transistor, it also causes a faster increase in capacitance, thereby reducing the speed of the transistor.

[0020] In some cases, the digital logic using transistors can use a widened gate to increase the effective channel length at the edge region of the active thin silicon. However, the widened gate increases the capacitance of the device, thereby reducing the logic speed. In addition, the widened gate can be used in devices with a thinner gate oxide in a double-gate process, which further reduces the logic speed due to the increased capacitance of the thinner oxide.

[0021] Embodiments of the present disclosure provide devices, apparatuses, and methods for reducing current leakage and operating at high speed between a wide voltage range by enhancing devices with an increased threshold voltage (e.g., having a SOI substrate). For example, some embodiments include a device having two double-gate regions and an active region between the two double-gate regions. In some embodiments, the gate oxide in the active region is thinner than the gate oxide in the double-gate regions. The gate oxide can be thicker in the double-gate regions because each double-gate region can include the edge region of the silicon layer that is more vulnerable to current leakage.

[0022] Some of the drawings of the present disclosure described below illustrate NMOSFETs. However, in some applications, the teachings of the present invention can be applied to PMOSFETs. Therefore, the illustrated embodiments and example materials should not be considered as limiting the scope of the present invention. In some embodiments, a polysilicon gate structure and an oxide gate insulator can be used as examples to describe the embodiments of the present invention, but other gate materials can be used to implement the present invention.

[0023] For the sake of clarity, the relative sizes of components in the drawings may be exaggerated.In the following description of the drawings, identical or similar reference numerals refer to identical or similar components or entities, and only the differences with respect to the various embodiments are described.

[0024] Figure 1 is a top view of a layout of a transistor fabricated on an SOI substrate consistent with an embodiment of the present disclosure.

[0025] In some embodiments, transistor 100 may include a first dual gate region 102, a second dual gate region 106, and a region 104 between the first dual gate region 102 and the second dual gate region 106. For example, region 104 may be an active region between dual gate region 102 and dual gate region 106 (e.g., region 104 is outside dual gate region 102 and outside dual gate region 106). In some embodiments, an island of active silicon layer 112 may be formed on an SOI substrate. A gate structure 108 including an insulator (e.g., an oxide layer) and an overlying gate material (e.g., polysilicon, a conductive material, etc.) may be at least partially formed over silicon layer 112 (e.g., gate structure 108 may at least partially overlying silicon layer 112). In some embodiments, silicon layer 112 may include one or more contacts 114. In some embodiments, transistor 100 may include a P+ implant region 132, an N+ implant region 134 overlying silicon layer 112, and a P+ implant region 136.

[0026] In some embodiments, the silicon layer 112 may be a thin silicon layer to improve switching performance. In some embodiments, an oxide layer may be disposed between the silicon layer 112 and the gate structure 108 overlying.

[0027] For the purpose of illustration, Figure 2 A cross-sectional view of the silicon layer 112 and the oxide layer along AA' is provided in FIG. It should be understood that other layers or components may exist around the silicon layer 112 and the oxide layer, but are not shown in FIG. Figure 2 As shown in Figure 2 As shown, oxidation or STI processes during manufacturing can shape the silicon layer 112 to form particularly thin tips 122a and 122c. Tips 122a and 122c of the silicon layer 112 each have a particularly low threshold voltage, thereby increasing the current leakage of the device. For example, in a dual gate region (e.g., Figure 1 The double gate region 102 or the double gate region 106 or Figure 3 The thickness of the portion 112a of the silicon layer 112 at the edge of the silicon layer 112 in the dual gate region 302 or 306 of the active region (eg, Figure 1 Domain 104 or Figure 3 The thickness of portion 112b of silicon layer 112 in domain 304).

[0028] In order to increase the threshold voltage of the transistor and reduce the current leakage of the transistor, the first portion 142 of the oxide layer in the dual gate region can be thicker than the second portion 144 of the oxide layer in the active region. The first portion 142 of the oxide layer can be thicker in the dual gate region because each dual gate region can include an edge of the silicon layer 112 that is more susceptible to current leakage, as described above. Since higher conduction may be required in the active region and there is a reduced drive current in the active region, the second portion 144 of the oxide layer can be thinner in the active region. In some embodiments, the second portion 144 of the oxide layer can cover at least a portion of the silicon layer 112 in the partial overlap of the gate structure 108. In some embodiments, the second portion 144 of the oxide layer can cover the entire silicon layer 112 in the region 104.

[0029] The first portion 142 of the oxide layer in the dual gate region may also increase the threshold voltage in the tip 122a of the silicon layer 112 formed in the edge of the silicon layer 112. That is, the first portion 142 of the oxide layer may be formed on the tip 122a of the silicon layer 112, thereby making the tip 122 more robust to oxide breakdown and reducing current leakage at the tip 122a. Therefore, the first portion 142 of the oxide layer may be configured to reduce current leakage in the edge transistor of the transistor.

[0030] In some embodiments, the partial overlap of the silicon layer 112 and the gate structure 108 may include a first edge and a second edge of the silicon layer 112 in the at least partial overlap of the gate structure 108. In some embodiments, the first portion 142 of the oxide layer may cover at least a portion of the first edge of the silicon layer 112. In some embodiments, the first portion 142 of the oxide layer may cover the entire silicon layer 112 in the dual gate region 102 (e.g., the first portion 142 of the oxide layer may cover the silicon layer 112 in the dual gate region 102, wherein the gate structure 108 at least partially overlaps the silicon layer 112 and wherein the gate structure 108 does not overlap the silicon layer 112). In some embodiments, the first portion 142 of the oxide layer, the first edge of the silicon layer 112, and the portion of the gate structure 108 on the first edge of the silicon layer 112 may define an edge transistor 110.

[0031] In some embodiments, the oxide layer may include a third portion 146 similar to the first portion 142, which may cover at least a portion of the second edge of the silicon layer 112. Similar to the portion 112a of the silicon layer 112, in the dual gate region (eg, Figure 1 The dual gate region 106 or Figure 1 The dual gate region 102 or Figure 3The thickness of the portion 112c of the silicon layer 112 at the edge of the silicon layer 112 in the dual gate region 306 or 302) can be less than the thickness of the portion 112b of the silicon layer 112 in the active region. In some embodiments, in order to increase the threshold voltage of the transistor and reduce the current leakage of the transistor, the third portion 146 of the oxide layer in the dual gate region can be thicker than the second portion 144 of the oxide layer in the active region. The third portion 146 of the oxide layer can be thicker in the dual gate region because each dual gate region can include an edge of the silicon layer 112 that is more susceptible to current leakage, as described above.

[0032] The third portion 146 of the oxide layer in the dual gate region can also increase the threshold voltage in the tip 122c of the silicon layer 112 formed in the edge of the silicon layer 112. That is, the third portion 146 of the oxide layer can be formed on the tip 122c of the silicon layer 112, thereby making the tip 122c more robust to oxide breakdown and reducing current leakage at the tip 122c. Therefore, the third portion 146 of the oxide layer can be configured to reduce current leakage in the edge transistor of the transistor.

[0033] In some embodiments, the third portion 146 of the oxide layer can cover the entire silicon layer 112 in the dual gate region 106 (e.g., the third portion of the oxide layer can cover the silicon layer 112 in the dual gate region 106, wherein the gate structure 108 at least partially overlaps the silicon layer 112 and wherein the gate structure 108 does not overlap the silicon layer 112). In some embodiments, the third portion 146 of the oxide layer, the second edge of the silicon layer 112, and the portion of the gate structure 108 on the second edge of the silicon layer 112 can define the edge transistor 120. That is, for the purposes of the present disclosure, the edge transistors 110 and 120 can be formed by Figure 1 Thus, the thick part of the oxide layer (e.g. Figure 2 The first portion 142 and the third portion 146 of the edge transistors 110 and 120 may increase the threshold voltage of the edge transistors 110 and 120 and reduce the current leakage in the edge transistors 110 and 120. For example, the threshold voltage of each of the edge transistors 110 and 120 may be increased to be greater than 0 V. In some embodiments, the threshold voltage of each of the edge transistors 110 and 120 may be increased so that they are greater than the threshold voltage of the edge transistors 110 and 120 having a thinner oxide layer (for example, the threshold voltage of the edge transistors 110 and 120 at the first portion 142 and the third portion 146 is greater than the threshold voltage at the edge transistors 110 and 120 having an oxide layer thinner than the first portion 142 and the third portion 146).

[0034] In some embodiments, the dopant concentration in implant region 134 in active region 104 may be higher than the dopant concentration in implant regions 132 and 136 in dual gate regions 102 and 106 so that the threshold voltage in all regions may be high, thereby reducing current leakage.

[0035] In some SOI processes, the device may have the same well for thin and thick oxide regions, but may have different LDD and halo doping for the thin and thick oxide regions. In some embodiments consistent with the present disclosure, different wells may be used for thin and thick oxide regions, but the same LDD and halo doping may be used for thin and thick oxide regions. In some embodiments, when the well doping of the thin oxide region is much higher than the well doping of the thick oxide region, the thick oxide region may have a higher threshold voltage at the edge region to reduce current leakage. In some embodiments, the threshold voltage and current leakage at the edge region may depend on the amount of well doping and the thickness of the oxide (e.g., high well doping and thicker oxide may increase the threshold voltage at the edge region to reduce current leakage).

[0036] Embodiments that form the same LDD and halo doping in thin and thick oxide regions may be advantageous because the only major process adjustment is to adjust the oxide thickness. These embodiments may also be advantageous because they avoid misalignment that may sometimes occur when different LDD and halo doping are formed in thin and thick oxide regions.

[0037] Figure 3 is a top view of a layout of a transistor fabricated on an SOI substrate consistent with an embodiment of the present disclosure. It should be understood that Figure 3 Can be used with the above Figure 1 and Figure 2 Designed and operated in a similar manner.

[0038] In some embodiments, transistor 300 may include a first dual gate region 302, a second dual gate region 306, and a region 304 between the first dual gate region 302 and the second dual gate region 306. For example, region 304 may be an active region between dual gate region 302 and dual gate region 306 (e.g., region 304 is outside dual gate region 302 and outside dual gate region 306). In some embodiments, active silicon layer 312 may be formed on an SOI substrate. A gate structure 308 including an insulator (e.g., an oxide layer) and an overlying gate material (e.g., polysilicon, a conductive material, etc.) may be at least partially formed over silicon layer 312 (e.g., gate structure 308 may at least partially overlying silicon layer 312). In some embodiments, silicon layer 312 may include one or more contacts 314. In some embodiments, P+ implant region 332, N+ implant region 334, and P+ implant region 336 may overlying silicon layer 312.

[0039] In some embodiments, the silicon layer 312 can be thin silicon resulting in improved switching performance. In some embodiments, an oxide layer can be disposed between the silicon layer 312 and the gate structure 308 overlay.

[0040] In some embodiments, the at least partial overlap of the silicon layer 312 and the gate structure 308 may include a first edge, a second edge, a third edge, and a fourth edge of the silicon layer 312 in the at least partial overlap of the gate structure 308. In some embodiments, the first portion of the oxide layer (e.g., Figure 2 The first portion of the oxide layer 142) may cover at least a portion of the first edge and the second edge of the silicon layer 312. In some embodiments, the first portion of the oxide layer may cover the entire silicon layer 312 in the dual gate region 302 (e.g., the first portion of the oxide layer may cover the silicon layer 312 in the dual gate region 302, wherein the gate structure 308 at least partially overlaps the silicon layer 312 and wherein the gate structure 308 does not overlap the silicon layer 312). In some embodiments, the first portion of the oxide layer, the first edge, and the portion of the gate structure 308 on the first edge may define an edge transistor 310. In some embodiments, the first portion of the oxide layer, the second edge, and the portion of the gate structure 308 on the second edge may define an edge transistor 311.

[0041] In some embodiments, the oxide layer may include a third portion similar to the first portion (e.g., Figure 2 312 ), which may cover at least a portion of a third edge and a fourth edge of the silicon layer 312. In some embodiments, the third portion of the oxide layer may cover the entire silicon layer 312 in the dual gate region 306 (e.g., the third portion of the oxide layer may cover the silicon layer 312 in the dual gate region 306, wherein the gate structure 308 at least partially overlaps the silicon layer 312 and wherein the gate structure 308 does not overlap the silicon layer 312). In some embodiments, the third portion of the oxide layer, the third edge of the silicon layer 312, and the portion of the gate structure 308 on the third edge of the silicon layer 312 may define an edge transistor 320. In some embodiments, the fourth portion of the oxide layer, the fourth edge of the silicon layer 312, and the portion of the gate structure 308 on the fourth edge of the silicon layer 312 may define an edge transistor 321. That is, for purposes of the present disclosure, edge transistors 310, 311, 320, and 321 may be formed by Figure 3 Indicated by bold lines.

[0042] To increase the threshold voltage of the transistor and reduce the current leakage of the transistor, the first portion of the oxide layer in the dual gate regions 302 and 306 may be thicker than the second portion of the oxide layer in the active region 304 (eg, Figure 2The first portion of the oxide layer may be thicker in the dual gate regions 302 and 306 because each dual gate region may include an edge of the silicon layer 312 that is more susceptible to current leakage, as described above. Since higher conduction may be required in the active region and there is a reduced drive current in the active region, the second portion of the oxide layer may be thinner in the active region. In some embodiments, the second portion of the oxide layer may cover at least a portion of the silicon layer 312 in at least a portion of the gate structure 308. In some embodiments, the second portion of the oxide layer may cover the entire silicon layer 312 in region 304.

[0043] The first portion of the oxide layer in the dual gate regions 302 and 306 may also increase the tip of the silicon layer 312 formed in the edge of the silicon layer 312 (eg, Figure 2 The first portion of the oxide layer may be formed on the tip of the silicon layer 312 so that the tip 322 is more robust to oxide breakdown and reduces current leakage at the tip. Therefore, the first portion of the oxide layer may be configured to reduce current leakage in the edge transistors 310, 311, 320, and 321 of the transistor. For example, the threshold voltage of each of the edge transistors 310, 311, 320, and 321 may be increased to be greater than 0V. In some embodiments, the threshold voltage of each of the edge transistors 310, 311, 320, and 321 may be increased so that they are greater than the threshold voltage of the edge transistors 310, 311, 320, and 321 with a thinner oxide layer (e.g., the threshold voltage of the edge transistors 310, 311, 320, and 321 with a thicker oxide layer is greater than that with a thinner oxide layer).

[0044] In some embodiments, gate structure 308 can be modified to increase or "widen" the effective channel length of edge transistors 310, 311, 320, and 321 relative to the length of the central conduction channel of transistor 300 (e.g., gate structure 308 can be widened in dual gate region 302 and dual gate region 306). The increased edge transistor channel length results in a further reduction in leakage current. While the widened shape of gate structure 308 increases its capacitance, thereby reducing logic speed, the thick portion of the oxide layer below the widened portion of gate structure 308 reduces the capacitance of gate structure 308, thereby increasing logic speed.

[0045] In some embodiments, silicon layer 312 may be bulk connected (eg, rather than Figure 1 The device may also be a floating body such as a silicon layer 112 of the embodiment of the present invention, wherein the silicon layer 312 includes a narrow neck shape (e.g., a body connection) 312a to reduce the amount of active silicon on the device, thereby minimizing or reducing wasted area or capacitance overhead.

[0046] In some SOI processes, the device may have the same well for both the thin oxide region and the thick oxide region, but may have different LDD and halo dopings for the thin oxide region and the thick oxide region. In some embodiments consistent with the present disclosure, different wells may be used for the thin oxide region and the thick oxide region, but the same LDD and halo dopings may be used for the thin oxide region and the thick oxide region. Since the well doping of the thin oxide region is much higher than that of the thick oxide region, the thick oxide region will have a higher threshold voltage in the edge region to reduce current leakage.

[0047] Embodiments in which the same LDD and halo dopings are formed in the thin oxide region and the thick oxide region may be advantageous because the only major process adjustment is to adjust the oxide thickness. These embodiments may also be advantageous because they avoid misalignment that can sometimes occur when different LDD and halo dopings are formed in the thin oxide region and the thick oxide region.

[0048] Figure 4 A flowchart showing an exemplary method 400 of forming a transistor on an SOI substrate consistent with embodiments of the present disclosure is shown.

[0049] In step 401, a silicon layer (e.g., Figure 1 silicon layer 112 of Figure 2 silicon layer 112 of Figure 3 silicon layer 312 of Figure 3 silicon layer 312 of Figure 1 silicon layer 112 of Figure 3 body-connected 312a of

[0050] In step 403, an oxide layer may be provided. In some embodiments, the oxide layer may be disposed between at least partial overlap of the silicon layer and the gate structure. In some embodiments, the at least partial overlap may include a first region (e.g., Figure 1 double-gate region 102 of Figure 3 double-gate region 302 of Figure 1 region 104 of Figure 3 region 304 of Figure 2 first part 142 of Figure 2The second part 144). In some embodiments, the first part of the oxide layer may be in the first region, and the second part of the oxide layer may be in the second region. In some embodiments, the first part of the oxide layer may be thicker than the second part of the oxide layer. In some embodiments, the first part of the oxide layer may cover at least a portion of at least one of the first edge and / or the second edge of the silicon layer in the stack. In some embodiments, the first part of the oxide layer, the first edge of the silicon layer, and the gate structure on the first edge may define a first edge transistor (e.g., Figure 1 edge transistor 110 or 120 of Figure 3 edge transistor 310, 311, 320 or 321 of Figure 1 edge transistor 110 or 120 of Figure 3 edge transistor 310, 311, 320 or 321 of

[0051] In some embodiments, the first part of the oxide layer may cover the entire silicon layer in the first region (e.g., the first part of the oxide layer may cover the silicon layer in the double-gate region, where the gate structure at least partially overlaps the silicon layer and where the gate structure does not overlap the silicon layer). In some embodiments, the oxide layer may include a third part similar to the first part, which may cover at least a portion of the third and fourth edges of the silicon layer. In some embodiments, the third part of the oxide layer may cover the entire silicon layer in the third region (e.g., the third part of the oxide layer may cover the silicon layer in the double-gate region, where the gate structure at least partially overlaps the silicon layer and where the gate structure does not overlap the silicon layer). In some embodiments, the third part of the oxide layer, the third and / or fourth edges of the silicon layer, and the portion of the gate structure on the third and / or fourth edges of the silicon layer may define one or more edge transistors (e.g., Figure 3 edge transistor 310, 311, 320 or 321 of

[0052] To increase the threshold voltage and reduce current leakage of the transistor, the first and third parts of the oxide layer in the double-gate region may be thicker than the second part of the oxide layer in the active region. The first and third parts of the oxide layer may be thicker in the double-gate region because each double-gate region may include edges of the silicon layer that are more vulnerable to current leakage, as described above. Since higher conduction may be required in the active region and there is no driving current in the active region, the second part of the oxide layer may be thinner in the active region. In some embodiments, the second part of the oxide layer may cover at least a portion of the silicon layer that is at least partially overlapped by the gate structure. In some embodiments, the second part of the oxide layer may cover the entire silicon layer in the active region.

[0053] The first and third portions of the oxide layer in the dual-gate regions can also increase the threshold voltage in the tips of the silicon layer formed at the edges of the silicon layer (e.g., Figure 2 tips 122a or 122c). That is, the first and third portions of the oxide layer can be formed on the tips of the silicon layer, such that the tips are more robust to oxide breakdown and current leakage at the tips is reduced. Accordingly, the first portion of the oxide layer can be configured to reduce current leakage in the edge transistors of the transistor. For example, the threshold voltage of the edge transistors can be increased to greater than 0V. In some embodiments, the threshold voltage of the edge transistors can be increased such that they are greater than the threshold voltage of edge transistors with a thinner oxide layer (e.g., the threshold voltages of edge transistors 110 and 120 at the first portion 142 and the third portion 146 are greater than those of edge transistors with an oxide layer thinner than the first portion 142 and the third portion 146).

[0054] At step 405, a gate structure (e.g., Figure 1 gate structure 108 or Figure 3 gate structure 308) that at least partially overlaps the silicon layer can be provided. In some embodiments, the gate structure (e.g., Figure 3 gate structure 308) can be modified to increase or "extend" the effective channel length of the edge transistors (e.g., Figure 3 edge transistors 310, 311, 320, and 321) relative to the length of the central conduction channel of the transistor (e.g., the gate structure 308 can be widened in the dual-gate regions 302 and 306). The increased edge transistor channel length results in a further reduction in leakage current. When the widened shape of the gate structure increases its capacitance, thereby reducing the logic speed, the thick portion of the oxide layer under the widened portion of the gate structure reduces the capacitance of the gate structure, thereby increasing the logic speed.

[0055] Embodiments can be further described using the following clauses:

[0056] 1. A device on a silicon-on-insulator substrate, comprising:

[0057] A silicon layer;

[0058] A gate structure that at least partially overlaps the silicon layer; and

[0059] An oxide layer disposed between the silicon layer and the partially overlapping portion of the gate structure, wherein:

[0060] The oxide layer includes a first portion and a second portion;

[0061] The first portion of the oxide layer is thicker than the second portion of the oxide layer; and

[0062] The first part of the oxide layer covers at least a portion of the first edge of the silicon layer in the partial overlap.

[0063] 2. The device according to clause 1, wherein the first part of the oxide layer covers the entire first edge of the silicon layer.

[0064] 3. The device according to any one of clauses 1 to 2, wherein the gate structure is widened.

[0065] 4. The device according to any one of clauses 1 to 3, wherein the thickness of the silicon layer below the first part of the oxide layer is less than the thickness of the silicon layer below the second part of the oxide layer.

[0066] 5. The device according to any one of clauses 1 to 4, wherein the second part of the oxide layer is in the active region.

[0067] 6. The device according to any one of clauses 1 to 5, wherein the first part of the oxide layer, the first edge of the silicon layer, and the gate structure on the first edge define a first-edge transistor.

[0068] 7. The device according to clause 6, wherein the first-edge transistor includes a threshold voltage greater than zero volts.

[0069] 8. The device according to clause 6, wherein the first-edge transistor includes a threshold voltage greater than the threshold voltage of a transistor having an oxide layer thickness less than the thickness of the first part of the oxide layer.

[0070] 9. The device according to any one of clauses 1 to 8, wherein the first part of the oxide layer is in a first double-gate region.

[0071] 10. The device according to clause 9, wherein:

[0072] The oxide layer includes a third part,

[0073] The third part of the oxide layer covers at least a portion of the second edge of the silicon layer in the partial overlap, and

[0074] The third part of the oxide layer, the second edge of the silicon layer, and the gate structure on the second edge define a second-edge transistor.

[0075] 11. The device according to clause 10, wherein the thickness of the silicon layer below the third part of the oxide layer is less than the thickness of the silicon layer below the second part of the oxide layer.

[0076] 12. The device of any of clauses 10 to 11, wherein the third portion of the oxide layer covers the entirety of the second edge of the silicon layer.

[0077] 13. The device of any of clauses 10 to 12, wherein the third portion of the oxide layer is thicker than the second portion of the oxide layer.

[0078] 14. The device of any of clauses 10 to 13, wherein the third portion of the oxide layer is located in a second dual gate region.

[0079] 15. The device of clause 14, wherein the second portion of the oxide layer is outside the first dual gate region and outside the second dual gate region.

[0080] 16. The device of any of clauses 10 to 15, the second portion of the oxide layer being located between the first portion of the oxide layer and the third portion of the oxide layer.

[0081] 17. A method for forming a device on a silicon-on-insulator substrate, comprising:

[0082] providing a silicon layer;

[0083] providing an oxide layer; and

[0084] A gate structure is provided, at least partially overlapping the silicon layer, wherein:

[0085] The oxide layer is disposed between the silicon layer and the partially overlapping gate structure;

[0086] The oxide layer includes a first portion and a second portion;

[0087] The first portion of the oxide layer is thicker than the second portion of the oxide layer; and

[0088] The first portion of the oxide layer covers at least a portion of a first edge of the silicon layer in the partial overlap.

[0089] 18. The method of clause 17, wherein the first portion of the oxide layer covers the entirety of the first edge of the silicon layer.

[0090] 19. The method according to any of clauses 17 to 18, wherein the gate structure is widened.

[0091] 20. The method of any of clauses 17 to 19, wherein a thickness of the silicon layer beneath the first portion of the oxide layer is less than a thickness of the silicon layer beneath the second portion of the oxide layer.

[0092] 21. The method of any of clauses 17 to 20, wherein the second portion of the oxide layer is in an active area.

[0093] 22. The method of any of clauses 17 to 21, wherein the first portion of the oxide layer, the first edge of the silicon layer, and the gate structure on the first edge define a first edge transistor.

[0094] 23. The method of clause 22, wherein the first edge transistor comprises a threshold voltage greater than zero volts.

[0095] 24. The method of clause 22, wherein the first edge transistor comprises a threshold voltage greater than a threshold voltage of a transistor having an oxide layer thickness less than a thickness of the first portion of the oxide layer.

[0096] 25. A silicon-on-insulator substrate, comprising:

[0097] Silicon layer;

[0098] an oxide layer for receiving a portion of a gate structure, wherein:

[0099] The oxide layer includes a first portion and a second portion;

[0100] The first portion of the oxide layer is thicker than the second portion of the oxide layer; and

[0101] The first portion of the oxide layer covers at least a portion of a first edge of the silicon layer.

[0102] 26. A device on a silicon-on-insulator substrate, comprising:

[0103] Silicon islands formed in the silicon layer;

[0104] forming a first gate structure in an active region on the silicon island, the first gate structure comprising a first gate oxide layer having a first gate oxide layer thickness; and

[0105] a second gate structure and a third gate structure, each of the second gate structure and the third gate structure being formed over an edge of the silicon island and each extending from the first gate structure, the second gate structure including a second gate oxide layer having a second gate oxide layer thickness, and the third gate structure including a third gate oxide layer having a third gate oxide layer thickness,

[0106] The first gate oxide layer thickness is smaller than the second gate oxide layer thickness and smaller than the third gate oxide layer thickness.

[0107] 27. A method of forming a device on a silicon-on-insulator substrate, comprising:

[0108] providing a silicon layer;

[0109] providing an active region in the silicon layer;

[0110] providing a first gate oxide layer over at least a portion of a central region of the active area;

[0111] providing a second gate oxide layer over at least one edge of the active area;

[0112] providing a conductive gate material over the first gate oxide layer and the second gate oxide layer; and

[0113] A gate structure overlapping the active area is formed in the silicon layer, wherein:

[0114] The gate structure extends across the active region, covering at least two edges and the at least a portion of the central region; and

[0115] The first gate oxide layer is thinner than the second gate oxide layer.

[0116] It will be appreciated that the embodiments of the present disclosure are not limited to the exact constructions that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof.

[0117] Manufacturing Techniques and Options

[0118] As used in this disclosure, the term "MOSFET" includes any field effect transistor (FET) having an insulated gate whose voltage determines the conductivity of the transistor, and encompasses insulated gates having metal or metalloid, insulator, and / or semiconductor structures. The terms "metal" or "metalloid" include at least one conductive material (e.g., aluminum, copper or other metal, or highly doped polysilicon, graphene or other electrical conductors), "insulator" includes at least one insulating material (e.g., silicon oxide or other dielectric material), and "semiconductor" includes at least one semiconductor material.

[0119] As used in this disclosure, the term "radio frequency" (RF) refers to oscillation rates in the range of about 3 kHz to about 300 GHz. The term also includes frequencies used in wireless communication systems. RF frequencies can be the frequency of electromagnetic waves or alternating voltages or currents in electrical circuits.

[0120] With respect to the drawings cited in this disclosure, the dimensions of the various elements are not drawn to scale; some dimensions are greatly exaggerated vertically and / or horizontally for clarity or emphasis. In addition, references to orientations and directions (e.g., "top," "bottom," "above," "below," "lateral," "vertical," "horizontal," etc.) are relative to the exemplary drawings and are not necessarily absolute orientations or directions.

[0121] Various embodiments of the present invention can be implemented to meet a variety of specifications. Unless otherwise specified above, the selection of suitable component values ​​is a matter of design choice. Various embodiments of the present invention can be implemented in any suitable integrated circuit (IC) technology (including but not limited to MOSFET structure), or in hybrid or discrete circuit form. Integrated circuit implementation can be manufactured using any suitable substrate and process, including but not limited to standard bulk silicon, high resistivity bulk CMOS, silicon on insulator (SOI) and silicon on sapphire (SOS). Unless otherwise specified above, embodiments of the present invention can be implemented in other transistor technologies, such as bipolar, BiCMOS, LDMOS, BCD, GaAs HBT, GaN HEMT, GaAs pHEMT and MESFET technology. However, when manufactured using SOI or SOS-based processes, or when manufactured with processes having similar characteristics, embodiments of the present invention are particularly useful. Fabrication in CMOS using SOI or SOS processes enables circuits to have low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity and high frequency operation (i.e., radio frequency reaches and exceeds 300GHz). Monolithic IC implementations are particularly useful because parasitic capacitances can usually be kept low (or at a minimum, or uniform across all cells, allowing them to be compensated for) by careful design.

[0122] Depending on the particular specifications and / or implementation technology (e.g., NMOS, PMOS, or CMOS, and enhancement mode or depletion mode transistor devices), voltage levels may be adjusted, and / or voltage and / or logic signal polarity may be inverted. Component voltage, current, and power handling capabilities may be adapted as needed, for example, by adjusting device size, "stacking" components (particularly FETs) in series to withstand greater voltages, and / or using multiple components in parallel to handle greater currents. Additional circuit components may be added to enhance the capabilities of the disclosed circuits and / or to provide additional functionality without significantly changing the functionality of the disclosed circuits.

[0123] Circuits and devices according to the present invention can be used alone or in combination with other components, circuits and devices. Embodiments of the present invention can be manufactured as integrated circuits (ICs), which can be packaged in IC packages and / or modules for ease of processing, manufacturing and / or improved performance. In particular, IC embodiments of the present invention are often used in modules, in which one or more such ICs are combined with other circuit components or blocks (e.g., filters, amplifiers, passive components and possible additional ICs) into a package. Then, the IC and / or module are usually combined with other components, usually on a printed circuit board, to form a part of a final product (e.g., a cellular phone, a laptop computer or an electronic tablet), or to form a more advanced module that can be used in a variety of products (e.g., vehicles, test equipment, medical equipment, etc.). Through various configurations of modules and components, such ICs generally implement communication modes, typically wireless communications.

[0124] Programming Implementation

[0125] Some or all aspects of the present invention may be implemented in hardware or software or a combination of the two (e.g., a programmable logic array). Unless otherwise specified, the methods included as part of the present invention are not inherently related to any particular computer or other device. In particular, various general-purpose computers may be used with programs written according to the teachings of this article, or it may be more convenient to use a special-purpose computer or special-purpose hardware (e.g., an integrated circuit) to perform a specific function. Therefore, embodiments of the present invention may be implemented in one or more computer programs (i.e., a set of instructions or codes) executed on one or more programming or programmable computer systems (which may have various architectures, such as distributed, client / server, or grid), each computer system including at least one processor, at least one data storage system (which may include volatile and non-volatile memory and / or storage elements), at least one input device or port, and at least one output device or port. Program instructions or codes are applied to input data to perform the functions described herein and generate output information. Output information is applied to one or more output devices in a known manner.

[0126] Each such computer program can be implemented in any desired computer language (including machine language, assembly language or high-level process language, logical language, object-oriented programming language or custom language / script) to communicate with a computer system, and can be implemented in a distributed manner, wherein the different parts of the calculation specified by the software are performed by different processors. In any case, the computer language can be a compiled or interpreted language. The computer programs that implement some or all of the present invention can form one or more modules of a larger program or program system. Some or all elements of a computer program can be implemented as a data structure stored in a computer-readable medium or data that conforms to other organizations of the data model stored in a data repository.

[0127] Each such computer program may be stored on or downloaded (e.g., by encoding in a propagating signal and delivering via a communications medium (e.g., a network)) to a tangible, non-transitory storage medium or device (e.g., a solid-state storage medium or device, or a magnetic or optical medium) for a period of time (e.g., a dynamic memory device (e.g., dynamic RAM), or the time between semi-permanent or permanent refresh cycles) that is readable by a general or special purpose programmable computer for configuring and operating the computer when the computer system reads the storage medium or device to perform the above-described processes. The system of the present invention may also be considered to be implemented as a non-transitory computer-readable storage medium configured with a computer program, wherein the storage medium so configured causes the computer system to operate in a specific or predefined manner to perform the above-described functions.

Claims

1. A device on a silicon-on-insulator substrate, comprising: a silicon layer; a gate structure that at least partially overlaps the silicon layer; and an oxide layer disposed between the silicon layer and the partial overlap of the gate structure, wherein: the oxide layer includes a first portion and a second portion; the first portion of the oxide layer is thicker than the second portion of the oxide layer; and the first portion of the oxide layer covers at least a portion of a first edge of the silicon layer in the partial overlap.

2. The device according to claim 1, wherein, the first portion of the oxide layer covers the entire first edge of the silicon layer.

3. The device according to any one of claims 1 to 2, wherein, the gate structure is widened.

4. The device according to any one of claims 1 to 3, wherein, the thickness of the silicon layer below the first portion of the oxide layer is less than the thickness of the silicon layer below the second portion of the oxide layer.

5. The device according to any one of claims 1 to 4, wherein, the second portion of the oxide layer is in the active region.

6. The device according to any one of claims 1 to 5, wherein, the first portion of the oxide layer, the first edge of the silicon layer, and the gate structure on the first edge define a first edge transistor.

7. The device according to claim 6, wherein, the first edge transistor includes a threshold voltage greater than zero volts.

8. The device according to claim 6, wherein, the first edge transistor includes a threshold voltage greater than the threshold voltage of a transistor having an oxide layer thickness less than the thickness of the first portion of the oxide layer.

9. The device according to any one of claims 1 to 8, wherein, the first portion of the oxide layer is located in a first double-gate region.

10. The device according to claim 9, wherein: the oxide layer includes a third portion, the third portion of the oxide layer covers at least a portion of a second edge of the silicon layer in the partial overlap, and the third portion of the oxide layer, the second edge of the silicon layer, and the gate structure on the second edge define a second edge transistor.

11. The device according to claim 10, wherein, the thickness of the silicon layer below the third portion of the oxide layer is less than the thickness of the silicon layer below the second portion of the oxide layer.

12. The device according to any one of claims 10 to 11, wherein, the third portion of the oxide layer covers the entire second edge of the silicon layer.

13. The device according to any one of claims 10 to 12, wherein, the third portion of the oxide layer is thicker than the second portion of the oxide layer.

14. The device according to any one of claims 10 to 13, wherein, the third portion of the oxide layer is located in a second double-gate region.

15. The device according to claim 14, wherein, the second portion of the oxide layer is outside the first double-gate region and outside the second double-gate region.

16. The device according to any one of claims 10 to 15, wherein the second part of the oxide layer is located between the first part of the oxide layer and the third part of the oxide layer.

17. A method of forming a device on a silicon-on-insulator substrate, comprising: providing a silicon layer; providing an oxide layer; and providing a gate structure that at least partially overlaps the silicon layer, wherein: the oxide layer is disposed between the silicon layer and the partially overlapping portion of the gate structure; the oxide layer includes a first part and a second part; the first part of the oxide layer is thicker than the second part of the oxide layer; and the first part of the oxide layer covers at least a portion of a first edge of the silicon layer in the partially overlapping portion.

18. The method according to claim 17, wherein the first part of the oxide layer covers the entire first edge of the silicon layer.

19. The method according to any one of claims 17 to 18, wherein the gate structure is widened.

20. The method according to any one of claims 17 to 19, wherein the thickness of the silicon layer below the first part of the oxide layer is less than the thickness of the silicon layer below the second part of the oxide layer.

21. The method according to any one of claims 17 to 20, wherein the second part of the oxide layer is in an active region.

22. The method according to any one of claims 17 to 21, wherein the first part of the oxide layer, the first edge of the silicon layer, and the gate structure on the first edge define a first-edge transistor.

23. The method according to claim 22, wherein the first-edge transistor includes a threshold voltage greater than zero volts.

24. The method according to claim 22, wherein the first-edge transistor includes a threshold voltage greater than the threshold voltage of a transistor having an oxide layer thickness less than the thickness of the first part of the oxide layer.

25. A silicon-on-insulator substrate, comprising: a silicon layer; an oxide layer for receiving a portion of a gate structure, wherein: the oxide layer includes a first part and a second part; the first part of the oxide layer is thicker than the second part of the oxide layer; and the first part of the oxide layer covers at least a portion of a first edge of the silicon layer.

26. A device on a silicon-on-insulator substrate, comprising: a silicon island formed in a silicon layer; a first gate structure formed in an active region on the silicon island, the first gate structure including a first gate oxide layer having a first gate oxide layer thickness; and a second gate structure and a third gate structure, the second gate structure and the third gate structure each formed above an edge of the silicon island and each extending from the first gate structure, the second gate structure including a second gate oxide layer having a second gate oxide layer thickness, and the third gate structure including a third gate oxide layer having a third gate oxide layer thickness, wherein the first gate oxide layer thickness is less than the second gate oxide layer thickness and less than the third gate oxide layer thickness.

27. A method for forming a device on a silicon-on-insulator substrate, comprising: providing a silicon layer; providing an active region in the silicon layer; providing a first gate oxide layer over at least a portion of a central region of the active region; providing a second gate oxide layer over at least one edge of the active region; providing a conductive gate material over the first gate oxide layer and the second gate oxide layer; and forming a gate structure in the silicon layer that overlays the active region, wherein: the gate structure extends across the active region, covering at least two edges and the at least a portion of the central region; and the first gate oxide layer is thinner than the second gate oxide layer.

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