Processor verification method and device, electronic equipment and storage medium

Abstract

The invention provides a processor verification method and device, electronic equipment and a storage medium, and relates to the technical field of processors, and the method comprises the steps: obtaining first instruction information corresponding to a to-be-verified processor; determining second instruction information corresponding to the reference model based on the first instruction information; based on the first instruction information and the second instruction information, determining a verification result of the to-be-verified processor; the verification result is used for representing whether the instruction set architecture behavior in the tested processor conforms to the standard definition of the instruction set architecture or not. The instruction information of the to-be-verified processor and the instruction information of the reference model are compared with each other with the instruction as the granularity, so that errors of the processor in instruction execution and memory access operation can be accurately detected in the verification process, and the verification accuracy and efficiency of the to-be-verified processor are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of processors, and in particular, to a processor verification method, apparatus, electronic device, and storage medium. Background Art

[0002] Currently, the main methods for verifying a processor are to use a software-implemented instruction set function model as a reference model, and compare the register contents of each cycle at the cycle granularity to verify the correctness of the instruction stream and memory access stream.

[0003] However, the verification granularity of comparing register contents at the cycle granularity is relatively coarse, which reduces the error rate of the processor in instruction execution and memory access operations, and further reduces the accuracy of verifying the processor. Summary of the Invention

[0004] The present invention provides a processor verification method, apparatus, electronic device, and storage medium, which are used to solve the defect that the verification granularity of comparing register contents at the cycle granularity in the prior art is relatively coarse, reducing the error rate of the processor in instruction execution and memory access operations, and further reducing the accuracy and efficiency of verifying the processor. It realizes comparing the instruction information of the processor to be verified and the reference model at the instruction granularity, so that the verification process can accurately detect errors in the processor's instruction execution and memory access operations, and improve the accuracy and efficiency of verifying the processor to be verified.

[0005] The present invention provides a processor verification method, apparatus, electronic device, and storage medium, including: Obtain first instruction information corresponding to the processor to be verified; the first instruction information is used to represent the attribute information obtained after the processor to be verified executes a target instruction; Based on the first instruction information, determine second instruction information corresponding to the reference model; the types of the first instruction information and the second instruction information are the same; the second instruction information is used to represent the attribute information obtained after the reference model executes the target instruction; the instruction set architecture in the processor to be verified is established based on the instruction set architecture in the reference model; Based on the first instruction information and the second instruction information, determine the verification result of the processor to be verified; the verification result is used to represent whether the instruction set architecture behavior in the tested processor conforms to the specification definition of the instruction set architecture.

[0006] A processor verification method provided by the present invention, wherein the first instruction information is a first instruction stream, and the second instruction information is a second instruction stream; determining a verification result for the processor to be verified based on the first instruction information and the second instruction information includes: comparing a first content in the first instruction stream with a second content in the second instruction stream to obtain a first comparison result; the first content and the second content are of the same type; determining the verification result based on the first comparison result.

[0007] A processor verification method provided by the present invention, wherein the first instruction information is an out-of-order load memory access stream, and the second instruction information is a reference load memory access stream; determining a verification result for the processor to be verified based on the first instruction information and the second instruction information includes: reordering the out-of-order load memory access stream based on a reorder buffer pointer to obtain a reordered load memory access stream; inserting the reordered load memory access stream into an initial load reorder queue to obtain a second load reorder queue; determining the verification result based on the second load reorder queue and the reference load memory access stream.

[0008] A processor verification method provided by the present invention, wherein determining the verification result based on the second load reorder queue and the reference load memory access stream includes: obtaining a pipeline flush signal of the processor to be verified; the pipeline flush signal is used to represent a signal for clearing invalid instructions; based on the pipeline flush signal, deleting load memory access stream entries in the second load reorder queue that are on an incorrect instruction path to obtain a third load reorder queue; dequeuing and comparing a first head-of-queue entry in the third load reorder queue with a second head-of-queue entry in the reference load memory access stream to obtain a second comparison result; in the case where the second comparison result indicates that the first head-of-queue entry and the second head-of-queue entry are inconsistent, determining that the instruction set architecture in the processor to be verified does not conform to the specification definition of the instruction set architecture in the reference model.

[0009] A processor verification method provided by the present invention, wherein the first instruction information is a sequential store memory access stream, and the second instruction information is a reference store memory access stream; determining a verification result for the processor to be verified based on the first instruction information and the second instruction information includes: inserting the sequential store memory access stream at the end of an initial measured store queue to obtain a second measured store queue; inserting the reference store memory access stream at the end of an initial reference store queue to obtain a second reference store queue; dequeuing and comparing a third head-of-queue entry in the second measured store queue with a fourth head-of-queue entry in the second reference store queue to obtain a third comparison result; determining the verification result based on the third comparison result.

[0010] A processor verification method provided by the present invention, determining second instruction information corresponding to a reference model based on the first instruction information includes: determining a target instruction executed by the processor to be verified based on the first instruction information; invoking the reference model to execute the target instruction to obtain the second instruction information.

[0011] A processor verification method provided by the present invention, before obtaining the first instruction information corresponding to the processor to be verified, the method further includes: obtaining configuration information of the processor to be verified; adjusting the configuration information in the initial model based on the configuration information to obtain the reference model.

[0012] The present invention also provides a processor verification device, including the following modules: An acquisition module, configured to acquire first instruction information corresponding to a processor to be verified; the first instruction information is used to characterize the attribute information obtained after the processor to be verified executes a target instruction; A second instruction information determination module, configured to determine second instruction information corresponding to a reference model based on the first instruction information; the first instruction information and the second instruction information are of the same type; the second instruction information is used to characterize the attribute information obtained after the reference model executes the target instruction; the processor to be verified and the reference model are established based on the specification definition of the same instruction set architecture; A verification result determination module, configured to determine a verification result of the processor to be verified based on the first instruction information and the second instruction information; the verification result is used to characterize whether the instruction set architecture behavior in the processor to be verified conforms to the specification definition of the instruction set architecture.

[0013] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor, where when the processor executes the computer program, the processor verification method as described in any one of the above is implemented.

[0014] The present invention also provides a non-transitory computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the processor verification method as described in any one of the above is implemented.

[0015] The present invention also provides a computer program product, including a computer program, and when the computer program is executed by a processor, the processor verification method as described in any one of the above is implemented.

[0016] The processor verification method, device, electronic device, and storage medium provided by the present invention obtain first instruction information corresponding to a processor to be verified. The first instruction information is used to represent the attribute information obtained after the processor to be verified executes a target instruction; second instruction information is used to represent the attribute information obtained after a reference model executes the target instruction; based on the first instruction information, determine the second instruction information corresponding to the reference model; the types of the first instruction information and the second instruction information are the same; the second instruction information is used to represent the attribute information obtained after the reference model executes the target instruction; the processor to be verified and the reference model are established based on the specification definition of the same instruction set architecture; based on the first instruction information and the second instruction information, determine the verification result of the processor to be verified; the verification result is used to represent whether the instruction set architecture in the processor to be verified conforms to the specification definition of the instruction set architecture in the reference model. In this way, by comparing the instruction information of the processor to be verified and the reference model at the instruction granularity, the verification process can accurately detect errors in the instruction execution and memory access operations of the processor, improving the accuracy and efficiency of verifying the processor to be verified. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] To more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for the descriptions of the embodiments or the prior art. Obviously, the drawings in the following descriptions are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0018] Figure 1 is a flowchart of the processor verification method provided by the present invention.

[0019] Figure 2 is a structural diagram of the processor verification system provided by the present invention.

[0020] Figure 3 is a structural diagram of the processor verification device provided by the present invention.

[0021] Figure 4 is a structural diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0022] To make the objectives, technical solutions, and advantages of the present invention clearer, the following clearly and completely describes the technical solutions in the present invention with reference to the drawings in the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0023] At present, in addition to the lack of precision in verification due to coarse granularity, the traditional processor system-level verification method also lacks flexible configurability. Usually, a set of verification logic codes and reference models are only applicable to a specific processor architecture under test. When the behavior of the processor architecture under test changes, the verification logic and reference model need to be manually adjusted, which is cumbersome and inefficient. With the introduction of agile hardware design languages, the configurability of processors has been significantly improved, making the deficiencies of traditional processor system verification methods in terms of flexibility more obvious.

[0024] Based on the above problems, the present invention proposes a processor verification method, which compares the instruction information of the processor to be verified and the reference model at the instruction granularity, enabling the verification process to accurately detect errors in the instruction execution and memory access operations of the processor, and improving the precision and efficiency of verifying the processor to be verified.

[0025] The following combines Figures 1 - 3 to describe the processor verification method of the present invention. This method is applicable to the verification of any processor. The execution subject of this method can be an electronic device or a processor verification method set in the electronic device. The processor verification device can be implemented by software, hardware, or a combination of both.

[0026] Figure 1 is one of the flow diagrams of the processor verification method provided by the present invention. As Figure 1 shown, this method includes the following: Step 101, obtain the first instruction information corresponding to the processor to be verified.

[0027] Among them, the first instruction information is used to characterize the attribute information obtained after the processor to be verified executes the target instruction.

[0028] Here, the processor architecture to be verified includes but is not limited to processors with RISC-V architecture, ARM architecture, etc.

[0029] Here, the first instruction information can include but is not limited to instruction stream, load memory access stream, store memory access stream, etc.

[0030] Here, the processor to be verified can be a processor model implemented based on a software programming language or a processor model implemented based on a hardware description language.

[0031] Here, the first instruction information can be obtained through the signals sent by the processor to be verified or directly obtained from the processor to be verified.

[0032] Step 102, determine the second instruction information corresponding to the reference model based on the first instruction information.

[0033] Among them, the types of the first instruction information and the second instruction information are the same; the second instruction information is used to represent the attribute information obtained after the reference model executes the target instruction; the processor to be verified and the reference model are established based on the specification definition of the same instruction set architecture. Here, the reference model is an instruction set function model implemented by software, such as the RISC-V instruction set, the ARM instruction set, etc.

[0034] It should be noted that the instruction set architecture in the reference model conforms to the specification definition, while it is uncertain whether the instruction set architecture in the processor to be verified conforms to the specification definition. Therefore, it is necessary to use the reference model to verify the processor.

[0035] Here, the second instruction information includes, but is not limited to, instruction stream, load memory access stream, store memory access stream, etc. For example, after the instruction stream comparison module receives the first instruction stream of the processor to be verified, it calls the reference model to execute an instruction, and the reference model returns the second instruction stream of the instruction after execution. The instruction stream comparison module compares the first instruction stream and the second instruction stream.

[0036] Step 103: Determine the verification result of the processor to be verified based on the first instruction information and the second instruction information.

[0037] Among them, the verification result is used to represent whether the instruction set architecture behavior in the processor under test conforms to the specification definition of the instruction set architecture.

[0038] It should be noted that the types of the first instruction information and the second instruction information are the same. For example, if the first instruction information is an instruction stream, the second instruction information is also an instruction stream; if the first instruction stream is a load memory access stream, the second instruction information is also a load memory access stream.

[0039] Here, when comparing the first instruction information and the second instruction information, if the two are inconsistent, it means that the verification result does not conform to the specification definition of the instruction set architecture; In the embodiment of the present invention, by obtaining the first instruction information corresponding to the processor to be verified; determining the second instruction information corresponding to the reference model based on the first instruction information; determining the verification result of the processor to be verified based on the first instruction information and the second instruction information; the verification result is used to represent whether the instruction set architecture behavior in the processor to be verified conforms to the specification definition of the instruction set architecture. In this way, the instruction information of the processor to be verified and the reference model is compared at the instruction granularity, so that the verification process can accurately detect errors in the instruction execution and memory access operations of the processor, and improve the accuracy and efficiency of verifying the processor to be verified.

[0040] Further, the first instruction information is a first instruction stream, and the second instruction information is a second instruction stream; determining a verification result for the processor to be verified based on the first instruction information and the second instruction information includes: comparing a first content in the first instruction stream with a second content in the second instruction stream to obtain a first comparison result; the first content and the second content are of the same type; determining the verification result based on the first comparison result.

[0041] Here, the first instruction stream and the second instruction stream can both include but are not limited to the current instruction storage address (Program Counter, PC), instruction physical address, instruction code, instruction write-back register number, instruction write-back value, register type written back by the instruction, etc.

[0042] Here, the first comparison result can be that the first instruction stream is consistent or inconsistent with the second instruction stream. If the first instruction stream is inconsistent with the second instruction stream, it indicates that the instruction set architecture behavior in the processor under test does not conform to the specification definition of the instruction set architecture in the reference model.

[0043] Specifically, when the first instruction information is a first instruction stream, the reference model is guided to execute the same number of instructions as the first instruction stream to obtain a second instruction stream. Then, the information in the first instruction stream and the second instruction stream is compared to obtain a first comparison result. When the first comparison result is incorrect, it is considered that the implementation of the processor to be verified is incorrect and does not conform to the specification definition of the instruction set architecture; when the second comparison result is correct, it is considered that the implementation of the processor to be verified is correct and conforms to the specification definition of the instruction set architecture. Among them, when any one of the current instruction PC, instruction physical address, instruction code, instruction write-back register number, instruction write-back value, and register type written back by the instruction in the first instruction information is inconsistent with that in the second instruction information, the verification result is determined to be incorrect.

[0044] In the embodiment of the present invention, by comparing the instruction stream of the processor to be verified with the instruction stream of the reference model, the verification process can accurately detect errors in the instruction execution and memory access operations of the processor, ensure that it conforms to the specification definition of the instruction set architecture, and further improve the accuracy and efficiency of verification.

[0045] Further, the first instruction information is an out-of-order load memory access stream, and the second instruction information is a reference load memory access stream; determining a verification result for the processor to be verified based on the first instruction information and the second instruction information includes: reordering the out-of-order load memory access stream based on the reorder buffer pointer to obtain a reordered load memory access stream; inserting the reordered load memory access stream into the initial load reorder queue to obtain a second load reorder queue; determining the verification result based on the second load reorder queue and the reference load memory access stream.

[0046] Here, both the out-of-order load memory access stream and the reference load memory access stream can include but are not limited to virtual addresses, physical addresses, memory access data, memory access sizes, etc. Among them, the load memory access operation is an operation where the processor reads data from the memory. When the processor executes a program, it often needs to load data from the memory into the register for processing. The memory access stream refers to a series of memory access operations generated by the processor during the execution of a program. These memory access operations are executed in the program order, forming a memory access stream.

[0047] Here, the out-of-order load memory access stream is obtained when the processor executes instructions out of order, and the execution order of the instructions may be different from the order specified by the program.

[0048] Here, the reorder buffer is a buffer used to temporarily store the results of out-of-order executed instructions. When an instruction is executed, its result is temporarily stored in the reorder buffer instead of being directly committed to the register or memory. Only when all the instructions before the position of the instruction in the reorder buffer have been committed, will its result be committed.

[0049] Here, an invalid instruction means that when the processor detects a branch prediction error, a load instruction out-of-order execution violation, an exception, or an interruption, it needs to clear (flush) all the instructions in the pipeline on the wrong path to ensure the correct execution of subsequent instructions.

[0050] Specifically, when the first instruction information is an out-of-order load memory access stream, first, according to the reorder buffer pointer, the out-of-order load memory access stream is reordered to obtain a reordered load memory access stream; second, the reordered load memory access stream is inserted into the initial load reorder queue to obtain a second load reorder queue; then, when a pipeline flush occurs in the processor to be verified, a pipeline flush signal is obtained; finally, according to the pipeline flush signal and the reference load memory access stream, the verification result is determined.

[0051] In the embodiments of the present invention, by reordering the out-of-order load memory access stream, the complexity brought by out-of-order execution is effectively handled, enabling the verification to handle complex execution paths in modern processors.

[0052] In another embodiment of the present invention, the first instruction information can directly be an in-order load memory access stream. There is no need to reorder the load memory access stream, and the verification result is directly determined by comparing the in-order load memory access stream and the reference load memory access stream.

[0053] Exemplarily, determining the verification result based on the second load reorder queue and the reference load memory access stream includes: obtaining a pipeline flush signal of the processor to be verified; the pipeline flush signal is used to represent a signal for clearing invalid instructions; based on the pipeline flush signal, deleting load memory access stream entries in the wrong instruction path in the second load reorder queue to obtain a third load reorder queue; dequeuing and comparing the first head entry in the third load reorder queue with the second head entry in the reference load memory access stream to obtain a second comparison result; in the case where the second comparison result is that the first head entry and the second head entry are inconsistent, determining that the instruction set architecture in the processor to be verified does not conform to the specification definition of the instruction set architecture in the reference model.

[0054] Here, the Load memory access stream entry is a type of memory access stream entry, which is specifically used to record and manage information of Load memory access operations. Among them, the memory access stream entry is a data structure in the processor used to record and manage information of each memory access operation in the memory access stream, including virtual address, physical address, memory access data, and memory access size.

[0055] It should be noted that the queue contains multiple elements, and each element can include a virtual address, a physical address, memory access data, and a memory access size. Here, the head entry of the queue can be understood as an element, including a virtual address, a physical address, memory access data, and a memory access size.

[0056] Here, the second comparison result can be that the first head entry is consistent or inconsistent with the second head entry. When any one of the first head entry (i.e., virtual address, physical address, memory access data, and memory access size) and the second head entry is inconsistent, it is determined that the instruction set architecture in the processor under test does not conform to the specification definition of the instruction set architecture in the reference model; otherwise, it is determined that the instruction set architecture in the processor under test conforms to the specification definition of the instruction set architecture in the reference model.

[0057] Specifically, after obtaining the pipeline flush signal, according to the pipeline flush signal, delete the load memory access stream entries in the wrong instruction path in the second load reorder queue to obtain a third load reorder queue, compare the first head entry in the third load reorder queue with the second head entry in the reference load memory access stream to obtain a second comparison result, and determine the verification result based on the second comparison result.

[0058] In the embodiment of the present invention, when a pipeline flush occurs in the processor to be verified, all Load memory access stream entries in the wrong instruction path in the Load reorder queue are correspondingly deleted, which improves the accuracy of the Load reorder queue, ensures that it conforms to the specification definition of the instruction set architecture, and further improves the accuracy and efficiency of verification.

[0059] Further, the first instruction information is a sequential memory access stream, and the second instruction information is a reference memory access stream; determining the verification result of the processor to be verified based on the first instruction information and the second instruction information includes: inserting the sequential memory access stream at the end of the initial memory queue under test to obtain a second memory queue under test; inserting the reference memory access stream at the end of the initial reference memory queue to obtain a second reference memory queue; dequeuing and comparing the third queue header entry of the second memory queue under test and the fourth queue header entry of the second reference memory queue to obtain a third comparison result; and determining the verification result based on the third comparison result.

[0060] Here, both the sequential memory access stream and the reference memory access stream may include, but are not limited to, virtual addresses, physical addresses, memory access data, memory access sizes, etc.

[0061] Here, the third comparison result may be that the third queue header entry and the fourth queue header entry are the same or different. If the third queue header entry and the fourth queue header entry are different, it indicates that the instruction set architecture in the processor under test does not conform to the specification definition of the instruction set architecture in the reference model; if they are the same, it indicates that the instruction set architecture behavior in the processor under test conforms to the specification definition of the instruction set architecture.

[0062] It should be noted that when both the second memory queue under test and the second reference memory queue are not empty, the third queue header entry and the fourth queue header entry are compared to verify the processor to be verified.

[0063] In the embodiments of the present invention, by comparing the Store memory access stream of the processor to be verified with the Store memory access stream of the reference model, the verification process can accurately detect errors in the instruction execution and memory access operations of the processor, ensure that it conforms to the specification definition of the instruction set architecture, and further improve the accuracy and efficiency of verification.

[0064] It should be noted that the present invention can use any one or more comparison results of the instruction stream, Load memory access stream, or Store memory access stream to verify the processing to be verified. For example, taking one as an example, when the instruction stream in the processor to be verified is consistent with that in the reference model, or when the Load memory access stream in the processor to be verified is consistent with that in the reference model, or when the Store memory access stream in the processor to be verified is consistent with that in the reference model, it is determined that the processor to be verified conforms to the specification definition of the instruction set architecture in the reference model; taking two as an example, when the Load memory access stream in the processor to be verified is consistent with that in the reference model and the Store memory access stream in the processor to be verified is consistent with that in the reference model, it is determined that the processor to be verified conforms to the specification definition of the instruction set architecture in the reference model; taking three as an example, when the Load memory access stream in the processor to be verified is consistent with that in the reference model, the Store memory access stream in the processor to be verified is consistent with that in the reference model, and the Store memory access stream in the processor to be verified is consistent with that in the reference model, it is determined that the processor to be verified conforms to the specification definition of the instruction set architecture in the reference model. The above are several embodiments for determining the verification result, and are not specifically limited.

[0065] Further, determining the second instruction information corresponding to the reference model based on the first instruction information includes: determining the target instruction executed by the processor to be verified based on the first instruction information; and calling the reference model to execute the target instruction to obtain the second instruction information.

[0066] Here, the target instruction refers to an instruction that the processor to be verified needs to execute or has executed, and the target instruction includes, but is not limited to, an instruction stream, a Load instruction, a Store instruction, etc.

[0067] In the embodiment of the present invention, after determining the target instruction of the processor to be verified according to the instruction information corresponding to the processor to be verified, the reference model is then guided to execute the target instruction to obtain the instruction information corresponding to the reference model, ensuring that the instruction information of the processor to be verified and the instruction information of the reference model are obtained for the same instruction, improving the accuracy of comparison, and further improving the precision and efficiency of verification.

[0068] Further, before obtaining the first instruction information corresponding to the processor to be verified, the method further includes: obtaining the configuration information of the processor to be verified; and adjusting the configuration information in the initial model based on the configuration information to obtain the reference model.

[0069] Here, the configuration information may include, but is not limited to, the supported instruction set architecture (such as RISC-V) extension, the supported instruction set architecture (such as RISC-V) privilege mode, the virtual address management unit configuration, the physical memory start address, the physical memory size, whether non-aligned memory access is supported, etc.

[0070] Specifically, before verifying the processor to be verified, obtain the configuration information of the processor to be verified, and guide the configuration information of the reference model according to the configuration information. It should be understood that the configuration information in the processor to be verified should be aligned with the configuration information in the reference model.

[0071] In another embodiment, the configuration information of the processor to be verified can also adjust the verification logic for instruction information during the verification process. It can be understood that if there is no configuration vector in the configuration information of the processor to be verified, there is no need to compare vectors during the verification process, and no configuration vector is required in the reference model either.

[0072] In the embodiments of the present invention, by obtaining the configuration information of the processor to be verified and configuring the configuration information of the reference model, it is possible to flexibly adapt to RISC-V processors with different configurations, achieve automatic alignment, reduce manual intervention, improve verification efficiency, and accelerate the processor development cycle and reduce development costs.

[0073] The following is an application scenario of a processor verification method provided by the embodiments of the present invention.

[0074] It should be noted that in this application scenario, the processor to be verified is a RISC-V processor, the reference model is an instruction set function model that conforms to the RISC-V specification definition, and the instruction information includes instruction stream, Load memory access stream, and Store memory access stream.

[0075] Figure 2 is a schematic structural diagram of a processor verification system provided by the present invention, as Figure 2 shown, the processor verification system 200 can execute the above-mentioned processor verification method, including: processor model 201, reference model 202, configuration information collection module 203, instruction stream comparison module 204, Load reorder queue 205, Load memory access stream comparison module 206, tested Store queue 207, Store memory access stream comparison module 208, reference Store queue 209. Among them, the processor verification process includes: (1) The configuration information collection module obtains the configuration information in the processor model 201 and adjusts the configuration information in the reference model 202 according to the configuration information. Among them, the configuration information includes but is not limited to supported RISC-V extensions, supported RISC-V privilege modes, virtual address management unit configuration, physical memory start address, physical memory size, whether non-aligned memory access is supported, etc.

[0076] (2) Every clock cycle, the processor model 201 sends the committed sequential instruction stream signal in its ROB to the instruction stream comparison module 204; the instruction stream comparison module 204 instructs the reference model 202 to execute the same number of instructions and obtains the instruction stream of the reference model; the instruction stream comparison module 204 compares the instruction stream information of the processor model 201 and the reference model 202. When the comparison is incorrect, it is considered that the implementation of the processor model 201 is incorrect and does not conform to the instruction set specification, and an error prompt is given and the simulation ends. Among them, the instruction stream information includes but is not limited to the current instruction PC, instruction physical address, instruction code, instruction write-back register number, instruction write-back value, instruction write-back register class, etc.

[0077] (3) Every clock cycle, the processor model 201 sends its speculative out-of-order Load memory access stream signal to the Load reorder queue 205; after collecting the Load memory access stream signal of the processor model 201, the Load reorder queue 205 reorders the Load memory access stream according to the order of its ROB pointer and inserts it into the Load reorder queue; when a pipeline flush occurs in the processor model 201, a pipeline flush signal is sent to the Load reorder queue 205, and the Load reorder queue 205 deletes all Load memory access stream entries in the incorrect instruction path in the Load reorder queue according to the pipeline flush signal; after the reference model 202 executes the same Load instruction, the Load memory access stream comparison module 206 obtains the Load memory access stream of the reference model 202, takes out the head entry of the Load reorder queue and compares it with the Load memory access stream of the reference model 202. When the comparison is incorrect, it is considered that the implementation of the processor model 201 is incorrect and does not conform to the instruction set specification, and an error prompt is given and the simulation ends. Among them, the Load memory access stream information includes: virtual address, physical address, memory access data, memory access size, etc.

[0078] (4) Every clock cycle, the processor model 201 sends the deterministic sequential Store memory access stream signal written to the next-level memory to the DUT Store queue 207; after collecting the Store memory access stream signal of the processor model 201, the DUT Store queue 207 inserts it at the end of the queue; after the reference model 202 executes the same Store instruction, the reference Store queue 209 obtains the Store memory access stream of the reference model 202 and inserts it at the end of the reference Store queue; when both the DUT Store queue 207 and the reference Store queue 209 are not empty, the Store memory access stream comparison module 208 takes out the head entries of both and compares them. When the comparison is incorrect, it is considered that the implementation of the processor model 201 is incorrect and does not conform to the instruction set specification, and an error prompt is given and the simulation ends. Among them, the Store memory access stream information includes: virtual address, physical address, memory access data, memory access size, etc.

[0079] In an embodiment of the present invention, first, by designing a configuration information collection module, it can flexibly adapt to RISC-V processors with different configurations, achieve automatic alignment, reduce manual intervention, and improve verification efficiency. Second, the introduction of the instruction stream comparison module and the memory access stream comparison module enables the verification process to accurately detect errors in the processor's instruction execution and memory access operations, ensuring compliance with the RISC-V specification. In addition, the design of the Load reordering queue effectively handles the complexity brought by out-of-order execution, enabling verification to handle complex execution paths in modern processors. Generally speaking, this invention significantly improves the automation level, flexibility, and efficiency of processor verification, and is of great significance for accelerating the processor development cycle and reducing development costs.

[0080] The processor verification device provided by the present invention will be described below. The processor verification device described below can be correspondingly referred to the processor verification method described above.

[0081] Figure 3 is a schematic structural diagram of the processor verification device provided by the present invention, as Figure 3 shown, the processor verification device 300 includes: An acquisition module 301, configured to acquire first instruction information corresponding to a processor to be verified; the first instruction information is used to characterize the attribute information obtained after the processor to be verified executes a target instruction; A second instruction information determination module 302, configured to determine second instruction information corresponding to a reference model based on the first instruction information; the first instruction information and the second instruction information are of the same type; the second instruction information is used to characterize the attribute information obtained after the reference model executes the target instruction; the instruction set architecture behavior in the processor to be verified is established based on the instruction set architecture; the reference model is established based on the specification definition of the instruction set architecture; A verification result determination module 303, configured to determine a verification result for the processor to be verified based on the first instruction information and the second instruction information; the verification result is used to characterize whether the instruction set architecture behavior in the processor to be verified conforms to the specification definition of the instruction set architecture.

[0082] In another embodiment, the first instruction information is a first instruction stream, and the second instruction information is a second instruction stream; the verification result determination module 303 is specifically configured to: compare a first content in the first instruction stream with a second content in the second instruction stream to obtain a first comparison result; the first content and the second content are of the same type; and determine the verification result based on the first comparison result.

[0083] In another embodiment, the first instruction information is an out-of-order load memory access stream, and the second instruction information is a reference load memory access stream; the verification result determination module 303 is further specifically configured to: reorder the out-of-order load memory access stream based on the reorder buffer pointer to obtain a reordered load memory access stream; insert the reordered load memory access stream into the initial load reorder queue to obtain a second load reorder queue; and determine the verification result based on the second load reorder queue and the reference load memory access stream.

[0084] In another embodiment, the verification result determination module 303 is further specifically configured to: obtain a pipeline flush signal of the processor to be verified; the pipeline flush signal is used to represent a signal for clearing invalid instructions; based on the pipeline flush signal, delete the load memory access stream entries in the error instruction path in the second load reorder queue to obtain a third load reorder queue; dequeue and compare the first head entry in the third load reorder queue with the second head entry in the reference load memory access stream to obtain a second comparison result; and when the second comparison result indicates that the first head entry and the second head entry are inconsistent, determine that the instruction set architecture behavior in the processor to be verified does not conform to the specification definition of the instruction set architecture.

[0085] In another embodiment, the first instruction information is an in-order store memory access stream, and the second instruction information is a reference store memory access stream; the verification result determination module 303 is further specifically configured to: determine the verification result for the processor to be verified based on the first instruction information and the second instruction information, including: insert the in-order store memory access stream at the end of the initial measured store queue to obtain a second measured store queue; insert the reference store memory access stream at the end of the initial reference store queue to obtain a second reference store queue; dequeue and compare the third queue head entry in the second measured store queue with the fourth queue head entry in the second reference store queue to obtain a third comparison result; and determine the verification result based on the third comparison result.

[0086] In another embodiment, the second instruction information determination module 302 is specifically configured to: determine a target instruction executed by the processor to be verified based on the first instruction information; and call the reference model to execute the target instruction to obtain the second instruction information.

[0087] In another embodiment, before obtaining the first instruction information corresponding to the processor to be verified, the processor verification apparatus 300 further includes a configuration module, which is specifically configured to: obtain configuration information of the processor to be verified; and adjust the configuration information in the initial model based on the configuration information to obtain the reference model.

[0088] Figure 4The structural schematic diagram of the electronic device provided by the present invention is as follows Figure 4 As shown, the electronic device may include: a processor 410, a communications interface 420, a memory 430, and a communication bus 440. Among them, the processor 410, the communications interface 420, and the memory 430 complete communication with each other through the communication bus 440. The processor 410 may call the logical instructions in the memory 430 to execute the processor verification method, and the method includes: obtaining first instruction information corresponding to the processor to be verified; the first instruction information is used to characterize the attribute information obtained after the processor to be verified executes the target instruction; based on the first instruction information, determining second instruction information corresponding to the reference model; the types of the first instruction information and the second instruction information are the same; the second instruction information is used to characterize the attribute information obtained after the reference model executes the target instruction; the processor to be verified and the reference model are established based on the specification definition of the same instruction set architecture; based on the first instruction information and the second instruction information, determining the verification result of the processor to be verified; the verification result is used to characterize whether the instruction set architecture behavior in the processor to be verified conforms to the specification definition of the instruction set architecture.

[0089] In addition, when the logical instructions in the above-mentioned memory 430 can be implemented in the form of software functional units and sold or used as an independent product, they can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present invention. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), magnetic disks, or optical discs that can store program codes.

[0090] On the other hand, the present invention also provides a computer program product, which includes a computer program. The computer program can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the processor verification method provided by each of the above methods. The method includes: obtaining first instruction information corresponding to the processor to be verified; the first instruction information is used to represent the attribute information obtained after the processor to be verified executes a target instruction; based on the first instruction information, determining second instruction information corresponding to a reference model; the first instruction information and the second instruction information are of the same type; the second instruction information is used to represent the attribute information obtained after the reference model executes the target instruction; the processor to be verified and the reference model are established based on the specification definition of the same instruction set architecture; based on the first instruction information and the second instruction information, determining a verification result for the processor to be verified; the verification result is used to represent whether the instruction set architecture behavior in the processor to be verified conforms to the specification definition of the instruction set architecture.

[0091] In another aspect, the present invention also provides a non-transitory computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it is implemented to execute the processor verification method provided by each of the above methods. The method includes: obtaining first instruction information corresponding to the processor to be verified; the first instruction information is used to represent the attribute information obtained after the processor to be verified executes a target instruction; based on the first instruction information, determining second instruction information corresponding to a reference model; the first instruction information and the second instruction information are of the same type; the second instruction information is used to represent the attribute information obtained after the reference model executes the target instruction; the processor to be verified and the reference model are established based on the specification definition of the same instruction set architecture; based on the first instruction information and the second instruction information, determining a verification result for the processor to be verified; the verification result is used to represent whether the instruction set architecture behavior in the processor to be verified conforms to the specification definition of the instruction set architecture.

[0092] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art can understand and implement it without creative labor.

[0093] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on such an understanding, the essence of the above technical solution, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0094] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A processor verification method, characterized in that: include: Obtaining first instruction information corresponding to the processor to be verified; The first instruction information is used to represent the attribute information obtained after the processor to be verified executes the target instruction; Based on the first instruction information, determining second instruction information corresponding to the reference model; The first instruction information and the second instruction information are of the same type; The second instruction information is used to represent the attribute information obtained after the reference model executes the target instruction; The processor to be verified and the reference model are established based on the specification definition of the same instruction set architecture; Based on the first instruction information and the second instruction information, a verification result of the processor to be verified is determined; the verification result is used to characterize whether the instruction set architecture behavior in the processor to be verified complies with the specification definition of the instruction set architecture.

2. The processor verification method according to claim 1, characterized in that: The first instruction information is a first instruction stream, and the second instruction information is a second instruction stream; The determining, based on the first instruction information and the second instruction information, a verification result of the processor to be verified includes: Compare the first content in the first instruction stream with the second content in the second instruction stream to obtain a first comparison result; the first content and the second content are of the same type; Based on the first comparison result, the verification result is determined.

3. The processor verification method according to claim 1, characterized in that: The first instruction information is a random load memory access stream, and the second instruction information is a reference load memory access stream; The determining, based on the first instruction information and the second instruction information, a verification result of the processor to be verified includes: Reordering the out-of-order loading memory access stream based on the reorder buffer pointer to obtain a reordered loading memory access stream; Inserting the reordered load access flow into the initial load reorder queue to obtain a second load reorder queue; The verification result is determined based on the second load reorder queue and the reference load memory access flow.

4. The processor verification method according to claim 3, characterized in that: The determining the verification result based on the second load reordering queue and the reference load memory access flow includes: Acquire a pipeline flush signal of the processor to be verified; the pipeline flush signal is used to represent a signal for clearing invalid instructions; Based on the pipeline flush signal, delete the load access flow table entry located in the error instruction path in the second load reordering queue to obtain a third load reordering queue; Dequeue and compare the first queue head entry in the third load reordering queue and the second queue head entry in the reference load access flow to obtain a second comparison result; When the second comparison result is that the first team head table entry and the second team head table entry are inconsistent, it is determined that the verification result is that the instruction set architecture in the processor to be verified does not comply with the specification definition of the instruction set architecture.

5. The processor verification method according to claim 1, characterized in that: The first instruction information is a sequential storage access flow, and the second instruction information is a reference storage access flow; The determining, based on the first instruction information and the second instruction information, a verification result of the processor to be verified includes: Inserting the sequential storage access flow into the end of the initial tested storage queue to obtain a second tested storage queue; Inserting the reference storage access flow into the end of the initial reference storage queue to obtain a second reference storage queue; Dequeueing and comparing the third queue head entry of the second tested storage queue and the fourth queue head entry of the second reference storage queue to obtain a third comparison result; Based on the third comparison result, the verification result is determined.

6. The processor verification method according to any one of claims 1 to 4, characterized in that: The determining, based on the first instruction information, second instruction information corresponding to the reference model includes: Based on the first instruction information, determining a target instruction executed by the processor to be verified; The reference model is called to execute the target instruction to obtain the second instruction information.

7. The processor verification method according to any one of claims 1 to 4, characterized in that: Before obtaining the first instruction information corresponding to the processor to be verified, the method further includes: Obtaining configuration information of the processor to be verified; Based on the configuration information, the configuration information in the initial model is adjusted to obtain the reference model.

8. A processor verification device, characterized in that: include: An acquisition module, used to acquire first instruction information corresponding to the processor to be verified; A second instruction information determining module, used to determine second instruction information corresponding to a reference model based on the first instruction information; The first instruction information and the second instruction information are of the same type; A verification result determination module is used to determine the verification result of the processor to be verified based on the first instruction information and the second instruction information; the verification result is used to characterize whether the instruction set architecture behavior in the processor to be verified complies with the specification definition of the instruction set architecture.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that: When the processor executes the computer program, the processor verification method according to any one of claims 1 to 7 is implemented.

10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the processor verification method according to any one of claims 1 to 7 is implemented.

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