Compensation circuit and compensation method of radio frequency clock chip

Abstract

The invention provides a compensation circuit and a compensation method for a radio frequency clock chip, and the method comprises the steps: firstly, collecting a real-time temperature value, a power noise condition and other chip working environments; secondly, based on a preset frequency deviation curve, according to the real-time temperature value, generating a first compensation voltage of the voltage-controlled oscillator by adopting an interpolation algorithm; then, based on a preset spectral analysis algorithm, high-frequency noise and low-frequency noise in the power supply noise are separated, and the power supply noise is suppressed in combination with a feedback control algorithm and cascade filter network frequency division; and finally, on the basis of the difference value between the output frequency of the voltage-controlled oscillator and the target frequency, generating a second compensation voltage of the voltage-controlled oscillator on the basis of a preset nonlinear tuning characteristic curve. According to the invention, a multi-dimensional cooperative compensation mechanism is formed through a hardware-algorithm, the problem of frequency stability of the radio frequency clock chip in a complex environment is solved, and the comprehensive performance of the radio frequency clock chip is improved to a new dimension.

Description

Technical Field

[0001] The present invention belongs to the field of radio frequency clocks. More specifically, the present invention discloses a compensation circuit and a compensation method for a radio frequency clock chip. Background Art

[0002] As the core timing source of a communication system, the frequency stability of a radio frequency clock chip directly determines the system performance. However, the existing technologies face significant challenges in high-frequency and variable working conditions: Firstly, traditional temperature compensation schemes mostly rely on a single linear model, making it difficult to adapt to the non-linear drift in a wide temperature range, resulting in the accumulation of frequency errors; Secondly, a static filtering structure is usually adopted to suppress power supply noise, unable to distinguish low-frequency ripple from high-frequency interference, causing phase noise deterioration; Thirdly, the inherent non-linear tuning characteristics of a voltage-controlled oscillator (VCO) cause the relationship between the frequency control voltage to deviate from the ideal curve. Without a dynamic segmented calibration mechanism, the frequency synthesis error is exacerbated; Fourthly, a phase-locked loop (PLL) with a fixed bandwidth is usually adopted, making it difficult to balance the locking speed and the noise suppression ability in a dynamic noise environment; In addition, when the load impedance is mismatched, the compensation relies on off-line pre-calibration, unable to respond to changes in real time, and the fault recovery mechanism is single, with a high switching delay after loss of lock, easily causing system-level timing disorders. These problems severely limit the application reliability of radio frequency clock chips in high-precision scenarios such as 5G and satellite communications.

[0003] Therefore, there is an urgent need for a multi-dimensional collaborative compensation technology for radio frequency clock chips to adapt to usage scenarios with strict stability requirements.

[0004] Explanation of Abbreviations of Professional Terms: LDO, low-dropout linear regulator, an electronic device used to provide a stable DC voltage power supply; VCO, voltage-controlled oscillator, an electronic device that generates oscillation signals with different frequencies according to the input voltage; PLL, phase-locked loop, a feedback control circuit used to achieve the synchronization of the phase and frequency of the output signal with the input signal; DAC, digital-to-analog converter, an electronic device that converts digital signals into analog signals; TDC, time-to-digital converter, an electronic device that converts time intervals or time delays into digital signals. Summary of the Invention

[0005] In view of the above problems, the purpose of the present invention is to provide a compensation circuit and compensation method for a radio frequency clock chip. First, the chip working environment such as real-time temperature value and power supply noise is collected; secondly, based on the preset frequency offset curve, according to the real-time temperature value, an interpolation algorithm is used to generate a first compensation voltage of a voltage-controlled oscillator; then, based on a preset spectrum analysis algorithm, the high-frequency noise and low-frequency noise in the power supply noise are separated, and the power supply noise is suppressed by combining the feedback control algorithm and the cascade filter network frequency division; finally, based on the difference between the output frequency of the voltage-controlled oscillator and the target frequency, based on the preset nonlinear tuning characteristic curve, a second compensation voltage of the voltage-controlled oscillator is generated. The present invention solves the frequency stability problem of the radio frequency clock chip in a complex environment by forming a multi-dimensional collaborative compensation mechanism through hardware-algorithm, and improves the comprehensive performance of the radio frequency clock chip to a new dimension.

[0006] Through the multi-dimensional collaborative compensation mechanism, the frequency stability problem of RF clock chips in complex environments is solved In order to achieve the above object, the first aspect of the present invention provides a compensation circuit for a radio frequency clock chip, the compensation circuit comprising: A power supply noise suppression module, comprising a π-type LC filter, a low-noise LDO and a multi-stage decoupling capacitor, wherein the π-type LC filter and the low-noise LDO are connected in series to the power supply input, and the decoupling capacitor is deployed between the power supply pin of the voltage-controlled oscillator and the ground; A temperature compensation module, used to generate temperature compensation information based on temperature information, wherein a compensation output terminal of the temperature compensation module is connected to a control voltage input terminal of a voltage-controlled oscillator; A VCO nonlinear compensation module generates a reverse compensation signal and adjusts the reverse compensation voltage of the voltage-controlled oscillator based on the real-time frequency of the voltage-controlled oscillator; The PLL phase compensation module dynamically adjusts the PLL closed-loop bandwidth by switching the switched capacitor array based on the phase error between the reference clock and the voltage-controlled oscillator output clock.

[0007] In this solution, the temperature compensation module specifically includes: The temperature detection unit is a high-precision digital temperature sensor used to measure the real-time temperature information of the compensation circuit; The temperature compensation adjustment unit comprises a first programmable DAC, wherein an output terminal of the first programmable DAC is connected to a control voltage input terminal of a voltage-controlled oscillator; The temperature compensation adjustment unit generates temperature compensation information based on real-time temperature information, and adjusts the first programmable DAC according to the temperature compensation information.

[0008] In this solution, the VCO nonlinear compensation module specifically includes: The digital predistortion unit includes a non - linear function generator and a second programmable DAC. The non - linear function generator generates a reverse compensation signal according to the tuning voltage - frequency characteristic curve of the voltage - controlled oscillator. The piece - wise linearization tuning unit is used to divide the tuning range of the voltage - controlled oscillator into at least 3 sub - intervals, and each sub - interval is configured with a gain calibration coefficient to adjust the reverse compensation signal according to the calibration coefficient. The calibration feedback loop unit triggers an update of the reverse compensation voltage output by the second programmable DAC based on the deviation between the real - time frequency and the target frequency.

[0009] In this solution, the PLL phase compensation module specifically includes: An adaptive loop filter, which consists of a programmable switched - capacitor array and adjusts the filter capacitance value by switching switches. A time - to - digital converter is used to quantify the phase error between the reference clock and the output clock of the voltage - controlled oscillator. The closed - loop bandwidth control unit dynamically switches the configuration of the switched - capacitor array according to the phase error, so that the PLL closed - loop bandwidth is within a preset bandwidth threshold range.

[0010] The second aspect of the present invention also provides a compensation method for a radio - frequency clock chip, which is applied to the compensation circuit of any of the above - mentioned radio - frequency clock chips. The compensation method includes: Obtain the chip operating environment parameters, including at least the first temperature information and the first power supply noise information. Based on the frequency offset curve obtained from the preset temperature calibration data, obtain the first compensation voltage information according to the first temperature information. Based on the preset spectrum analysis algorithm, separate the low - frequency noise information and the high - frequency noise information according to the first power supply noise information. According to the high - frequency noise information, dynamically switch the multi - stage decoupling capacitors. According to the low - frequency noise information, dynamically adjust the first feedback voltage of the low - noise LDO through a preset feedback regulation algorithm. Obtain the first frequency information output by the voltage - controlled oscillator. According to the difference between the first frequency information and the target frequency, obtain the second compensation voltage information based on the preset tuning characteristic curve. Adjust the output voltage of the voltage - controlled oscillator according to the first compensation voltage information and the second compensation voltage information.

[0011] In this solution, the frequency offset obtained from the preset temperature calibration data, and obtaining the first compensation voltage information according to the first temperature information is specifically: Based on the discrete data points of the preset temperature-frequency offset, perform curve fitting according to the preset to obtain the frequency offset curve. Among them, the method for obtaining the discrete data points of the temperature-frequency offset includes: in the chip initialization stage, place the chip in a temperature-controlled environment and collect the output frequency of the voltage-controlled oscillator at preset temperature intervals to obtain the temperature-frequency discrete data points; According to the first temperature information, based on the frequency offset curve, use the interpolation algorithm to obtain the first compensation coefficient; Generate the first compensation voltage information inversely proportional to the temperature according to the first compensation coefficient to adjust the first programmable DAC.

[0012] In this solution, the dynamic switching of the multi-stage decoupling capacitors according to the high-frequency noise information is specifically as follows: Obtain the first noise main frequency according to the high-frequency noise information; Obtain the first noise amplitude threshold according to the frequency of the first noise main frequency; Switch the conduction states of the multi-stage decoupling capacitors in sequence until the amplitude of the first noise main frequency is lower than the set first noise amplitude threshold.

[0013] In this solution, the dynamic adjustment of the first feedback voltage of the low-noise LDO according to the low-frequency noise information through the preset feedback adjustment algorithm is specifically as follows: Obtain the second noise main frequency according to the low-frequency noise information; Obtain the second noise amplitude threshold according to the frequency of the second noise main frequency; Calculate the difference between the amplitude of the second noise main frequency and the second noise amplitude threshold to obtain the noise deviation information; Based on the preset feedback control algorithm, obtain the voltage control amount according to the noise deviation information; Adjust the first feedback voltage according to the voltage control amount.

[0014] In this solution, the obtaining of the second compensation voltage information according to the difference between the first frequency information and the target frequency based on the preset tuning characteristic curve is specifically as follows: Based on the discrete data points of the preset voltage-frequency, perform curve fitting according to the preset to obtain the tuning characteristic curve. Among them, the method for obtaining the discrete data points of the voltage-frequency includes: in the chip calibration stage, scan the corresponding relationship between the voltage-controlled oscillator control voltage and the output frequency; Perform function inverse operation based on the tuning characteristic curve to generate the pre-distortion compensation correspondence table; According to the difference between the first frequency information and the target frequency, look up the pre-distortion compensation correspondence table to obtain the second compensation voltage information; The second programmable DAC is adjusted according to the second compensation voltage information.

[0015] This solution also includes dynamically adjusting the closed-loop bandwidth, specifically: Obtaining first time difference information through the time-to-digital converter; According to the first time difference information, based on a preset closed-loop bandwidth mode library, a first capacitor array mode is obtained; According to the first capacitor array mode, the configuration of the switch capacitor array is switched.

[0016] The present invention provides a compensation circuit and compensation method for a radio frequency clock chip. First, the chip working environment such as real-time temperature value and power supply noise is collected; secondly, based on a preset frequency offset curve, according to the real-time temperature value, an interpolation algorithm is used to generate a first compensation voltage of a voltage-controlled oscillator; then, based on a preset spectrum analysis algorithm, high-frequency noise and low-frequency noise in the power supply noise are separated, and the power supply noise is suppressed by combining a feedback control algorithm and a cascade filter network frequency division; finally, based on the difference between the output frequency of the voltage-controlled oscillator and the target frequency, a second compensation voltage of the voltage-controlled oscillator is generated based on a preset nonlinear tuning characteristic curve. The present invention constitutes a multi-dimensional collaborative compensation mechanism through hardware-algorithm, solves the frequency stability problem of the radio frequency clock chip in a complex environment, and improves the comprehensive performance of the radio frequency clock chip to a new dimension. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and should not be regarded as limiting the scope.

[0018] Figure 1 A schematic diagram showing the structural connection of a compensation circuit of a radio frequency clock chip is shown; Figure 2 A schematic diagram showing the structure of a temperature compensation module provided by an embodiment of the present invention is shown; Figure 3 A schematic diagram showing the structure of a VCO nonlinear compensation module provided by an embodiment of the present invention is shown; Figure 4 A schematic diagram showing the structure of a PLL phase compensation module provided by an embodiment of the present invention is shown; Figure 5 A schematic flow chart of a compensation method for a radio frequency clock chip is shown; Figure 6 A temperature compensation flow chart provided by an embodiment of the present invention is shown; Figure 7 A filtering flow chart of high-frequency power supply noise provided by an embodiment of the present invention is shown; Figure 8 The flowchart for suppressing low-frequency power supply noise provided by the embodiments of the present invention is shown; Figure 9 The flowchart for non-linear compensation of the output frequency provided by the embodiments of the present invention is shown. Detailed implementation manners

[0019] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0020] Unless otherwise defined, all terms (including technical and scientific terms) used in the embodiments of the present invention have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present invention belongs. It should also be understood that terms such as those defined in a general dictionary should be interpreted as having a meaning consistent with their meaning in the context of the related art, and should not be interpreted in an idealized or overly formal sense unless explicitly defined in the embodiments of the present invention.

[0021] The "first", "second" and similar terms used in the embodiments of the present invention do not denote any order, quantity or importance, but are only used to distinguish different components. Terms such as "a", "one" or "the" do not denote a quantity limitation either, but mean that there is at least one. Similarly, words such as "include" or "comprise" mean that the elements or objects appearing before this word cover the elements or objects listed after this word and their equivalents, without excluding other elements or objects. "Connection" or "connected" and similar terms are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The steps before or after the methods in the embodiments of the present invention do not necessarily have to be carried out precisely in order. On the contrary, they can be carried out in reverse order or simultaneously. At the same time, other operations can also be added to these processes, or one or several steps can be removed from these processes.

[0022] Please refer to Figure 1 , Figure 1 which shows a schematic structural connection diagram of a compensation circuit for a radio frequency clock chip.

[0023] As Figure 1 shown, in a first aspect of the present invention, a compensation circuit for a radio frequency clock chip is disclosed, and the circuit includes: The power supply noise suppression module 101 includes a π-type LC filter, a low-noise LDO, and a multi-stage decoupling capacitor. The π-type LC filter and the low-noise LDO are connected in series to the power supply input, and the decoupling capacitor is deployed between the power supply pin of the voltage-controlled oscillator and the ground; The temperature compensation module 102 is used to generate temperature compensation information based on temperature information. The compensation output terminal of the temperature compensation module is connected to the control voltage input terminal of the voltage-controlled oscillator; The VCO non-linear compensation module 103 generates a reverse compensation signal based on the real-time frequency of the voltage-controlled oscillator and adjusts and controls the reverse compensation voltage of the voltage-controlled oscillator; The PLL phase compensation module 104 dynamically adjusts the PLL closed-loop bandwidth by switching the switched capacitor array based on the phase error between the reference clock and the output clock of the voltage-controlled oscillator.

[0024] It should be noted that the voltage-controlled oscillator 100 includes a power supply terminal, a control voltage terminal, and an output terminal; the power supply terminal is used to receive the driving power supply, the control voltage terminal is used to adjust the output frequency, and the output terminal is used to output a clock signal. The power supply noise suppression module includes a π-type LC filter, a low-noise LDO, and a multi-stage decoupling capacitor. The π-type LC filter is composed of a high-frequency power inductor, a low-ESR ceramic capacitor, and a high-precision damping resistor; among them, the resonant frequency of the LC filter reaches a preset frequency value, such as 1 MHz, to suppress high-frequency noise. An ultra-low-noise LDO is selected, and the feedback pin of the LDO is connected to a low-temperature-drift resistor. The LDO output is connected in parallel with a tantalum capacitor and a ceramic capacitor and other capacitor arrays to form a multi-stage decoupling structure. In addition, the power supply noise suppression module is designed with heat dissipation vias in the PCB, and the vias are connected to the heat dissipation layer on the back of the PCB to improve the heat dissipation effect, thereby ensuring the stability of the power supply output at high temperatures. The temperature compensation module collects the real-time temperature value of the circuit through a temperature sensor, generates a compensation signal through a compensation unit according to the real-time temperature value, and then outputs the compensation signal to the control voltage terminal of the voltage-controlled oscillator through a high-precision DAC. The VCO non-linear compensation module first generates a reverse compensation signal according to the output frequency of the voltage-controlled oscillator through a predistortion unit, then corrects the reverse compensation signal by using a non-linear adjustment coefficient through a piecewise linearization tuning unit, and finally triggers a high-precision DAC to output the reverse compensation signal to the control voltage terminal of the voltage-controlled oscillator by a calibration feedback loop unit. The PLL phase compensation module quantifies the phase error between the reference clock and the output clock of the voltage-controlled oscillator through a time-to-digital converter, and adjusts the PLL closed-loop bandwidth based on the phase error by switching the switched capacitor array.

[0025] Please refer to Figure 2 , Figure 2 which shows the structural schematic diagram of the temperature compensation module provided by the embodiment of the present invention.

[0026] According to the embodiment of the present invention, as Figure 2As shown, the temperature compensation module 102 specifically includes: A temperature detection unit 201, which is a high-precision digital temperature sensor, used to measure the real-time temperature information of the compensation circuit; A temperature compensation adjustment unit 202, including a first programmable DAC 2021, and the output end of the first programmable DAC is connected to the control voltage input end of the voltage-controlled oscillator; The temperature compensation adjustment unit generates temperature compensation information based on the real-time temperature information, and adjusts the first programmable DAC according to the temperature compensation information.

[0027] It should be noted that a high-precision digital temperature sensor, such as MAX31875, is used to communicate data with the processor through the I2C interface. The temperature sensor is arranged within a set distance range of the voltage-controlled oscillator to ensure the accuracy of temperature measurement. The temperature compensation unit generates a temperature compensation signal based on the real-time temperature information, and then outputs a compensation voltage through a high-precision DAC, which is superimposed on the original control voltage of the voltage-controlled oscillator; among them, the compensation signal includes bidirectional adjustment, that is, an upward compensation voltage or a downward compensation voltage.

[0028] Please refer to Figure 3 , Figure 3 which shows the structural schematic diagram of the VCO nonlinear compensation module provided by the embodiment of the present invention.

[0029] According to the embodiment of the present invention, as Figure 3 shown, the VCO nonlinear compensation module 103 specifically includes: A digital predistortion unit 301, including a nonlinear function generator and a second programmable DAC, and the nonlinear function generator generates a reverse compensation signal according to the tuning voltage-frequency characteristic curve of the voltage-controlled oscillator; A piecewise linearized tuning unit 302, used to divide the tuning range of the voltage-controlled oscillator into at least 3 sub-intervals, each sub-interval is configured with a gain calibration coefficient, and adjusts the reverse compensation signal according to the calibration coefficient; A calibration feedback loop unit 303, based on the deviation between the real-time frequency and the target frequency, triggers an update of the reverse compensation voltage output by the second programmable DAC.

[0030] It should be noted that the digital predistortion unit generates a tuning characteristic curve based on the relationship between the control voltage and the output frequency of the voltage-controlled oscillator in the rated working environment; and then obtains a reverse compensation signal according to the difference between the output frequency of the voltage-controlled oscillator and the target frequency. The piecewise linearization tuning unit divides the tuning range of the voltage-controlled oscillator into at least 3 sub-intervals, generates corresponding linear gain relationships according to each sub-interval, and obtains corresponding gain calibration coefficients based on the linear gain relationships for correcting the reverse compensation signal. Finally, the calibration feedback loop unit triggers the second programmable DAC to output a reverse compensation voltage according to the deviation between the real-time frequency and the target frequency. When the above deviation exceeds the set deviation threshold, the reverse compensation signal includes bidirectional adjustment, that is, an upward reverse compensation voltage or a downward reverse compensation voltage.

[0031] Please refer to Figure 4 , Figure 4 which shows a schematic structural diagram of the PLL phase compensation module provided by an embodiment of the present invention.

[0032] According to an embodiment of the present invention, as Figure 4 shown, the PLL phase compensation module 104 specifically includes: An adaptive loop filter 401, which is composed of a programmable switched capacitor array and adjusts the filter capacitance value by switching the switch; A time-to-digital converter 402 for quantifying the phase error between the reference clock and the output clock of the voltage-controlled oscillator; A closed-loop bandwidth control unit 403, which dynamically switches the configuration of the switched capacitor array according to the phase error to make the PLL closed-loop bandwidth within a preset bandwidth threshold range.

[0033] It should be noted that the adaptive loop filter is provided with multiple groups of capacitor arrays, and the connection of the capacitor arrays is controlled by MOS switches. In this embodiment, by switching the configuration of the switched capacitor array, the PLL closed-loop bandwidth can be adjusted. The time-to-digital converter 402 quantifies the phase error between the reference clock and the output clock of the voltage-controlled oscillator. According to the amplitude of the phase error, by switching the configuration of the switched capacitor array, the PLL closed-loop bandwidth is within a preset bandwidth threshold range to achieve the effect of stable phase locking.

[0034] Please refer to Figure 5 , Figure 5 which shows a schematic flow diagram of a compensation method for a radio frequency clock chip.

[0035] As Figure 5 shown, a second aspect of the present invention discloses a compensation method for a radio frequency clock chip, and the compensation method includes: S502, obtaining chip working environment parameters, at least including first temperature information and first power supply noise information; S504, obtain the first compensation voltage information according to the first temperature information based on the frequency offset curve obtained from the preset temperature calibration data; S506, based on the preset spectrum analysis algorithm, separate the low-frequency noise information and the high-frequency noise information according to the first power supply noise information; S508, dynamically switch the multi-stage decoupling capacitor according to the high-frequency noise information; S510, dynamically adjust the first feedback voltage of the low-noise LDO through the preset feedback adjustment algorithm according to the low-frequency noise information; S512, obtain the first frequency information output by the voltage-controlled oscillator; S514, obtain the second compensation voltage information based on the preset tuning characteristic curve according to the difference between the first frequency information and the target frequency; S516, adjust the output voltage of the voltage-controlled oscillator according to the first compensation voltage information and the second compensation voltage information.

[0036] It should be noted that the first temperature information is the real-time temperature value of the compensation circuit; the first power supply noise information is the power supply noise input to the compensation circuit; the high-frequency noise information is the power supply noise with a frequency exceeding the preset noise frequency threshold; the low-frequency noise information is the power supply noise with a frequency not exceeding the preset noise frequency threshold; the first compensation voltage information is the compensation voltage value output by the temperature compensation module to the voltage-controlled oscillator; the first feedback voltage is the voltage value of the feedback pin of the low-noise LDO; the first frequency information is the frequency of the clock signal output by the voltage-controlled oscillator; the second compensation voltage information is the compensation voltage value output by the VCO nonlinear compensation module to the voltage-controlled oscillator.

[0037] In this embodiment, compensation adjustments are respectively performed on the front-end signal and the back-end signal of the voltage-controlled oscillator. The compensation of the front-end signal of the voltage-controlled oscillator refers to compensating the operating environment parameters of the compensation circuit, specifically including temperature compensation and power supply noise compensation. For temperature compensation, according to the real-time temperature value, based on the frequency offset curve obtained from the preset temperature calibration data, the corresponding temperature compensation signal is obtained by using the interpolation algorithm, and then the temperature compensation signal is converted into the first compensation voltage through a high-precision DAC and output to the control voltage terminal of the voltage-controlled oscillator to achieve the temperature compensation function. For power supply noise compensation, first, the power supply noise is separated into high-frequency noise and low-frequency noise through FFT transformation; for high-frequency noise, hardware filtering is achieved by switching the multi-stage decoupling capacitors; for low-frequency noise, the feedback voltage of the low-frequency LDO is dynamically adjusted through a preset feedback adjustment algorithm, so as to achieve the effect of reducing low-frequency noise. The compensation of the back-end signal of the voltage-controlled oscillator refers to performing reverse compensation based on the output signal of the voltage-controlled oscillator, thereby improving the output stability. The frequency of the output clock signal of the voltage-controlled oscillator is measured in real time, that is, the output frequency; the difference between the output frequency and the target frequency is calculated. Then, according to the frequency difference, the reverse compensation signal is determined based on the preset tuning characteristic curve; and then the reverse compensation signal is converted into the second compensation voltage through a high-precision DAC and output to the control voltage terminal of the voltage-controlled oscillator to achieve the reverse compensation function. Through the multi-dimensional collaborative compensation mechanism, the frequency stability of the radio frequency clock chip in a complex environment is improved.

[0038] Please refer to Figure 6 , Figure 6 which shows the temperature compensation flowchart provided by the embodiment of the present invention.

[0039] In the embodiment of the present invention, as Figure 6 shown, for the frequency offset obtained from the preset temperature calibration data, according to the first temperature information, the first compensation voltage information is obtained, specifically: S602, based on the discrete data points of the preset temperature-frequency offset, perform curve fitting according to the preset to obtain the frequency offset curve; S604, according to the first temperature information, based on the frequency offset curve, use the interpolation algorithm to obtain the first compensation coefficient; S606, according to the first compensation coefficient, generate the first compensation voltage information inversely proportional to the temperature to adjust the first programmable DAC; Among them, the method for obtaining the discrete data points of temperature-frequency offset includes: in the chip initialization stage, place the chip in a temperature-controlled environment, and collect the output frequency of the voltage-controlled oscillator at a preset temperature interval to obtain the temperature-frequency discrete data points.

[0040] It should be noted that, as an implementation, during the initialization stage of the radio frequency clock chip, the temperature range preset by the test control is set through a high-precision constant temperature chamber. For example, the temperature range is from -40°C to 80°C, and the output frequency of the voltage-controlled oscillator is collected at a sampling interval of 5°C, so as to obtain temperature-frequency discrete data points. Based on the discrete data points, curve fitting methods such as quadratic fitting and exponential fitting are used to obtain the frequency offset curve. According to the real-time temperature value of the voltage-controlled oscillator, based on the frequency offset curve, an interpolation algorithm is used to obtain the frequency offset amount, and then based on the corresponding discrete point data, it is converted into a compensation coefficient. Finally, based on the compensation coefficient and the current control voltage of the voltage-controlled oscillator, the first compensation voltage information is calculated; the first compensation voltage is output to the voltage control terminal of the voltage-controlled oscillator through the first programmable DAC, so as to achieve the effect of temperature compensation.

[0041] Please refer to Figure 7 , Figure 7 which shows the filtering flowchart of the high-frequency power supply noise provided by the embodiment of the present invention.

[0042] In the embodiment of the present invention, as Figure 7 shown, the dynamically switching the multi-stage decoupling capacitors according to the high-frequency noise information is specifically as follows: S702, obtaining the first noise main frequency according to the high-frequency noise information; S704, obtaining the first noise amplitude threshold according to the frequency of the first noise main frequency; S706, sequentially switching the conduction states of the multi-stage decoupling capacitors until the amplitude of the first noise main frequency is lower than the set first noise amplitude threshold.

[0043] It should be noted that, in this embodiment, for high-frequency noise, hardware filtering is achieved by switching the multi-stage decoupling capacitors. First, the frequency and amplitude of the high-frequency noise signal are analyzed to obtain the noise frequency with the highest amplitude value, so as to determine the first noise main frequency. Then, based on the frequency value of the first noise main frequency, the preset first main frequency corresponding table is searched to determine the first noise amplitude threshold. Finally, the conduction of the multi-stage decoupling capacitors is sequentially switched according to the set order until the amplitude of the first noise main frequency is lower than the set first noise amplitude threshold.

[0044] Please refer to Figure 8 , Figure 8 which shows the suppression flowchart of the low-frequency power supply noise provided by the embodiment of the present invention.

[0045] In the embodiment of the present invention, as Figure 8 shown, the dynamically adjusting the first feedback voltage of the low-noise LDO according to the low-frequency noise information through a preset feedback adjustment algorithm is specifically as follows: S802. Obtain a second main noise frequency based on the low-frequency noise information. S804. Obtain a second noise amplitude threshold based on the frequency of the second main noise frequency. S806. Calculate the difference between the amplitude of the second main noise frequency and the second noise amplitude threshold to obtain noise deviation information. S808. Based on the noise deviation information, obtain a voltage control amount based on a preset feedback control algorithm. S810. Adjust the first feedback voltage according to the voltage control amount.

[0046] It should be noted that in this embodiment, for low-frequency noise, the feedback voltage of the low-frequency LDO is dynamically adjusted through a preset feedback adjustment algorithm, so as to achieve the effect of reducing low-frequency noise. First, analyze the frequency and amplitude of the low-frequency noise signal to obtain the noise frequency with the highest amplitude value, so as to determine the second main noise frequency. Secondly, based on the frequency value of the second main noise frequency, look up the preset second main frequency corresponding table to determine the second noise amplitude threshold. Then, calculate the difference between the amplitude of the second main noise frequency and the second noise amplitude threshold to obtain a noise deviation value; then, based on a preset feedback control algorithm, such as the PID algorithm, calculate the voltage control amount. Finally, adjust the first feedback voltage of the low-noise LDO through the voltage control amount. That is to say, based on the noise deviation value, the effect of dynamically adjusting the feedback voltage is achieved through the feedback control algorithm.

[0047] Please refer to Figure 9 , Figure 9 which shows the non-linear compensation flowchart of the output frequency provided by the embodiment of the present invention.

[0048] In the embodiment of the present invention, as Figure 9 shown, obtaining the second compensation voltage information based on the difference between the first frequency information and the target frequency and based on a preset tuning characteristic curve is specifically as follows: S902. Based on the discrete data points of the preset voltage-frequency, perform curve fitting according to the preset to obtain a tuning characteristic curve. S904. Perform an inverse function operation based on the tuning characteristic curve to generate a pre-distortion compensation corresponding table. S906. According to the difference between the first frequency information and the target frequency, look up the pre-distortion compensation corresponding table to obtain the second compensation voltage information. S908. Adjust the second programmable DAC according to the second compensation voltage information. Among them, the method for obtaining the discrete data points of voltage-frequency includes: during the chip calibration stage, scan the corresponding relationship between the voltage-controlled oscillator control voltage and the output frequency.

[0049] It should be noted that in this embodiment, a reverse compensation logic based on nonlinear tuning is provided. As an implementation, during the calibration phase of the radio frequency clock chip, based on the range of the control voltage of the voltage-controlled oscillator, with a preset step voltage, a frequency meter is used to record the output frequency corresponding to each voltage point, obtaining voltage-frequency discrete data points; for example, the control voltage range is 0 - 3V, with a step of 0.2V, and the output frequency of each voltage point is collected and recorded. Based on the discrete data points, curve fitting methods such as quadratic fitting and exponential fitting are used to obtain the tuning characteristic curve. Secondly, according to the tuning characteristic curve, in accordance with the calculation method of function inverse operation, a pre-distortion compensation correspondence table is generated. Then, according to the difference between the output frequency of the voltage-controlled oscillator and the target frequency, the pre-distortion compensation correspondence table is searched to obtain the reverse compensation signal; then the nonlinear gain calibration coefficient is searched to obtain the adjustment coefficient for the corresponding segment, which is used to correct the reverse compensation signal to obtain the reverse compensation voltage. Finally, the reverse compensation voltage is output to the voltage control terminal of the voltage-controlled oscillator through the second programmable DAC to achieve nonlinear tuning compensation.

[0050] In the embodiment of the present invention, it further includes dynamically adjusting the closed-loop bandwidth, specifically: Through the time-to-digital converter, the first time difference information is obtained; According to the first time difference information, based on a preset closed-loop bandwidth mode library, the first capacitor array mode is obtained; According to the first capacitor array mode, the configuration of the switched capacitor array is switched.

[0051] It should be noted that the first time difference information is the rising edge time difference between the quantization reference clock and the output clock of the voltage-controlled oscillator. In this embodiment, the first time difference information is measured by the time-to-digital converter. Then, based on the target output frequency, a time difference threshold is determined. When the first time difference information exceeds the time difference threshold, the preset closed-loop bandwidth mode library is searched according to the first time difference information to determine the first capacitor array mode. Then, the configuration of the switched capacitor array is switched according to the first capacitor array mode, so that the PLL closed-loop bandwidth is within the preset bandwidth threshold range, thereby improving the stability of phase locking.

[0052] It is worth mentioning that it further includes: Based on a preset first sampling frequency, the output signal of the voltage-controlled oscillator is collected to obtain the first time-domain waveform; According to the first time-domain waveform, through fast Fourier transform, the peak frequency of the phase noise is extracted; According to the peak frequency of the phase noise, based on a preset tuning characteristic curve, a reverse suppression voltage is generated; According to the reverse suppression voltage, the second programmable DAC is adjusted.

[0053] The phase noise refers to the phenomenon of random phase fluctuations of the oscillator output signal in the frequency domain, which is manifested as unwanted noise sidebands appearing near the main frequency of the signal.

[0054] It should be noted that, according to the preset sampling period, the output clock signal of the voltage-controlled oscillator is collected in real time to obtain the time-domain waveform of the clock signal. Then, based on the FFT transform, the time-domain waveform is converted into a frequency-domain waveform; and the peak frequency of the phase noise is extracted according to the frequency-domain waveform. Among them, the phase noise refers to the phenomenon of random phase fluctuations of the oscillator output signal in the frequency domain, which is manifested as unwanted noise sidebands appearing near the main frequency of the signal; the frequency at the peak is determined based on the amplitude of the phase noise. According to the peak frequency, a reverse suppression signal is generated based on the tuning characteristic curve of the VCO nonlinear compensation module; and then the reverse suppression signal is converted into a reverse suppression voltage by the second programmable DAC and output to the voltage control terminal of the voltage-controlled oscillator.

[0055] It is worth mentioning that it also includes: When a PLL unlock event is detected, the configuration of the switched-capacitor array is initialized and the compensation control logic is paused; Based on a preset ramp function, the control voltage of the voltage-controlled oscillator is gradually increased while detecting the PLL lock signal; When the lock signal becomes effective again, the compensation control logic is restarted.

[0056] It should be noted that this embodiment provides a self-recovery mechanism when the PLL unlocks. When the duration of the low level of the PLL lock detection signal exceeds the set time threshold, it is determined that the PLL unlocks. At this time, the compensation algorithm is paused and the DAC output is turned off to prevent sudden changes in the control voltage of the voltage-controlled oscillator. Then, starting from the set voltage value, the control voltage of the voltage-controlled oscillator is gradually increased with a ramp function having a preset slope while monitoring the lock detection signal. When the lock detection signal returns to a high level, it indicates that the PLL phase lock is restored, the compensation algorithm is re-enabled, and the DAC output is gradually restored to the normal value.

[0057] In summary, the present invention provides a compensation circuit and a compensation method for a radio frequency clock chip. First, the chip operating environment such as the real-time temperature value and the power supply noise condition is collected; secondly, based on a preset frequency offset curve, according to the real-time temperature value, an interpolation algorithm is used to generate the first compensation voltage of the voltage-controlled oscillator; then, based on a preset spectrum analysis algorithm, the high-frequency noise and low-frequency noise in the power supply noise are separated, and the power supply noise is suppressed by combining the feedback control algorithm and the cascaded filter network frequency division; finally, based on the difference between the output frequency of the voltage-controlled oscillator and the target frequency, a second compensation voltage of the voltage-controlled oscillator is generated based on a preset nonlinear tuning characteristic curve. The present invention solves the frequency stability problem of the radio frequency clock chip in a complex environment through a multi-dimensional collaborative compensation mechanism composed of hardware-algorithms, and improves the comprehensive performance of the radio frequency clock chip to a new dimension.

[0058] In addition, each functional module in various embodiments of the present invention may be integrated together to form an independent part, or each module may exist alone, or two or more modules may be integrated to form an independent part.

[0059] If the above-mentioned function is implemented in the form of a software functional module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present invention. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), magnetic disks, or optical discs that can store program codes.

[0060] The foregoing are only the preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A compensation circuit for a radio frequency clock chip, characterized in that: The compensation circuit comprises: A power supply noise suppression module, comprising a π-type LC filter, a low-noise LDO and a multi-stage decoupling capacitor, wherein the π-type LC filter and the low-noise LDO are connected in series to the power supply input, and the decoupling capacitor is deployed between the power supply pin of the voltage-controlled oscillator and the ground; A temperature compensation module, used to generate temperature compensation information based on temperature information, wherein a compensation output terminal of the temperature compensation module is connected to a control voltage input terminal of a voltage-controlled oscillator; A VCO nonlinear compensation module generates a reverse compensation signal and adjusts the reverse compensation voltage of the voltage-controlled oscillator based on the real-time frequency of the voltage-controlled oscillator; The PLL phase compensation module dynamically adjusts the PLL closed-loop bandwidth by switching the switched capacitor array based on the phase error between the reference clock and the voltage-controlled oscillator output clock.

2. The compensation circuit of the radio frequency clock chip according to claim 1, characterized in that: The temperature compensation module specifically includes: The temperature detection unit is a high-precision digital temperature sensor used to measure the real-time temperature information of the compensation circuit; The temperature compensation adjustment unit comprises a first programmable DAC, wherein an output terminal of the first programmable DAC is connected to a control voltage input terminal of a voltage-controlled oscillator; The temperature compensation adjustment unit generates temperature compensation information based on real-time temperature information, and adjusts the first programmable DAC according to the temperature compensation information.

3. The compensation circuit of the radio frequency clock chip according to claim 1, characterized in that: The VCO nonlinear compensation module specifically includes: A digital predistortion unit, comprising a nonlinear function generator and a second programmable DAC, wherein the nonlinear function generator generates a reverse compensation signal according to a tuning voltage-frequency characteristic curve of a voltage-controlled oscillator; A piecewise linear tuning unit, used for dividing the tuning range of the voltage-controlled oscillator into at least three sub-intervals, each sub-interval is configured with a gain calibration coefficient, and the reverse compensation signal is adjusted according to the calibration coefficient; The calibration feedback loop unit triggers updating of the second programmable DAC output reverse compensation voltage based on the deviation between the real-time frequency and the target frequency.

4. The compensation circuit of the radio frequency clock chip according to claim 1, characterized in that: The PLL phase compensation module specifically includes: An adaptive loop filter, which consists of a programmable switched capacitor array, and the filter capacitor value is adjusted by switching switches; A time-to-digital converter for quantifying the phase error between a reference clock and a voltage-controlled oscillator output clock; The closed-loop bandwidth control unit dynamically switches the configuration of the switch capacitor array according to the phase error so that the PLL closed-loop bandwidth is within a preset bandwidth threshold range.

5. A compensation method for a radio frequency clock chip, applied to the compensation circuit of the radio frequency clock chip according to any one of claims 1 to 4, characterized in that: The compensation method includes: Acquire chip working environment parameters, including at least first temperature information and first power supply noise information; Based on a frequency offset curve obtained from preset temperature calibration data, first compensation voltage information is obtained according to the first temperature information; Based on a preset spectrum analysis algorithm, low-frequency noise information and high-frequency noise information are separated according to the first power supply noise information; Dynamically switching the multi-stage decoupling capacitors according to the high-frequency noise information; According to the low-frequency noise information, dynamically adjust the first feedback voltage of the low-noise LDO through a preset feedback adjustment algorithm; Acquire first frequency information output by a voltage-controlled oscillator; According to the difference between the first frequency information and the target frequency, based on a preset tuning characteristic curve, second compensation voltage information is obtained; The output voltage of the voltage-controlled oscillator is adjusted according to the first compensation voltage information and the second compensation voltage information.

6. The compensation method of a radio frequency clock chip according to claim 5, characterized in that: The frequency offset obtained based on the preset temperature calibration data obtains the first compensation voltage information according to the first temperature information, specifically: Based on the preset discrete data points of temperature-frequency offset, a frequency offset curve is obtained according to a preset curve fitting, wherein the method for obtaining the discrete data points of temperature-frequency offset includes: in the chip initialization stage, placing the chip in a controllable temperature environment, collecting the output frequency of the voltage-controlled oscillator at a preset temperature interval, and obtaining the temperature-frequency discrete data points; According to the first temperature information, based on the frequency offset curve, an interpolation algorithm is used to obtain a first compensation coefficient; According to the first compensation coefficient, first compensation voltage information inversely proportional to the temperature is generated to adjust the first programmable DAC.

7. The compensation method for a radio frequency clock chip according to claim 5, characterized in that: The dynamically switching the multi-stage decoupling capacitors according to the high-frequency noise information is specifically: Obtaining a first noise main frequency according to the high-frequency noise information; Obtaining a first noise amplitude threshold according to the frequency of the first noise main frequency; The conduction states of the multi-stage decoupling capacitors are switched in sequence until the amplitude of the first noise main frequency is lower than the set first noise amplitude threshold.

8. The compensation method for a radio frequency clock chip according to claim 5, characterized in that: The first feedback voltage of the low-noise LDO is dynamically adjusted according to the low-frequency noise information by a preset feedback adjustment algorithm, specifically: Obtaining a second noise main frequency according to the low-frequency noise information; Obtaining a second noise amplitude threshold according to the frequency of the second noise main frequency; Calculating a difference between the amplitude of the second noise main frequency and the second noise amplitude threshold to obtain noise deviation information; According to the noise deviation information, based on a preset feedback control algorithm, a voltage control amount is obtained; The first feedback voltage is adjusted according to the voltage control amount.

9. The compensation method for a radio frequency clock chip according to claim 5, characterized in that: The second compensation voltage information is obtained based on the difference between the first frequency information and the target frequency and on a preset tuning characteristic curve, specifically: Based on the preset voltage-frequency discrete data points, a tuning characteristic curve is obtained according to the preset curve fitting, wherein the method for obtaining the voltage-frequency discrete data points includes: in the chip calibration stage, scanning the corresponding relationship between the control voltage and the output frequency of the voltage-controlled oscillator; Performing a function inverse operation based on the tuning characteristic curve to generate a pre-distortion compensation correspondence table; According to the difference between the first frequency information and the target frequency, searching the pre-distortion compensation correspondence table to obtain second compensation voltage information; The second programmable DAC is adjusted according to the second compensation voltage information.

10. The compensation method of a radio frequency clock chip according to claim 5, characterized in that: It also includes dynamic adjustment of closed-loop bandwidth, specifically: Obtaining first time difference information through the time-to-digital converter; According to the first time difference information, based on a preset closed-loop bandwidth mode library, a first capacitor array mode is obtained; According to the first capacitor array mode, the configuration of the switch capacitor array is switched.

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