Pressure sensor and processing method

Abstract

The invention relates to the field of pressure sensors, in particular to a pressure sensor and a processing method, and a chip comprises a silicon substrate, a silicon dioxide dielectric layer, a device layer, a metal electrode and packaging glass. The device layer comprises a silicon carbide single crystal device layer and a silicon device layer; the silicon carbide single crystal device layer is arranged on the silicon device layer; the silicon device layer, the silicon dioxide dielectric layer and the silicon substrate are connected in sequence; the device layer is etched to form a sensitive resistor device layer, an annular sealing region and a micro-channel; the sensitive resistance device layer is isolated from the annular sealing area through the micro-channel; the device layer, the silicon dioxide dielectric layer and the silicon substrate are etched to form a cross beam etching area; the silicon substrate is etched to form a silicon pressure cavity and a beam film; the metal electrode is arranged on the top of the device layer; and the packaging glass anode is bonded at the top of the device layer or the bottom of the silicon substrate so as to solve the problems of low high temperature resistance and low sensitivity of the MEMS pressure sensor.

Description

Technical Field

[0001] The present application relates to the technical field of pressure sensors, and particularly relates to a pressure sensor and a processing method thereof. Background Art

[0002] Micro Electro Mechanical System (MEMS) is developed on the basis of microelectronic technology and is a high-tech electro-mechanical device integrating technologies such as lithography, etching, doping, thin film, LIGA, and precision machining. The piezoresistive pressure sensor processed based on MEMS technology has the advantages of low cost, high performance, and mass production, and is widely used in fields such as aerospace and automotive processing.

[0003] MEMS pressure sensors are mainly made of silicon materials. Commonly, there are two types: pressure sensors based on silicon PN junction isolation technology and pressure sensors based on SOI technology. Among them, the pressure sensor based on silicon PN junction isolation technology has a lower cost, but due to the limitation of silicon PN junction leakage current, its maximum application temperature is only 125°C; the pressure sensor based on SOI technology has more prominent high-temperature resistance performance due to material advantages, and its application temperature can reach 400°C, but it is difficult to exceed 450°C. With the continuous expansion of the application fields of sensors, for some special high-temperature use environments, the pressure sensors based on silicon PN junction isolation technology and the pressure sensors based on SOI technology cannot meet the requirements of high-temperature environments.

[0004] To meet the requirements of high-temperature environments, in related technologies, silicon carbide pressure sensors can be selected. Although silicon carbide pressure sensors can be applied to high-temperature environments above 800°C at most, due to the immaturity of the MEMS processing method of silicon carbide, the chip processing cost is high, mass production is difficult, the repeatability and consistency are poor, and there is also a problem of low sensitivity, which affects the detection accuracy of the pressure sensor. Summary of the Invention

[0005] The present application provides a pressure sensor and a processing method thereof to solve the problems of low high-temperature resistance and low sensitivity of MEMS pressure sensors.

[0006] The first aspect of the present application provides a pressure sensor, including: a silicon substrate, a silicon dioxide dielectric layer, a device layer, metal electrodes, and packaging glass; The device layer includes a 3C-SiC single crystal device layer and a silicon device layer; the 3C-SiC single crystal device layer is disposed on the silicon device layer; the silicon device layer, the silicon dioxide dielectric layer, and the silicon substrate are sequentially connected; The device layer is etched to form a sensitive resistor device layer, an annular sealing area, and a microchannel; the sensitive resistor device layer is isolated from the annular sealing area through the microchannel; A cross-beam etching region is formed by etching at the top center of the device layer, the silicon dioxide dielectric layer, and the silicon substrate; a silicon pressure cavity and a beam film are formed by etching at the bottom of the silicon substrate. The metal electrode is disposed on the top of the device layer; the encapsulation glass is anodically bonded to the top of the device layer or the bottom of the silicon substrate.

[0007] In this application, a 3C-SiC single-crystal device layer is epitaxially grown on the silicon device layer as the device layer, greatly improving the high-temperature resistance of the pressure-sensitive chip and enabling it to maintain stable mechanical and electrical properties under high-temperature conditions. At the same time, the silicon dioxide dielectric layer is provided between the device layer and the silicon substrate, which can significantly reduce the leakage current between the device layer and the silicon substrate, increase the breakdown voltage threshold, and is suitable for high-temperature environments. The cross-beam etching region can generate a greater stress value under the same pressure, optimize the stress distribution, and improve the output sensitivity of the 3C-SiC pressure-sensitive chip. In addition, the 3C-SiC single-crystal device layer is compatible with silicon dry and wet etching technologies to complete the processing of the pressure-sensitive diaphragm, and the process is stable, the etching is uniform, and the cost is low. It can also realize the sealing forms of absolute pressure, differential pressure, and gauge pressure, as well as the packaging structures of top sealing and bottom sealing respectively.

[0008] Optionally, the thickness range of the 3C-SiC single-crystal device layer is 500 nm - 2000 nm; the thickness range of the silicon device layer is 20 nm - 200 nm; the thickness range of the silicon dioxide dielectric layer is 200 nm - 2000 nm.

[0009] The 3C-SiC single-crystal device layer with a thickness range of 500 nm - 2000 nm can not only effectively withstand harsh environments such as high temperature and high pressure, ensuring the long-term stable operation of the device, but also be easily processed into the required shapes and sizes and integrated with other materials (such as silicon, silicon dioxide, etc.) to form composite-structure microelectronic devices. The silicon device layer with a thickness range of 20 nm - 200 nm can not only exhibit good electrical performance and power consumption characteristics, but also be conducive to achieving higher integration, enabling more electronic devices to be integrated on the same chip, thereby improving the function and performance of the entire system. In addition, within this thickness range, the doping concentration and distribution of the silicon device layer can be more precisely controlled, and it has good compatibility. The silicon dioxide dielectric layer with a thickness range of 200 nm - 2000 nm can not only effectively isolate adjacent electronic devices, prevent current leakage and signal interference, but also serve as a protective layer to prevent the device from being damaged by environmental factors such as moisture and oxygen, extending the service life of the device. In addition, the silicon dioxide dielectric layer can be flexibly applied to multi-layer structures and complex circuits, providing more degrees of freedom for the design and manufacture of the device.

[0010] Optionally, the number of the metal electrodes is four, and the four metal electrodes are disposed on the sensitive resistor device layer; the sensitive resistor device layer includes four piezoresistors for forming a Wheatstone bridge, and the four piezoresistors are symmetric to each other and isolated from each other through the microchannels.

[0011] The four metal electrodes provide sufficient interfaces for signal input and output, making the circuit connection on the chip more flexible and meeting the requirements of various circuit configurations. At the same time, the four metal electrodes are also convenient for multi-point measurement or differential measurement, thereby improving the accuracy and stability of the measurement. Since the Wheatstone bridge has the characteristics of high precision and high sensitivity, using four piezoresistors to form a Wheatstone bridge can achieve precise pressure measurement. The four symmetric piezoresistors have the same response characteristics when subjected to the same pressure, thus improving the measurement accuracy. At the same time, isolating these piezoresistors from each other through the microchannels can prevent electrical interference and thermal interference between them, further improving the stability and reliability of the measurement. In addition, the design of the microchannels can also reduce the size and weight of the device, making it more suitable for miniaturized and integrated application scenarios.

[0012] Optionally, the cross-beam etching region includes four square regions and a cross-beam structure; the four square regions are disposed on the periphery of the cross-beam structure; the depth of the square regions is 10 μm - 40 μm.

[0013] The four square regions are disposed on the periphery of the cross-beam structure, which not only increases the rigidity of the wafer and reduces the risk of deformation caused by external forces and process operations, but also makes the internal stress distribution of the wafer uniform, reduces quality problems caused by stress concentration, and ensures the chip performance and reliability. Providing a clear etching structure and depth for the four square regions helps to precisely control the etching degree, improving the consistency and carrier mobility between different chips on the wafer.

[0014] The second aspect of the present application provides a method for manufacturing a pressure sensor for manufacturing the pressure sensor described in the first aspect, and the method includes: Select a P-type double-polished SOI wafer as the double-polished SOI wafer substrate; wherein, the top layer of the double-polished SOI wafer substrate is a silicon device layer; the middle layer of the double-polished SOI wafer substrate is a silicon dioxide dielectric layer; the bottom layer of the double-polished SOI wafer substrate is a silicon substrate; Clean the double-polished SOI wafer substrate according to a pre-configured cleaning solution and cleaning conditions; Epitaxially grow an N-type 3C-SiC single crystal device layer on the silicon device layer to form a device layer; Etch the device layer using an inductively coupled plasma etching process or a reactive ion etching process to form a sensitive resistor device layer, an annular sealing region, and microchannels; The pre-processed metal electrodes and the device layer are treated by annealing to form ohmic contacts; A 3C-SiC single crystal device layer, a silicon device layer, a silicon dioxide dielectric layer, and a silicon substrate are etched from top to bottom in sequence by a deep silicon etching process to form a cross-beam etching region; The bottom of the silicon substrate is etched by a wet etching method to form a silicon pressure cavity and a beam film; The encapsulation glass is electrostatically sealed on the top of the device layer or the bottom of the silicon substrate.

[0015] In the above method, a 3C-SiC single crystal device layer is epitaxially grown on the silicon device layer as the device layer, greatly improving the high-temperature resistance characteristics of the pressure-sensitive chip and enabling it to maintain stable mechanical and electrical characteristics under high-temperature conditions. At the same time, the silicon dioxide dielectric layer is provided between the device layer and the silicon substrate, which can significantly reduce the leakage current between the device layer and the silicon substrate, increase the breakdown voltage threshold, and is suitable for high-temperature environments. The cross-beam etching region can generate a greater stress value under the same pressure, optimize the stress distribution, and improve the output sensitivity of the 3C-SiC pressure-sensitive chip. In addition, the 3C-SiC single crystal device layer is compatible with silicon dry and wet etching technologies to complete the processing of the pressure-sensitive diaphragm, and the process is stable, the etching is uniform, and the cost is low. It can also achieve the sealing forms of absolute pressure, differential pressure, and gauge pressure, as well as the encapsulation structures of top sealing and bottom sealing respectively.

[0016] Optionally, the step of cleaning the double-polished SOI wafer substrate according to the pre-configured cleaning solution and cleaning conditions includes: The double-polished SOI wafer substrate is cleaned with a sulfuric acid-hydrogen peroxide mixture at a temperature of 100-130 °C for 5-20 minutes to obtain a double-polished SOI wafer substrate after the first cleaning; the sulfuric acid-hydrogen peroxide mixture is a mixture of sulfuric acid and hydrogen peroxide with a ratio of 4:1; The double-polished SOI wafer substrate after the first cleaning is cleaned with a first mixture at a temperature of 65-80 °C for 5-10 minutes to obtain a double-polished SOI wafer substrate after the second cleaning; the first mixture is a mixture of ammonia water, hydrogen peroxide, and deionized water with a ratio of 1:1:5; The double-polished SOI wafer substrate after the second cleaning is cleaned with a second mixture at a temperature of 65-80 °C for 5-10 minutes to obtain a double-polished SOI wafer substrate after the third cleaning; the second mixture is a mixture of hydrochloric acid, hydrogen peroxide, and deionized water with a ratio of 1:1:6.

[0017] Due to the strong oxidizing property of the mixed solution of sulfuric acid and hydrogen peroxide, the double-polished SOI wafer substrate after the first cleaning can effectively remove the organic impurities adhering to the wafer surface. After the second cleaning, the ammonia water in the first mixed solution of the double-polished SOI wafer substrate can not only react with metal ions to form soluble metal hydroxides, but also adjust the charge state of the wafer surface, which is beneficial to the adsorption and reaction of chemicals in the subsequent steps. Hydrogen peroxide can further oxidize these impurities, thus effectively removing the metal ion contamination on the wafer surface. The addition of deionized water helps to dilute and evenly distribute the reactants, thereby improving the uniformity of the wafer surface. After the third cleaning, the hydrochloric acid in the second mixed solution of the double-polished SOI wafer substrate can react with the oxides on the wafer surface to form soluble salts, and hydrogen peroxide further oxidizes and removes the residual impurities, thus achieving deep cleaning, removing surface defects, and providing ideal substrate conditions for subsequent processing.

[0018] Optionally, the process gas for the inductively coupled plasma etching process or the reactive ion etching process is one or more of carbon tetrafluoride, sulfur hexafluoride, and oxygen.

[0019] Due to the strong chemical activity of carbon tetrafluoride, sulfur hexafluoride, and oxygen, the etching rate can be increased. By precisely controlling the types and ratios of the gases, fine pattern etching can be achieved. The mixed use of the process gases not only helps to ensure etching uniformity, but also enables selective etching of specific materials by selecting appropriate gas combinations; it also helps to stabilize the plasma state and reduce process instability problems.

[0020] Optionally, the process gas for the deep silicon etching process is one or more of octafluoroisobutene, carbon tetrafluoride, sulfur hexafluoride, oxygen, and argon.

[0021] The deep silicon etching process uses one or more of octafluoroisobutene, carbon tetrafluoride, sulfur hexafluoride, oxygen, and argon as the process gas, and has many advantages such as improving etching efficiency and uniformity, improving etching selectivity and surface quality, enhancing process control and stability, and broadening the process application range and flexibility.

[0022] Optionally, the silicon etchant in the wet etching method is potassium hydroxide solution or tetramethylammonium hydroxide solution.

[0023] Etching with potassium hydroxide solution or tetramethylammonium hydroxide solution can efficiently react with silicon, maintain the smoothness and integrity of the silicon surface, reduce the risk of equipment corrosion, is easy for waste liquid treatment, and the process parameters are easy to adjust.

[0024] Optionally, the steps of annealing the pre-processed metal electrode and the device layer include: Grow a metal electrode layer on the device layer based on the lift-off process; the material system of the metal electrode is titanium / platinum / gold or titanium / tungsten / gold; Place the device layer and the metal electrode in an annealing device with an atmosphere of vacuum, nitrogen or argon; Anneal the device layer and the metal electrode to form an ohmic contact between the device layer and the metal electrode; wherein, the annealing temperature is 700°C - 1100°C.

[0025] The above method deposits a metal electrode on the device layer by using the lift-off process, which can ensure that the metal electrode has good conductivity and compatibility with the device layer. The annealing method is used to process the metal electrode and the device layer, which can form a low-resistance ohmic contact between the device layer and the metal electrode and optimize the electrical performance.

[0026] From the above technical solutions, the present application provides a pressure sensor and a processing method. The chip includes: a silicon substrate, a silicon dioxide dielectric layer, a device layer, a metal electrode, and a packaging glass; the device layer includes a 3C-SiC single crystal device layer and a silicon device layer; the 3C-SiC single crystal device layer is disposed on the silicon device layer; the silicon device layer, the silicon dioxide dielectric layer, and the silicon substrate are connected in sequence; the device layer is etched to form a sensitive resistor device layer, an annular sealing area, and a microchannel; the sensitive resistor device layer is isolated from the annular sealing area through the microchannel; a cross-beam etching area is etched at the top center of the device layer, the silicon dioxide dielectric layer, and the silicon substrate; a silicon pressure cavity and a beam film are etched at the bottom of the silicon substrate; the metal electrode is disposed on the top of the device layer; the packaging glass is anodic bonded to the top of the device layer or the bottom of the silicon substrate to solve the problems of high temperature resistance and low sensitivity of the MEMS pressure sensor. Description of the Drawings

[0027] In order to more clearly illustrate the technical solutions of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, for those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0028] Figure 1 It is the planar process layout of the pressure sensor provided by the embodiment of the present application; Figure 2 It is the structural schematic diagram of the double-polished SOI wafer substrate in the pressure sensor processing method provided by the embodiment of the present application; Figure 3 It is the structural schematic diagram after epitaxially growing the 3C-SiC single crystal device layer in the pressure sensor processing method provided by the embodiment of the present application; Figure 4 Schematic diagram of the structure of the sensitive resistor device layer, the annular sealing area, and the microchannel in the pressure sensor processing method provided by the embodiment of the present application; Figure 5 Schematic diagram of the structure after forming ohmic contact in the pressure sensor processing method provided by the embodiment of the present application; Figure 6 Schematic diagram of the structure after forming the crossbeam etching area in the pressure sensor processing method provided by the embodiment of the present application; Figure 7 Schematic diagram of the structure of the silicon pressure cavity and the beam film in the pressure sensor processing method provided by the embodiment of the present application; Figure 8 Schematic diagram of the structure after electrostatically sealing the upper glass without a through hole in the pressure sensor provided by the embodiment of the present application; Figure 9 Schematic diagram of the structure after electrostatically sealing the upper glass with a through hole in the pressure sensor provided by the embodiment of the present application; Figure 10 Schematic diagram of the structure after electrostatically sealing the lower glass without a through hole in the pressure sensor provided by the embodiment of the present application; Figure 11 Schematic diagram of the structure after electrostatically sealing the lower glass with a through hole in the pressure sensor provided by the embodiment of the present application.

[0029] Illustration: Among them, 1 - silicon device layer; 2 - silicon dioxide dielectric layer; 3 - silicon substrate; 4 - 3C-SiC single crystal device layer; 5 - annular sealing area; 6 - microchannel; 7 - sensitive resistor device layer; 8 - metal electrode; 9 - crossbeam etching area; 10 - silicon pressure cavity; 11 - beam film; 12 - upper glass without a through hole; 13 - upper glass with a through hole; 14 - upper glass through hole; 15 - lower glass without a through hole; 16 - lower glass with a through hole; 17 - lower glass through hole. Detailed implementation manners

[0030] The embodiments will be described in detail below, and the examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following embodiments do not represent all implementation manners consistent with the present application. They are only examples of systems and methods consistent with some aspects of the present application.

[0031] Micro - Electro - Mechanical System (MEMS) is developed on the basis of microelectronics technology and is a high - tech electro - mechanical device that integrates technologies such as lithography, etching, doping, thin - film, LIGA, and precision machining. The piezoresistive pressure sensor processed based on MEMS technology has the advantages of low cost, high performance, and mass production, and is widely used in fields such as aerospace and automotive processing.

[0032] MEMS pressure sensors are mainly made of silicon materials. Commonly, there are two types of pressure sensor chips: those based on silicon PN - junction isolation technology and those based on SOI technology. Among them, the pressure sensor chip based on silicon PN - junction isolation technology has a lower cost. However, due to the limitation of the silicon PN - junction leakage current, its maximum application temperature is only 125°C. The pressure sensor chip based on SOI technology has more prominent high - temperature resistance performance due to material advantages, and its application temperature can reach 400°C, but it is difficult to exceed 450°C. With the continuous expansion of the sensor application field, for some special high - temperature usage environments, the pressure sensor chips based on silicon PN - junction isolation technology and those based on SOI technology cannot meet the requirements of high - temperature environments.

[0033] To meet the requirements of high - temperature environments, in related embodiments, a silicon carbide pressure sensor chip can be selected. Although the silicon carbide pressure sensor chip can be applied to high - temperature environments above 800°C, due to the immature MEMS processing method of silicon carbide, its chip processing cost is high, mass production is difficult, the repeatability and consistency are poor, and there is also a problem of low sensitivity, which affects the detection accuracy of the pressure sensor.

[0034] To solve the above problems, see Figures 1 - 11 , some embodiments of this application provide a pressure sensor, including: a silicon substrate 3, a silicon dioxide dielectric layer 2, a device layer, a metal electrode 8, and a packaging glass; The device layer includes a 3C - SiC single - crystal device layer 4 and a silicon device layer 1; the silicon device layer 1, the silicon dioxide dielectric layer 2, and the silicon substrate 3 are connected in sequence to serve as a double - polished SOI wafer substrate; the 3C - SiC single - crystal device layer 4 is disposed on the silicon device layer 1 to enhance the high - temperature resistance characteristics of the double - polished SOI wafer substrate; The device layer is etched to form a sensitive resistor device layer 7, an annular sealing area 5, and a micro - channel 6; the sensitive resistor device layer 7 is isolated from the annular sealing area 5 through the micro - channel 6; The top center of the device layer, the silicon dioxide dielectric layer 2, and the silicon substrate 3 is etched to form a cross - beam etching area 9 to generate a greater stress value under the same pressure; The bottom of the silicon substrate 3 is etched to form a silicon pressure cavity 10 and a beam film 11 to sense an external pressure signal; The metal electrode 8 is disposed on the top of the device layer to achieve electrical connection with the device layer; The encapsulation glass is anodically bonded to the top of the device layer or the bottom of the silicon substrate 3.

[0035] It should be understood that 3C-SiC, whose full name is cubic silicon carbide, is a wide-bandgap compound semiconductor material with a unique crystal structure and excellent properties. In the crystal structure, carbon atoms and silicon atoms are arranged at equal intervals to form a cubic lattice, and carbon atoms and silicon atoms are alternately arranged to form continuous Si-C bonds, having high hardness, high temperature resistance, thermal conductivity, high electron mobility, and good chemical stability. The 3C-SiC single-crystal device layer 4 greatly improves the high-temperature resistance characteristics of the pressure-sensitive chip and can maintain stable mechanical and electrical characteristics under high-temperature conditions. At the same time, a silicon dioxide dielectric layer 2 is provided between the device layer and the silicon substrate 3, which can greatly reduce the leakage current between the device layer and the silicon substrate 3 and improve the breakdown voltage threshold, being applicable to high-temperature environments.

[0036] The encapsulation glass can be borosilicate glass; the structure of the encapsulation glass is not unique. When the encapsulation glass is the non-through-hole upper glass 12 and the through-hole upper glass 13, the encapsulation glass is sealed to the top of the device layer through the annular seal; when the encapsulation glass is the non-through-hole lower glass 15 and the through-hole lower glass 16, the encapsulation glass is sealed to the bottom of the silicon substrate 3. To meet different chip packaging requirements. Compared with the flat diaphragm structure, the cross-beam etching region 9 can generate a greater stress value under the same pressure, optimize the stress distribution, and improve the output sensitivity of the chip.

[0037] In some embodiments, the thickness range of the 3C-SiC single-crystal device layer 4 is 500nm - 2000nm; the thickness range of the silicon device layer 1 is 20nm - 200nm; the thickness range of the silicon dioxide dielectric layer 2 is 200nm - 2000nm.

[0038] The 3C-SiC single-crystal device layer 4 with a thickness range of 500nm - 2000nm can not only effectively withstand harsh environments such as high temperature and high pressure to ensure the long-term stable operation of the device, but also be easily processed into the required shapes and sizes and integrated with other materials (such as silicon, silicon dioxide, etc.) to form a composite-structure microelectronic device.

[0039] The silicon device layer 1 with a thickness range of 20 nm - 200 nm can not only exhibit good electrical properties and power consumption characteristics, but also facilitate higher integration, enabling more electronic devices to be integrated on the same chip, thereby improving the functionality and performance of the entire system. In addition, within this thickness range, the doping concentration and distribution of the silicon device layer 1 can be more precisely controlled, and it also has good compatibility.

[0040] The silicon dioxide dielectric layer 2 with a thickness range of 200 nm - 2000 nm can not only effectively isolate adjacent electronic devices, prevent current leakage and signal interference, but also serve as a protective layer to prevent the device from being damaged by environmental factors such as moisture and oxygen, and extend the service life of the device. In addition, the silicon dioxide dielectric layer 2 can be flexibly applied to multi-layer structures and complex circuits, providing more degrees of freedom for device design and manufacturing.

[0041] In some embodiments, the number of the metal electrodes 8 is four, and the four metal electrodes 8 are disposed on the sensitive resistor device layer 7; the sensitive resistor device layer 7 includes four piezoresistors for forming a Wheatstone bridge, and the four piezoresistors are symmetric to each other and are isolated from each other through the microchannel 6.

[0042] It should be understood that the four piezoresistors (R1, R2, R3, R4) are used to convert the pressure signal into an electrical signal. The piezoresistors are isolated from the silicon substrate 3 through the silicon dioxide dielectric layer 2.

[0043] The four metal electrodes 8 provide sufficient interfaces for signal input and output, making the circuit connections on the chip more flexible and meeting the requirements of various circuit configurations. At the same time, the four metal electrodes 8 are also convenient for multi-point measurement or differential measurement, thereby improving the accuracy and stability of the measurement. Due to the high precision and high sensitivity of the Wheatstone bridge, using four piezoresistors to form a Wheatstone bridge can achieve precise measurement of pressure. The four symmetric piezoresistors have the same response characteristics when subjected to the same pressure, thus improving the measurement accuracy. At the same time, by isolating these piezoresistors from each other through the microchannel 6, electrical interference and thermal interference between them can be prevented, further improving the stability and reliability of the measurement. In addition, the design of the microchannel 6 can also reduce the size and weight of the device, making it more suitable for miniaturized and integrated application scenarios.

[0044] In some embodiments, the cross-beam etching region 9 includes four square regions and a cross-beam structure; The four square regions are disposed on the periphery of the cross-beam structure; the depth of the square regions is 10 μm - 40 μm.

[0045] It should be understood that the four square regions are etching regions. The four square regions are arranged on the peripheral side of the cross beam structure, which not only increases the rigidity of the wafer and reduces the deformation risk caused by external forces and process operations, but also makes the internal stress distribution of the wafer uniform, reduces the quality problems caused by stress concentration, and ensures the chip performance and reliability. Providing a clear etching structure and depth for the four square regions helps to precisely control the etching degree and improve the consistency and carrier mobility between different chips on the wafer.

[0046] Some embodiments of the present application further provide a method for manufacturing a pressure sensor, which is used to manufacture the pressure sensor described in the above embodiments. The method includes: S100: Select a P-type double-polished SOI wafer as the double-polished SOI wafer substrate.

[0047] Among them, the top layer of the double-polished SOI wafer substrate is a silicon device layer 1; the middle layer of the double-polished SOI wafer substrate is a silicon dioxide dielectric layer 2; the bottom layer of the double-polished SOI wafer substrate is a silicon substrate 3. The double-polished SOI wafer substrate is of P-type <100> crystal orientation. The thickness range of the silicon device layer 1 is 20nm - 200nm; the thickness range of the silicon dioxide dielectric layer 2 is 200nm - 2000nm; the thickness range of the silicon substrate 3 is 400μm - 800μm. As Figure 2 shown.

[0048] S200: Clean the double-polished SOI wafer substrate according to the pre-configured cleaning solution and cleaning conditions.

[0049] In some embodiments, the step of cleaning the double-polished SOI wafer substrate according to the pre-configured cleaning solution and cleaning conditions includes: Clean the double-polished SOI wafer substrate with a sulfuric acid-hydrogen peroxide mixture at a temperature of 100 - 130°C for 5 - 20 minutes to obtain the double-polished SOI wafer substrate after the first cleaning; the sulfuric acid-hydrogen peroxide mixture is a mixture of sulfuric acid and hydrogen peroxide with a ratio of 4:1; Clean the double-polished SOI wafer substrate after the first cleaning with a first mixture at a temperature of 65 - 80°C for 5 - 10 minutes to obtain the double-polished SOI wafer substrate after the second cleaning; the first mixture is a mixture of ammonia water, hydrogen peroxide and deionized water with a ratio of 1:1:5; Clean the double-polished SOI wafer substrate after the second cleaning with a second mixture at a temperature of 65 - 80°C for 5 - 10 minutes to obtain the double-polished SOI wafer substrate after the third cleaning; the second mixture is a mixture of hydrochloric acid, hydrogen peroxide and deionized water with a ratio of 1:1:6.

[0050] Due to the strong oxidizing property of the mixture of sulfuric acid and hydrogen peroxide, the double-polished SOI wafer substrate after the first cleaning can effectively remove the organic impurities adhering to the wafer surface. After the second cleaning, the ammonia in the first mixture of the double-polished SOI wafer substrate can not only react with metal ions to form soluble metal hydroxides, but also adjust the charge state of the wafer surface, which is beneficial to the adsorption and reaction of chemicals in the subsequent steps. Hydrogen peroxide can further oxidize these impurities, thus effectively removing the metal ion contamination on the wafer surface. The addition of deionized water helps to dilute and evenly distribute the reactants, thereby improving the uniformity of the wafer surface. After the third cleaning, the hydrochloric acid in the second mixture of the double-polished SOI wafer substrate can react with the oxides on the wafer surface to form soluble salts, and hydrogen peroxide further oxidizes and removes the residual impurities, thus achieving deep cleaning, removing surface defects, and providing ideal substrate conditions for subsequent processing.

[0051] S300: Epitaxially grow an N-type 3C-SiC single-crystal device layer 4 on the silicon device layer 1 to form a device layer.

[0052] Specifically, when epitaxially growing a layer of 3C-SiC single-crystal device layer 4 on the silicon device layer 1, epitaxial doping is carried out simultaneously, with a thickness of 500 nm - 2000 nm, a doping type of N-type, and a doping concentration of 1×10 18 -1×10 20 cm -3 ,as Figure 3 shown.

[0053] S400: Etch the device layer using an inductively coupled plasma etching process or a reactive ion etching process to form a sensitive resistor device layer 7, an annular sealing area 5, and a microchannel 6.

[0054] Specifically, before etching the device layer, photoresist can be used for protection at the bottom of the device layer and as an etching mask at the top for photolithography. First, etch the 3C-SiC single-crystal device layer 4, then etch the silicon device layer 1, stop etching at the silicon dioxide dielectric layer 2, and finally remove the photoresist.

[0055] In some embodiments, the process gas for the inductively coupled plasma etching process or the reactive ion etching process is one or more of carbon tetrafluoride, sulfur hexafluoride, and oxygen.

[0056] Due to the strong chemical activity of carbon tetrafluoride, sulfur hexafluoride, and oxygen, the etching rate can be increased. By precisely controlling the gas type and ratio, fine pattern etching can be achieved. The mixed use of the process gases not only helps to ensure etching uniformity, and by selecting a suitable gas combination, selective etching of specific materials can be achieved; it also helps to stabilize the plasma state and reduce process instability problems.

[0057] S500: The pre-processed metal electrode 8 and the device layer are processed by annealing to form an ohmic contact.

[0058] In some embodiments, the step of processing the pre-processed metal electrode 8 and the device layer by annealing includes: Growing a layer of metal electrode 8 on the device layer based on the lift-off process; the material system of the metal electrode 8 is titanium / platinum / gold or titanium / tungsten / gold.

[0059] It should be understood that the principle of the lift-off process is to first coat a photoresist on the substrate, and then form a specific pattern as a mask through photolithography processes such as exposure and development. Then, metal or other materials are deposited on the substrate, and finally, the patterned photoresist and the deposited layer thereon are removed together, just like "lifting off" or "peeling off", so as to leave the required patterned metal or other material structure on the substrate. In the embodiments of the present application, a layer of metal electrode 8 can be grown on the device layer by magnetron sputtering or electron beam evaporation. In the material system of the metal electrode 8, titanium can be selected from 10 - 50 nm, platinum can be selected from 50 - 500 nm, tungsten can be selected from 50 - 500 nm; gold can be selected from 200 - 1000 nm.

[0060] The device layer and the metal electrode 8 are placed in an annealing device with an atmosphere of vacuum, nitrogen or argon.

[0061] The device layer and the metal electrode 8 are annealed to form an ohmic contact between the device layer and the metal electrode 8; wherein, the annealing temperature is 700°C - 1100°C.

[0062] The above method deposits the metal electrode 8 on the device layer by using the lift-off process, which can ensure that the metal electrode 8 has good conductivity and compatibility with the device layer. Processing the metal electrode 8 and the device layer by annealing can form a low-resistance ohmic contact between the device layer and the metal electrode 8, optimizing the electrical performance.

[0063] S600: The 3C-SiC single crystal device layer 4, the silicon device layer 1, the silicon dioxide dielectric layer 2 and the silicon substrate 3 are etched from top to bottom in sequence by deep silicon etching process to form a cross-beam etching region 9.

[0064] Specifically, before etching, a photoresist can be used to protect the bottom of the silicon substrate 3, and a photoresist can be used as an etching mask on the top of the 3C-SiC single crystal device layer 4 for photolithography. When the total etching depth reaches 10 μm - 40 μm and stops, the photoresist is finally removed.

[0065] In some embodiments, the process gas for the deep silicon etching process is one or more of octafluoroisobutene, carbon tetrafluoride, sulfur hexafluoride, oxygen, and argon.

[0066] The deep silicon etching process uses one or more of octafluoroisobutene, carbon tetrafluoride, sulfur hexafluoride, oxygen, and argon as the process gas, and has many advantages such as improving etching efficiency and uniformity, improving etching selectivity and surface quality, enhancing process control and stability, and broadening the process application range and flexibility.

[0067] S700: Etch the bottom of the silicon substrate 3 by wet etching to form the silicon pressure cavity 10 and the beam film 11.

[0068] Specifically, before etching, the top of the silicon substrate 3 is also protected, and silicon nitride is used as a mask for the bottom of the silicon substrate 3. Then, anisotropic etching is performed on the silicon substrate 3 to form the silicon pressure cavity 10 and the beam film 11. The side of the silicon pressure cavity 10 can be a trapezoidal structure.

[0069] In some embodiments, the silicon etchant in the wet etching method is potassium hydroxide solution or tetramethylammonium hydroxide solution.

[0070] Etching with potassium hydroxide solution or tetramethylammonium hydroxide solution can react with silicon efficiently, maintain the smoothness and integrity of the silicon surface, reduce the risk of equipment corrosion, be easy for waste liquid treatment, and the process parameters are easy to adjust.

[0071] S800: Electrostatically bond the encapsulation glass on the top of the device layer or the bottom of the silicon substrate 3.

[0072] It should be understood that the device layer is disposed on the top of the etched wafer.

[0073] Example 1: As Figure 8 shown, when the encapsulation glass uses the through-hole-free upper glass 12, the method of electrostatic bonding is as follows: Stack the through-hole-free upper glass 12, the wafer, and the metal surface electrode plate on the working stage of the sealing machine in sequence.

[0074] Apply a sealing pressure of 0.05 - 0.5 MPa to make the materials in close contact.

[0075] Connect the wafer to the positive pole of the DC power supply through the heating plate, and connect the through-hole-free upper glass 12 to the negative pole of the DC power supply through the metal surface electrode.

[0076] The sealing voltage is applied to the wafer and the through-hole-free upper glass 12 respectively by the surface electrode pressing method.

[0077] Control the vacuum degree ≤ 1 - 5×10-4 Pa, raise the temperature to 350 - 520 °C within 1 - 2 h and keep it warm for 1 - 2 h.

[0078] Under constant temperature conditions, apply a sealing voltage of 500 - 2000 V for 30 - 120 min to complete electrostatic sealing.

[0079] Example 2: As Figure 9 shown, when the encapsulation glass uses the upper glass with through - holes 13, an upper glass through - hole 14 is opened in the middle of the upper glass with through - holes 13. The method of electrostatic sealing is as follows: Stack the upper glass with through - holes 13, the wafer, and the metal surface electrode plate on the working stage of the sealing machine in sequence.

[0080] Apply a sealing pressure of 0.05 - 0.5 MPa to make the materials in close contact.

[0081] Connect the wafer to the positive pole of the DC power supply through the heating plate, and connect the upper glass with through - holes 13 to the negative pole of the DC power supply through the metal surface electrode.

[0082] The sealing voltage adopts the surface - electrode pressure - applying method and is applied to the wafer and the upper glass with through - holes 13 respectively.

[0083] Control the vacuum degree ≤ 1 - 5×10 -4 Pa, raise the temperature to 350 - 520 °C within 1 - 2 h and keep it warm for 1 - 2 h.

[0084] Under constant temperature conditions, apply a sealing voltage of 500 - 2000 V for 30 - 120 min to complete electrostatic sealing.

[0085] Example 3: As Figure 10 shown, when the encapsulation glass uses the lower glass without through - holes 15, the method of electrostatic sealing is as follows: Stack the wafer, the lower glass without through - holes 15, and the metal surface electrode plate on the working stage of the sealing machine in sequence.

[0086] Apply a sealing pressure of 0.05 - 0.5 MPa to make the materials in close contact.

[0087] Connect the wafer to the positive pole of the DC power supply through the heating plate, and connect the lower glass without through - holes 15 to the negative pole of the DC power supply through the metal surface electrode.

[0088] The sealing voltage adopts the surface - electrode pressure - applying method and is applied to the wafer and the lower glass without through - holes 15 respectively.

[0089] Control the vacuum degree ≤ 1 - 5×10 -4 Pa, raise the temperature to 350 - 520 °C within 1 - 2 h and keep it warm for 1 - 2 h.

[0090] Under constant temperature conditions, apply a sealing voltage of 500 - 2000V for 30 - 120 minutes to complete electrostatic sealing.

[0091] Example 4: As Figure 11 shown, when the encapsulation glass uses the glass 16 with through - holes, a lower - glass through - hole 17 is opened in the middle of the glass 16 with through - holes. The method of electrostatic sealing is as follows: Stack the wafer, the glass 16 with through - holes, and the metal - faced electrode plate on the working stage of the sealing machine in sequence.

[0092] Apply a sealing pressure of 0.05 - 0.5 MPa to make the materials in close contact.

[0093] Connect the wafer to the positive pole of the DC power supply through a heating plate, and connect the glass 16 with through - holes to the negative pole of the DC power supply through the metal - faced electrode.

[0094] The sealing voltage adopts the surface - electrode pressing method and is applied to the wafer and the glass 16 with through - holes respectively.

[0095] Control the vacuum degree ≤ 1 - 5×10 -4 Pa, raise the temperature to 350 - 520 °C within 1 - 2 h and keep it warm for 1 - 2 h.

[0096] Under constant temperature conditions, apply a sealing voltage of 500 - 2000V for 30 - 120 minutes to complete electrostatic sealing.

[0097] In Examples 2 - 4 compared with Example 1, except for the following changed process parameters, the remaining process steps and process parameters are exactly the same as those in Example 1. As shown in Examples 1 - 4, the chips of the present application can select different electrostatic encapsulation methods to meet different chip encapsulation requirements.

[0098] As can be seen from the above technical solutions, the embodiments of the present application provide a pressure sensor and a processing method. The chip includes: a silicon substrate 3, a silicon dioxide dielectric layer 2, a device layer, a metal electrode 8, and a packaging glass; the device layer includes a 3C-SiC single crystal device layer 4 and a silicon device layer 1; the 3C-SiC single crystal device layer 4 is disposed on the silicon device layer 1; the silicon device layer 1, the silicon dioxide dielectric layer 2, and the silicon substrate 3 are sequentially connected; the device layer is etched to form a sensitive resistor device layer 7, an annular sealing region 5, and a microchannel 6; the sensitive resistor device layer 7 is isolated from the annular sealing region 5 through the microchannel 6; a cross beam etching region 9 is formed by etching the top center of the device layer, the silicon dioxide dielectric layer 2, and the silicon substrate 3; a silicon pressure cavity 10 and a beam film 11 are formed by etching the bottom of the silicon substrate 3; the metal electrode 8 is disposed on the top of the device layer; the packaging glass is anodically bonded to the top of the device layer or the bottom of the silicon substrate 3 to solve the problems of high temperature resistance and low sensitivity of MEMS pressure sensors.

[0099] For the similar parts between the embodiments provided in the present application, reference can be made to each other. The specific embodiments provided above are only several examples under the general concept of the present application and do not constitute a limitation on the protection scope of the present application. For those skilled in the art, any other embodiments extended based on the solutions of the present application without creative efforts belong to the protection scope of the present application.

Claims

1. A pressure sensor, characterized in that: include: Silicon substrate (3), silicon dioxide dielectric layer (2), device layer, metal electrode (8) and packaging glass; The device layer comprises a 3C-SiC single crystal device layer (4) and a silicon device layer (1); the 3C-SiC single crystal device layer (4) is arranged on the silicon device layer (1); the silicon device layer (1), the silicon dioxide dielectric layer (2) and the silicon substrate (3) are connected in sequence; The device layer is etched to form a sensitive resistor device layer (7), an annular sealing area (5) and a microchannel (6); the sensitive resistor device layer (7) is isolated from the annular sealing area (5) by the microchannel (6); The device layer, the silicon dioxide dielectric layer (2) and the top center of the silicon substrate (3) are etched to form a cross beam etching area (9); the bottom of the silicon substrate (3) is etched to form a silicon pressure cavity (10) and a beam membrane (11); The metal electrode (8) is arranged on the top of the device layer; and the encapsulation glass is anode-bonded on the top of the device layer or on the bottom of the silicon substrate (3).

2. The pressure sensor according to claim 1, characterized in that: The thickness of the 3C-SiC single crystal device layer (4) is in the range of 500nm-2000nm; the thickness of the silicon device layer (1) is in the range of 20nm-200nm; and the thickness of the silicon dioxide dielectric layer (2) is in the range of 200nm-2000nm.

3. The pressure sensor according to claim 1, characterized in that: The number of the metal electrodes (8) is four, and the four metal electrodes (8) are arranged on the sensitive resistor device layer (7); the sensitive resistor device layer (7) includes four pressure sensitive resistors for forming a Wheatstone bridge, and the four pressure sensitive resistors are symmetrical to each other and isolated from each other by the microchannel (6).

4. The pressure sensor according to claim 1, characterized in that: The cross beam etching area (9) comprises four square areas and a cross beam structure; The four square regions are arranged on the peripheral side of the cross beam structure; the depth of the square region is 10 μm-40 μm.

5. A pressure sensor processing method, characterized in that: For processing the pressure sensor according to any one of claims 1 to 4, the method comprises: A P-type double-polished SOI wafer is selected as a double-polished SOI wafer substrate; wherein the top layer of the double-polished SOI wafer substrate is a silicon device layer (1); the middle layer of the double-polished SOI wafer substrate is a silicon dioxide dielectric layer (2); and the bottom layer of the double-polished SOI wafer substrate is a silicon substrate (3); Cleaning the double-polished SOI wafer substrate according to a pre-configured cleaning solution and cleaning conditions; epitaxially growing an N-type 3C-SiC single crystal device layer (4) on the silicon device layer (1) to form a device layer; Etching the device layer using an inductively coupled plasma etching process or a reactive ion etching process to form a sensitive resistor device layer (7), an annular sealing region (5) and a microchannel (6); The pre-processed metal electrode (8) and the device layer are processed by annealing to form an ohmic contact; A deep silicon etching process is used to sequentially etch the 3C-SiC single crystal device layer (4), the silicon device layer (1), the silicon dioxide dielectric layer (2) and the silicon substrate (3) from top to bottom to form a cross beam etching area (9); Etching the bottom of the silicon substrate (3) by wet etching to form a silicon pressure cavity (10) and a beam membrane (11); The encapsulation glass is electrostatically sealed on the top of the device layer or the bottom of the silicon substrate (3).

6. The pressure sensor processing method according to claim 5, characterized in that: The step of cleaning the double-polished SOI wafer substrate according to the pre-configured cleaning solution and cleaning conditions includes: Using a sulfuric acid and hydrogen peroxide mixture at a temperature of 100-130° C. to clean the double-polished SOI wafer substrate for 5-20 minutes to obtain a double-polished SOI wafer substrate after initial cleaning; the sulfuric acid and hydrogen peroxide mixture is a mixture of sulfuric acid and hydrogen peroxide in a ratio of 4:1; Using a No. 1 mixed solution to clean the double-polished SOI wafer substrate after the primary cleaning at a temperature of 65-80° C. for 5-10 minutes to obtain a double-polished SOI wafer substrate after the secondary cleaning; the No. 1 mixed solution is a mixture of ammonia water, hydrogen peroxide and deionized water in a ratio of 1:1:5; The double-polished SOI wafer substrate after the second cleaning is cleaned at a temperature of 65-80°C for 5-10 minutes to obtain a double-polished SOI wafer substrate after the third cleaning; the second mixed solution is a mixture of hydrochloric acid, hydrogen peroxide and deionized water in a ratio of 1:1:

6.

7. The pressure sensor processing method according to claim 5, characterized in that: The process gas of the inductively coupled plasma etching process or the reactive ion etching process is one or more of carbon tetrafluoride, sulfur hexafluoride and oxygen.

8. The pressure sensor processing method according to claim 5, characterized in that: The process gas of the deep silicon etching process is one or more of octafluoroisobutylene, carbon tetrafluoride, sulfur hexafluoride, oxygen and argon.

9. The pressure sensor processing method according to claim 5, characterized in that: The silicon etchant in the wet etching method is potassium hydroxide solution or tetramethylammonium hydroxide solution.

10. The pressure sensor processing method according to claim 5, characterized in that: The step of treating the pre-processed metal electrode (8) and the device layer by annealing comprises: A layer of metal electrode (8) is grown on the device layer based on a lift-off process; the material system of the metal electrode (8) is titanium / platinum / gold or titanium / tungsten / gold; Placing the device layer and the metal electrode (8) in an annealing device with a vacuum, nitrogen or argon atmosphere; The device layer and the metal electrode (8) are subjected to an annealing treatment so as to form an ohmic contact between the device layer and the metal electrode (8); wherein the annealing temperature is 700° C.-1100° C.

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