Instruction set control method for discrete semiconductor testing

Abstract

The invention relates to the technical field of discrete semiconductor testing, and discloses an instruction set control method for discrete semiconductor testing, which comprises the following steps: packaging test steps and parameters of a tested device into an instruction set through an upper computer, and writing the instruction set into a memory of a lower computer. When the test starts, the upper computer sends a starting instruction, the lower computer analyzes and executes an instruction set in the memory, the corresponding hardware board card is operated to complete a test item, and finally result data is stored to a specified memory address and a completion flag bit is returned to the upper computer. And after receiving the completion mark, the upper computer reads and displays the test result in real time. According to the method, high-speed data transmission and parallel testing of multiple hardware board cards are achieved through PCIE driving, the testing efficiency, stability and anti-jamming capability are remarkably improved, the testing cost is reduced, and the method is suitable for the automatic testing process of various discrete semiconductor devices.

Description

Technical Field

[0001] This application relates to the field of discrete semiconductor testing technology, and more specifically, to an instruction set control method for discrete semiconductor testing. Background Art

[0002] In the semiconductor manufacturing process, the testing of discrete devices (such as diodes, transistors, triodes, MOS transistors, etc.) is a key link to ensure product quality and performance. Traditional testing methods usually rely on fixed instructions that need to be written to the memory of the lower computer one by one through the serial port or network port, and execute responses one by one after a test request and return the results, which leads to problems such as low execution efficiency and long response time in complex testing environments.

[0003] Existing upper computers control testing equipment using serial port and network port communication methods. Among them, serial port communication: the compatibility between different devices is poor, the communication protocol is complex, and the development difficulty is high; when multiple devices work together, it is difficult to achieve precise clock synchronization between the serial port and the network port, affecting the overall coordination of the system, the data is easily tampered with, the anti-electromagnetic interference ability is weak, and the test instructions are sent and responded one by one, resulting in slow speed.

[0004] Therefore, an instruction set control method for discrete semiconductor testing is expected. Summary of the Invention

[0005] To solve the above technical problems, this application is proposed. Embodiments of this application provide an instruction set control method for discrete semiconductor testing, which uses a PCIE driver to achieve high-speed data transmission and parallel testing of multiple hardware boards, significantly improving the testing efficiency, stability, and anti-interference ability, reducing the testing cost, and being applicable to the automated testing processes of various discrete semiconductor devices.

[0006] According to one aspect of this application, there is provided an instruction set control method for discrete semiconductor testing, including: the upper computer packages test steps and parameters into an instruction set based on the test requirements of the device under test; the upper computer writes the instruction set into the memory of the lower computer; the upper computer sends a start test instruction to the lower computer; after receiving the start test instruction, the lower computer parses the instruction set from its memory and operates the hardware board based on the indication of the instruction set to execute each test item to obtain test result data; after the execution of the instruction set is completed, the lower computer saves the test result data to a pre-specified memory address and sends a completion flag bit to the upper computer; after detecting the completion flag bit, the upper computer reads the test result data from the pre-specified memory address and displays the test result data in real time on the upper computer interface.

[0007] In the above instruction set control method for discrete semiconductor testing, the host computer writes the instruction set into the memory of the slave computer, including: the host computer writes the instruction set into the memory of the slave computer through a PCIE card.

[0008] In the above instruction set control method for discrete semiconductor testing, the host computer writes the instruction set into the memory of the slave computer, including: initializing the driver of the PCIE card; the host computer writes the instruction set into the memory area of the PCIE card through the driver program of the PCIE card; the PCIE card writes it into the memory of the slave computer based on the routing information of the instruction set.

[0009] In the above instruction set control method for discrete semiconductor testing, the PCIE card writes the instruction set into the memory of the slave computer based on the routing information of the instruction set, including: the PCIE card sends each instruction in the instruction set to the corresponding hardware board based on the routing information of the instruction set; the hardware board issues each instruction in the instruction set to the memory of the slave computer.

[0010] In the above instruction set control method for discrete semiconductor testing, the host computer writes the instruction set into the memory of the slave computer, and further includes: the host computer divides the instruction set into multiple data packets and calculates a check code for each data packet to obtain multiple data packets with check codes; the host computer issues the multiple data packets with check codes to the slave computer one by one; after receiving each data packet with a check code, the slave computer performs content verification on each data packet based on the check code; after completing the data packet verification, it sends a response signal to the host computer to inform the reception status of the data packet.

[0011] In the above instruction set control method for discrete semiconductor testing, the host computer divides the instruction set into multiple data packets and calculates a check code for each data packet to obtain multiple data packets with check codes, including: extracting the MTU value of the PCIE card; extracting the buffer size and memory bandwidth value of the slave computer; evaluating the complexity of the instruction set and calculating the size of the instruction set; based on the MTU value, the buffer size, the memory bandwidth value, the complexity of the instruction set, and the size of the instruction set, recommending the maximum payload size of a fixed data packet.

[0012] In the above instruction set control method for discrete semiconductor testing, based on the MTU value, the buffer size, the memory bandwidth value, the complexity of the instruction set, and the size of the instruction set, recommending the maximum payload size of a fixed data packet, including: recommending the maximum payload size of a fixed data packet with the following formula, and the formula is:

[0013]

[0014] where is the MTU value, is the buffer size, is the memory bandwidth value, is the maximum latency allowed by the system, is the size of the instruction set, is the protocol header overhead, is the buffer reservation ratio, represents the complexity factor of the instruction set, represents the minimum value function, represents the maximum payload size of a fixed data packet.

[0015] In the above instruction set control method for discrete semiconductor testing, the host computer writes the instruction set into the memory of the slave computer, and further includes: reducing the copy overhead from the buffer to the memory during data transmission through the buffer-memory zero-copy mechanism of the header.

[0016] In the above instruction set control method for discrete semiconductor testing, reducing the copy overhead from the buffer to the memory during data transmission through the buffer-memory zero-copy mechanism of the header includes:

[0017] Define the buffer as a circular linked list, where the size of each table in the circular linked list is and the number of loops is Then, obviously, there is ;

[0018] Set the size of each table while corresponding to the memory bandwidth value and the maximum latency allowed by the system Then perform buffer-memory pre-allocation mapping. Specifically, let

[0019]

[0020]

[0021] where, is the ratio of the protocol header overhead to the MTU value, is the ratio of the size of each table to the memory bandwidth value, where, ;

[0022] Considering the socket correspondence between the table size and the maximum latency allowed by the system There should be:

[0023]

[0024] And the corresponding coefficient should satisfy such that tends to one, that is:

[0025] 。

[0026] Compared with the prior art, the instruction set control method for discrete semiconductor testing provided by this application aims to solve the problems of low efficiency and long response time caused by transmitting test instructions one by one through the serial port or network port in the prior art. This method encapsulates the test steps and parameters of the device under test into an instruction set by the host computer and writes it into the memory of the lower computer. At the start of the test, the host computer sends a start instruction, and the lower computer parses and executes the instruction set in the memory, operates the corresponding hardware board to complete the test item, and finally saves the result data to the specified memory address and returns a completion flag to the host computer. After receiving the completion flag, the host computer reads and displays the test results in real time. This method uses the PCIE driver to achieve high-speed data transmission and parallel testing of multiple hardware boards, significantly improving the test efficiency, stability, and anti-interference ability, reducing the test cost, and is applicable to the automated test processes of various discrete semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] By describing the embodiments of the present application in more detail in conjunction with the accompanying drawings, the above and other objects, features, and advantages of the present application will become more apparent. The accompanying drawings are used to provide a further understanding of the embodiments of the present application, and constitute a part of the specification, and are used to explain the present application together with the embodiments of the present application, and do not constitute a limitation to the present application. In the accompanying drawings, the same reference numerals generally represent the same components or steps.

[0028] Figure 1 FIG. is a schematic flow chart of an instruction set control method for discrete semiconductor testing according to an embodiment of the present application.

[0029] Figure 2 FIG. is a schematic flow chart of S2 in the instruction set control method for discrete semiconductor testing according to an embodiment of the present application.

[0030] Figure 3 FIG. is a schematic flow chart of S23 in the instruction set control method for discrete semiconductor testing according to an embodiment of the present application.

[0031] Figure 4 FIG. is a schematic architecture diagram of an instruction set control method for discrete semiconductor testing according to an embodiment of the present application.

[0032] Figure 5 FIG. is another schematic flow chart of S2 in the instruction set control method for discrete semiconductor testing according to an embodiment of the present application.

[0033] Figure 6 FIG. is a schematic flow chart of S24 in the instruction set control method for discrete semiconductor testing according to an embodiment of the present application.

[0034] Figure 7 Schematic diagram of the communication process of the instruction set control method for discrete semiconductor testing according to an embodiment of the present application.

[0035] Figure 8 Schematic diagram of the test request process of the instruction set control method for discrete semiconductor testing according to an embodiment of the present application. Detailed implementation manners

[0036] Hereinafter, exemplary embodiments according to the present application will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. It should be understood that the present application is not limited by the exemplary embodiments described herein.

[0037] In view of the above technical problems, the present application provides an instruction set control method for discrete semiconductor testing, as Figure 1 shown. The instruction set control method for discrete semiconductor testing includes: S1, the host computer encapsulates test steps and parameters into an instruction set based on the test requirements of the device under test; S2, the host computer writes the instruction set into the memory of the slave computer; S3, the host computer sends a start test instruction to the slave computer; S4, after receiving the start test instruction, the slave computer parses the instruction set from its memory and operates the hardware board based on the indication of the instruction set to execute each test item to obtain test result data; S5, after the instruction set is executed, the slave computer saves the test result data to a pre-specified memory address and sends a completion flag bit to the host computer; S6, after detecting the completion flag bit, the host computer reads the test result data from the pre-specified memory address and displays the test result data in real time on the host computer interface.

[0038] Specifically, in step S1, the host computer first encapsulates all test steps and parameters (such as voltage, current, gear, test time, waiting time, discharge time, measurement mode, etc.) into a series of instruction sets according to the test requirements of the device under test (such as the forward voltage, reverse breakdown voltage, reverse current, etc. of a diode). Each test item may include one or more instruction sets.

[0039] Taking diode testing as an example, it is first necessary to clarify the specific test items, such as forward voltage, reverse breakdown voltage, and reverse current, etc. These test items determine the specific content of the test steps and the required parameters. For example, when testing the forward voltage of a diode, a specific current value needs to be set and the corresponding voltage response measured; while when testing the reverse breakdown voltage, the voltage needs to be gradually increased until a specific current threshold is reached. Each test step contains multiple parameters, such as current, voltage, gear, test time, waiting time, and discharge time, etc. Next, the host computer will generate a corresponding instruction set according to the specific requirements of these test items. This instruction set is not just a simple command sequence; it also includes operation instructions for the hardware board. For example, for the above diode testing, the host computer will assemble all the parameter information of each test item into an instruction set, and the instruction set for each test item may contain 8 bytes of data. These instruction sets will be written into the memory of the lower computer for subsequent execution. Specifically, the host computer creates a test thread TestThread, which is responsible for parsing all the parameters of each test item and converting them into an instruction format suitable for hardware board operation. For example, for forward voltage testing, the instruction set will contain commands to set a specific current value and instructions to start measurement and record the results.

[0040] Specifically, in step S2, the host computer writes the complete instruction set into the memory of the lower computer (usually the control system of the test device) through a high-speed communication method such as a PCIE card. In a specific embodiment, the host computer writes the instruction set into the memory of the lower computer, including: the host computer writes the instruction set into the memory of the lower computer through a PCIE card. PCIE is a high-speed serial computer expansion bus standard that can provide higher bandwidth and lower latency than traditional serial ports or network ports, which makes it an ideal choice. For example, during diode testing, the host computer needs to transmit instruction sets containing test items such as forward voltage and reverse breakdown voltage to the lower computer. These instruction sets not only contain specific test parameters but also involve operation instructions for the hardware board.

[0041] In a specific embodiment, as Figure 2 shown in S2, the host computer writes the instruction set into the memory of the lower computer, including: S21, initializing the driver of the PCIE card; S22, the host computer writes the instruction set into the memory area of the PCIE card through the driver program of the PCIE card; S23, the PCIE card writes it into the memory of the lower computer based on the routing information of the instruction set.

[0042] Specifically, the host computer will first initialize the driver program of the PCIE card. In this way, it can be ensured that the PCIE card is in the correct state and can receive and process data from the host computer. After initialization, the host computer will write the instruction set into the memory area of the PCIE card through the driver program of the PCIE card. This memory area serves as a temporary storage area for caching data to be transmitted to the lower computer. Considering that the instruction set may be very large, especially when there are many test items, the high-bandwidth characteristic of the PCIE card ensures that data can be transmitted quickly and stably.

[0043] Next, the PCIE card will forward it to the corresponding hardware board according to the routing information in the instruction set. The routing information here is similar to an address table, indicating which hardware board each instruction should be sent to. For example, when testing a diode, some instructions may need to be sent to the board responsible for current regulation, while others need to be sent to the board responsible for voltage measurement. The PCIE card accurately distributes the instructions to the specified hardware board by parsing this routing information. After receiving the instructions, the hardware board will further write them into the memory of the lower computer for subsequent execution.

[0044] In a specific embodiment, as Figure 3 shown in S23, the PCIE card writes it into the memory of the lower computer based on the routing information of the instruction set, including: S231, the PCIE card sends each instruction in the instruction set to the corresponding hardware board based on the routing information of the instruction set; S232, the hardware board distributes each instruction in the instruction set to the memory of the lower computer.

[0045] In a specific embodiment, as Figure 4 shown, check whether the communication between the PC and each hardware board is normal, call the written test process of the device under test (including multiple test items), send the instruction sets of PCIE and physical hardware (voltage and current boards, calibration boards) to the PCIE card through the PC, and the PCIE card forwards them to the corresponding hardware board set through different channels and different stations in the instruction, for example, station 1, 0x01 is forwarded to the calibration board of the first set of hardware boards.

[0046] Throughout the process, the packet segmentation and verification mechanism also plays a crucial role. To ensure the integrity of data transmission, the host computer will split the instruction set into multiple smaller data packets and calculate the check code for each data packet. This can effectively prevent errors or losses of data during transmission. Once all data packets have been successfully sent and confirmed error-free, the lower computer can start executing the instruction set. This mechanism not only improves the reliability of data transmission but also enhances the fault tolerance of the system.

[0047] In a specific embodiment, asFigure 5 As shown, the host computer writes the instruction set into the memory of the slave computer, and further includes: S24, the host computer divides the instruction set into multiple data packets and calculates a checksum for each data packet to obtain multiple data packets with checksums; S25, the host computer sequentially sends the multiple data packets with checksums to the slave computer; S26, after receiving each data packet with a checksum, the slave computer performs content verification on each data packet based on the checksum; S27, after completing the data packet verification, send a response signal to the host computer to inform the reception status of the data packet.

[0048] Specifically, first, when the host computer sends an instruction set, instead of directly sending the original instruction data stream, it divides the instruction set into multiple data packets and defines a clear protocol structure for each data packet. The protocol structure should at least include the following fields: Packet header: Identifies the start of the data packet and contains information such as packet type (instruction packet, control packet, etc.) and version number. Packet sequence number: Assigns a unique sequence number to each data packet for the slave computer to perform data packet recombination and sequence verification. Data length: Indicates the length of the valid data in the current data packet. Checksum (e.g., CRC): A checksum calculated based on the data packet content for data integrity verification. Packet tail: Identifies the end of the data packet.

[0049] Here, it should be understood that the instruction set contains all test steps and parameters. The host computer divides the complete instruction set into multiple data packets according to the segmentation strategy. The segmentation strategy needs to consider factors such as the maximum transmission unit (MTU) of the PCIE channel, the overhead of the data packet (header, checksum, etc.), and the processing capacity of the receiving end. Specifically, it is necessary to determine a suitable maximum payload size (Payloadsize) for the data packet. For example, 512 bytes or 1024 bytes can be selected as the maximum length of the data packet payload. Selecting a suitable size requires a trade-off between efficiency and overhead: if the packet is too small, the overhead of the packet header accounts for a high proportion, reducing the effective data transmission rate; if the packet is too large, the amount of data to be retransmitted in case of an error is also large, and it may increase the pressure on the receiving end buffer. It can be determined by referring to the MTU of the PCIE and the memory resources of the slave computer.

[0050] It should be understood that MTU refers to the size limit of the largest data packet that a network protocol can transmit, including the packet header and data payload. For PCIE, although it is not a network protocol in the traditional sense, there is a similar concept to MTU, which refers to the maximum data payload size transmitted in one go in the PCIE transaction layer. The MTU of PCIE is usually much larger than that of networks such as Ethernet and can support larger data packets. Default MTU and configurability: The MTU value of PCIE is usually preset by hardware and drivers and may have a default value. In some cases, the driver or configuration of the PCIE device may allow adjustment of the MTU size, but this is not common, and usually the default larger value can be used. Theoretically, if the data packet size exceeds the MTU of PCIE, the PCIE protocol stack will automatically perform fragmentation and reassembly, but this will increase the complexity and overhead of protocol processing and reduce efficiency. Therefore, the host computer divides the instruction set into multiple data packets.

[0051] When performing the division, the memory resources of the lower computer need to be considered, including: the size of the receive buffer and the memory bandwidth limit. Among them, the size of the receive buffer: The lower computer needs to have enough memory to receive and cache data packets from the host computer. If the data packet is too large and the receive buffer of the lower computer is small, it may cause buffer overflow, data loss, or more frequent data processing, affecting real-time performance. Memory bandwidth limit: Even if there is enough memory space, if the memory bandwidth of the lower computer is limited, processing large data packets will become a bottleneck. Frequent reading and writing of large data packets will occupy a large amount of memory bandwidth and affect the performance of the lower computer in processing other tasks.

[0052] When performing segmentation, it is also necessary to balance efficiency and overhead. Disadvantages of small data packets: High header overhead: If the Payload of a data packet is very small but the header size is fixed, then the proportion of header overhead will be very high, reducing the effective data transmission rate. For example, if the Payload is 50 bytes and the header is 20 bytes, only 50 / (50 + 20) = 71% of the bandwidth is used to transmit actual instruction data, wasting 29% of the bandwidth on the header. Increased processing overhead: Sending and receiving a large number of small data packets will increase the number of processing times in the protocol stacks of the host computer and the slave computer. For example, more interrupt handling, checksum calculations, etc., thus increasing the burden on the CPU and reducing the overall efficiency. Disadvantages of large data packets: High retransmission cost: If a data packet is very large, once an error occurs during transmission, the entire large data packet needs to be retransmitted, with a higher retransmission cost and lower efficiency. High buffer pressure: The receiving end needs a larger buffer to temporarily store large data packets, requiring more memory resources. If the network condition is poor and data packets pile up, it may lead to buffer overflow or increased latency. May exceed memory limit: If the instruction set is very large, after being segmented into overly large data packets, a single data packet may exceed the memory block size that the slave computer can quickly process, resulting in performance degradation.

[0053] In a specific embodiment, as Figure 6 shown, in S24, the host computer segments the instruction set into multiple data packets and calculates checksum codes for each data packet to obtain multiple data packets with checksum codes, including: S241, extracting the MTU value of the PCIe card; S242, extracting the buffer size and memory bandwidth value of the slave computer; S243, evaluating the complexity of the instruction set and calculating the size of the instruction set; S244, based on the MTU value, the buffer size, the memory bandwidth value, the complexity of the instruction set, and the size of the instruction set, recommending the maximum payload size of a fixed data packet.

[0054] In a specific embodiment, based on the MTU value, the buffer size, the memory bandwidth value, the complexity of the instruction set, and the size of the instruction set, recommending the maximum payload size of a fixed data packet includes: recommending the maximum payload size of a fixed data packet using the following formula:

[0055]

[0056] where is the MTU value, is the buffer size, is the memory bandwidth value, is the maximum delay allowed by the system, is the size of the instruction set, is the protocol header overhead, is the buffer reservation ratio. Represents the complexity factor of the instruction set, Represents the minimum value function, Represents the maximum payload size of a fixed data packet.

[0057] Specifically, the maximum payload size of a fixed data packet should be close to but not exceed the MTU. For example, selecting a Payload size of 4076 bytes (or a close value of 2048 / 4096 bytes) can maximize the utilization of the PCIE MTU, reduce the possibility of data packet fragmentation, increase the amount of data transmitted in a single transmission, thereby improving bandwidth utilization and transmission efficiency. At the same time, 20 bytes of header space is reserved for control information and verification, ensuring the reliability of data transmission. At the same time, according to research findings, in practical applications, if the instruction set is very large and complex, the payload size also needs to be limited. Therefore, the complexity factor of the instruction set is further introduced , where, , at medium complexity , if the instruction complexity increases, the complexity factor of the instruction set will further increase to rebalance the performance.

[0058] The buffer size and buffer reservation ratio are also considered in the above formula to ensure that the Payload size will not be set too large, resulting in the risk of buffer overflow when buffer resources are limited. At the same time, in the above formula, the bandwidth delay limit is also considered. The maximum payload size is limited by the memory bandwidth value, the maximum delay allowed by the system, and the size of the instruction set to ensure sufficient bandwidth.

[0059] In another embodiment of the present application, when the host computer writes the instruction set into the memory of the lower computer, it further includes: reducing the copy overhead from the buffer to the memory during data transmission through the buffer-memory zero-copy mechanism of the header.

[0060] Preferably, the copy overhead from the buffer to the memory during data transmission can be reduced through the buffer-memory zero-copy mechanism of the header. That is, since the header usually includes different types of control data such as metadata, control fields, and identifiers, different types of control data can be used as sockets to utilize the buffer. In this case, the buffer is first defined as a circular linked list, where it is assumed that the size of each table in the circular linked list is , and the number of loops is , then obviously .

[0061] Here, in order to effectively utilize the circular linked list based on the delay time allowed by the system, that is, to parse the header in the buffer through the delay time allowed by the system to avoid the overhead of dynamically allocating memory during runtime, the size of each table can be set Simultaneously corresponding to the memory bandwidth value and the maximum latency allowed by the system so that buffer-memory pre-allocation mapping can be performed. Specifically, let

[0062]

[0063]

[0064] wherein is the ratio of the protocol header overhead to the MTU value, is the ratio of the size of each table to the memory bandwidth value;

[0065] Obviously, in order to achieve memory redundancy and avoid buffer overflow, there should be On the other hand, in order to implement the circular linked list as a lock-free circular queue, that is, considering the socket correspondence between the table size and the maximum latency allowed by the system there should be:

[0066]

[0067] And the corresponding coefficient should satisfy such that tends to one, that is:

[0068]

[0069] In this way, the efficient buffer-memory zero-copy storage of the header can be achieved through the circular linked list mechanism of the buffer, so as to obtain high packet processing efficiency under the buffer-memory hierarchical storage architecture.

[0070] Then, the host computer instruction set is packetized and sent down with verification. The host computer software packetizes the complete instruction set according to the defined packet protocol and calculates the checksum for each packet. Then, the host computer sends these packets with checksum to the lower computer one by one through the PCIE driver. The packet sending process is sequential, and the sequence numbers of the sent packets are recorded.

[0071] Next, the lower computer receives and verifies the packets. The lower computer receives the packets from the host computer through the PCIE driver. For each received packet, the lower computer first judges the integrity of the packet according to the packet header and packet tail, and then verifies the packet content according to the checksum.

[0072] Finally, after the lower computer completes the data packet verification, it needs to send an acknowledgment signal to the upper computer to inform the reception status of the data packet: Verification successful (ACK): If the checksum is correct, the lower computer sends an acknowledgment (ACK) packet, which contains the sequence number of the successfully received data packet. Verification failed (NACK): If the checksum is incorrect, the lower computer sends a negative acknowledgment (NACK) packet, which contains the sequence number of the data packet that failed to be received. Timeout retransmission: After the upper computer sends a data packet, it starts a timer. If it does not receive an ACK acknowledgment from the lower computer before the timer times out, or receives a NACK acknowledgment, the upper computer will retransmit the data packet with the corresponding sequence number. The number of retransmissions can be set with an upper limit to avoid infinite retransmissions.

[0073] Here, according to the sequence number of the received data packet, the lower computer reorganizes the instruction data segments in sequence to restore the complete instruction set. After all data packets are successfully received and reorganized, the lower computer can perform a global integrity check on the complete instruction set (for example, generating a digest of the original instruction set using a hash algorithm and transmitting the digest information in the data packet, and recalculating and comparing the digest after the lower computer reorganizes). Only when the integrity verification passes does the lower computer consider that the instruction set has been successfully issued and is ready to execute the subsequent test process.

[0074] Specifically, in step S3, the upper computer sends a start test instruction to the lower computer. In this process, it is necessary to accurately transfer the instruction to the lower computer and ensure that the lower computer can correctly parse and execute these instructions to efficiently complete various test tasks. Specifically, the process of sending the start test instruction usually involves the following steps. First, the upper computer establishes a stable communication connection with the lower computer through a PCIe card. This connection not only ensures high-speed and low-latency data transmission but also provides a reliable channel for sending control instructions. Then, the upper computer constructs a start test instruction packet in a specific format, which contains necessary control information such as a test sequence number, a timestamp, and some checksum codes. These information helps the lower computer correctly identify and process the instruction. Taking a specific diode test scenario as an example, assume that all instruction sets have been transmitted and the hardware board has been initialized according to the requirements of the instruction set. At this time, the upper computer sends a start test instruction packet to the lower computer. This instruction packet may contain the following content: a flag bit indicating that this is a start test instruction, a unique sequence number used to track the instruction, and a timestamp recording the sending time point. In addition, to ensure data integrity and accuracy, a checksum code is also attached so that the lower computer can verify it after receiving the instruction.

[0075] Specifically, in step S4, after receiving the start test instruction, the lower computer parses the instruction set from its memory and operates the hardware board based on the instructions in the instruction set to execute each test item to obtain test result data. It should be understood that after the upper computer successfully writes the instruction set into the memory of the lower computer and sends the start test instruction, the lower computer will immediately enter the parsing phase. The key to this phase is to correctly identify and process the instruction set from the upper computer. To ensure the integrity and accuracy of data transmission, the upper computer divides the instruction set into multiple data packets and calculates a checksum for each data packet. The purpose of doing this is to prevent errors or loss of data during transmission. When the lower computer receives these data packets with checksums, it will perform checks one by one to ensure that the content of each data packet is correct. If the check of a certain data packet fails, the lower computer will send an error report to the upper computer, requesting retransmission of that data packet.

[0076] Taking diode testing as an example, all instruction sets have been transmitted in the previous steps, and the hardware board has been initialized according to the requirements of the instruction set. At this time, the lower computer reads the pre-stored instruction set from its memory and starts to parse these instructions. Each instruction set may contain multiple test items, such as forward voltage, reverse breakdown voltage, etc. The parameter information of each test item (such as current value, voltage value, test time, etc.) is encapsulated in one or more instruction sets. The lower computer sets the corresponding hardware board according to the parameters in these instruction sets and prepares to execute the test.

[0077] Next, the lower computer distributes each instruction to the corresponding hardware board according to the routing information in the instruction set. For example, when testing the forward voltage, the lower computer sends the instruction to set a specific current value to the board responsible for current regulation; while when testing the reverse breakdown voltage, the instruction to gradually increase the voltage until a specific current threshold is reached needs to be sent to the board responsible for voltage regulation. After receiving the instruction, each hardware board will execute the test task according to the predetermined operation steps and record the corresponding test results.

[0078] In a specific embodiment, as Figure 7 shown, the parameter instruction sets such as voltage, current, gear, measurement time, test mode, etc. corresponding to each set of hardware are sent to the memory of the lower computer according to the negotiated mode and wait for testing. The upper computer only needs to send a test start instruction, and the lower computer will execute and return the test results after parsing the content of the instruction set. According to the specified number of executions of the test, the lower computer performs actions. The lower computer does not need to update the instruction set in its memory for subsequent executions, but only needs to repeat the test until the test is completed. The upper computer issues instructions to read different types of data and reads them at the corresponding lower computer addresses. The upper computer saves the test data results to the database in real time.

[0079] Specifically, in step S5, after the instruction set is executed, the lower computer saves the test result data to a pre-specified memory address and sends a completion flag bit to the upper computer.

[0080] In a specific embodiment, when the lower computer completes all test items according to the instruction set, it saves the generated test result data to a pre-specified memory address in a predetermined format. This memory address is set by the upper computer during the test initialization phase, ensuring the consistency and traceability of the data storage location. For example, during the diode test, after the tests for forward voltage, reverse breakdown voltage, etc. have been completed, the lower computer saves the results of each test item (such as the specific voltage and current values measured) to the corresponding memory address. These addresses are usually associated with the test item number or name for easy subsequent data reading and analysis. To ensure the integrity and accuracy of the data, the lower computer calculates a checksum and stores the checksum along with the test result data when saving it. The purpose of this is to prevent errors or loss of data during storage or transmission. Once the data is saved, the lower computer generates a completion flag bit and sends this flag bit to the upper computer through the PCIE card. This completion flag bit is a clear signal indicating that all test tasks have been successfully completed and the test result data is ready for the upper computer to read. When the data for all test items has been successfully saved, the lower computer generates a completion flag bit and sends it to the upper computer. This completion flag bit can be a simple boolean value (such as 1 indicating completion) or a more complex structure containing more information about the test status (such as test time, device number, etc.). After receiving this flag bit, the upper computer knows that the test has been completed and can start reading the test result data from the specified memory address.

[0081] In this way, the reliability and integrity of the test results can be ensured. There are many drawbacks to the traditional method of transmitting test results item by item through serial ports or network ports, such as slow transmission speed, susceptibility to electromagnetic interference, and difficulty in achieving precise synchronization when multiple devices work together. By using a PCIE driver for communication, not only can high-speed data transmission be achieved, but also parallel testing of multiple hardware boards can be supported, greatly improving the overall performance of the system. In addition, by sending a clear completion flag bit, the host computer can ensure that the test results are read at the optimal time, avoiding data loss or incorrect reading due to external interference or other factors. Moreover, this method also has a high degree of flexibility and scalability. Since the test result data is generated in the lower computer and saved to a specified memory address, the storage strategy can be dynamically adjusted according to actual needs. For example, if new test items need to be added or existing items need to be modified, only the corresponding memory address needs to be updated, without making major adjustments to the entire system architecture. This not only improves the development efficiency but also provides greater flexibility and convenience for users.

[0082] Specifically, in step S6, after the host computer detects the completion flag bit, it reads the test result data from the pre-specified memory address and displays the test result data in real time on the host computer interface. In a specific embodiment, when the lower computer completes all test items and saves the test result data to the pre-specified memory address, it generates a completion flag bit and sends it to the host computer through the PCIE card. After receiving this flag bit, the host computer immediately starts the reading program and extracts the corresponding test result data from the memory of the lower computer. For example, during the diode test, assuming that tests such as forward voltage and reverse breakdown voltage have been completed, the lower computer will save the results of each test item (such as the specific voltage values and current values measured) to specific memory addresses. These addresses are usually associated with the numbers or names of the test items for subsequent data reading and analysis.

[0083] Once the host computer detects the completion flag bit, it reads the test result data stored in these addresses one by one according to the pre-set list of memory addresses. To ensure the reliability and integrity of data transmission, the host computer will verify the read data and compare it with the checksum calculated by the lower computer. If the verification passes, the host computer will parse and convert these data into a format suitable for display. Subsequently, these results are displayed on the user interface of the host computer for engineers to further analyze and process.

[0084] Such as Figure 8As shown, in this mode, multiple sets of physical hardware can be supported for parallel testing without mutual interference. The host computer only needs to create multiple threads, send the instruction set to the memory of the corresponding physical hardware, and wait for the start test instruction to be sent, which greatly improves the test efficiency, stability, and anti-interference ability, and at the same time significantly reduces the customer's purchase cost.

[0085] In a specific embodiment, taking the diode device test as an example, it first verifies the normal communication of various boards between the host computer and the lower computer, initializes the PCIE driver first, and opens the PCIE hardware device with open_intr_dev. Then, it opens the test process of the device under test, including the forward voltage, reverse breakdown voltage, reverse current, etc. of the diode. The host computer creates a test thread TestThread, parses all the parameters of each test item, and assembles the parameter information such as voltage, current, gear, test time, waiting time, discharge time, measurement mode, etc. into an instruction set. The instruction set of each test item contains 8 bytes, and the instructions of the entire test process are written into the memory starting from the address 0x0000. Each site is allocated 2000 address spaces; the total execution time of the instructions and the board mask to be executed are combined into 2 words and written into the memory of the PCIE card. Finally, after starting the test, it sends a start test request. The lower computer parses the instruction set and operates the corresponding hardware board through the 2 words in the PCIE card memory. The lower computer will automatically execute the next instruction set after the total execution time of each instruction set. After the lower computer completes within the specified time, it sends an execution completion flag bit and saves the measurement result to the specified address. The host computer reads the completion flag bit of each instruction set, reads the data results of the specified type (maximum value, average value, minimum value, voltage / current value) from the agreed address, displays them in real time on the host computer, and saves them to the corresponding database.

[0086] The basic principle of the present application has been described above in combination with specific embodiments. However, it should be noted that the advantages, advantages, effects, etc. mentioned in the present application are only examples and not limitations. It cannot be considered that these advantages, advantages, effects, etc. are essential for each embodiment of the present application. In addition, the above-disclosed specific details are only for the purpose of illustration and easy understanding, and not for limitation. The above details do not limit the present application to necessarily adopt the above specific details to implement.

[0087] The block diagrams of the devices, apparatuses, equipment, and systems involved in this application are only illustrative examples and are not intended to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, equipment, and systems can be connected, arranged, and configured in any manner. Words such as "including", "comprising", "having", etc. are open-ended terms that mean "including but not limited to" and can be used interchangeably with each other. The word "or" and "and" used herein refer to the phrase "and / or" and can be used interchangeably with it, unless the context clearly indicates otherwise. The phrase "such as" used herein refers to the phrase "such as but not limited to" and can be used interchangeably with it.

[0088] It should also be noted that in the devices, equipment, and methods of this application, each component or each step can be decomposed and / or recombined. These decompositions and / or recombinations should be regarded as equivalent solutions of this application.

[0089] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this application. Various modifications to these aspects will be very apparent to those skilled in the art, and the general principles defined herein can be applied to other aspects without departing from the scope of this application. Therefore, this application is not intended to be limited to the aspects shown herein, but rather to the broadest scope consistent with the principles and novel features disclosed herein.

[0090] The above description has been given for purposes of illustration and description. In addition, this description is not intended to limit the embodiments of this application to the forms disclosed herein. Although multiple example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions, and sub-combinations thereof.

Claims

1. An instruction set control method for discrete semiconductor testing, characterized in that: include: The host computer encapsulates the test steps and parameters into an instruction set based on the test requirements of the device under test; The upper computer writes the instruction set into the memory of the lower computer; The upper computer sends a start test command to the lower computer; After receiving the start test instruction, the lower computer parses the instruction set from its memory, and operates the hardware board to execute each test item based on the instruction of the instruction set to obtain test result data; After the execution of the instruction set is completed, the lower computer saves the test result data to a pre-specified memory address and sends a completion flag to the upper computer; After the host computer detects the completion flag, it reads the test result data from the pre-specified memory address and displays the test result data in real time on the host computer interface.

2. The instruction set control method for discrete semiconductor testing according to claim 1, characterized in that: The upper computer writes the instruction set into the memory of the lower computer, including: the upper computer writes the instruction set into the memory of the lower computer through the PCIE card.

3. The instruction set control method for discrete semiconductor testing according to claim 2, characterized in that: The upper computer writes the instruction set into the memory of the lower computer, including: Initialize the PCIE card driver; The host computer writes the instruction set into the memory area of ​​the PCIE card through the driver of the PCIE card; The PCIE card writes the instruction set into the memory of the lower computer based on the routing information of the instruction set.

4. The instruction set control method for discrete semiconductor testing according to claim 3, characterized in that: The PCIE card writes the instruction set into the memory of the lower computer based on the routing information of the instruction set, including: The PCIE card sends each instruction in the instruction set to the corresponding hardware board based on the routing information of the instruction set; The hardware board sends each instruction in the instruction set to the memory of the lower computer.

5. The instruction set control method for discrete semiconductor testing according to claim 2, characterized in that: The upper computer writes the instruction set into the memory of the lower computer, and also includes: The host computer divides the instruction set into a plurality of data packets and calculates a check code for each data packet to obtain a plurality of data packets with check codes; The upper computer sends the multiple data packets with verification codes to the lower computer one by one; After receiving each data packet with a check code, the lower computer performs content verification on each data packet based on the check code; After completing the data packet verification, a response signal is sent to the host computer to inform the reception status of the data packet.

6. The instruction set control method for discrete semiconductor testing according to claim 5, characterized in that: The host computer divides the instruction set into multiple data packets and calculates a check code for each data packet to obtain multiple data packets with check codes, including: Extract the MTU value of the PCIE card; Extract the buffer size and memory bandwidth value of the lower computer; evaluating the complexity of the instruction set and calculating the size of the instruction set; Based on the MTU value, the buffer size, the memory bandwidth value, the complexity of the instruction set, and the size of the instruction set, a maximum payload size of a fixed data packet is recommended.

7. The instruction set control method for discrete semiconductor testing according to claim 6, characterized in that: Based on the MTU value, the buffer size, the memory bandwidth value, the complexity of the instruction set, and the size of the instruction set, recommending a maximum payload size of a fixed data packet includes: recommending a maximum payload size of a fixed data packet using the following formula, wherein the formula is: in, is the MTU value, is the buffer size, is the memory bandwidth value, is the maximum delay allowed by the system, is the size of the instruction set, is the protocol header overhead, Reserve a ratio for the buffer zone, represents the complexity factor of the instruction set, represents the minimum function, Indicates the maximum payload size of a fixed data packet.

8. The instruction set control method for discrete semiconductor testing according to claim 7, characterized in that: The upper computer writes the instruction set into the memory of the lower computer, and also includes: reducing the copy overhead from the buffer to the memory during data transmission through the buffer-memory zero copy mechanism of the header.

9. The instruction set control method for discrete semiconductor testing according to claim 8, characterized in that: The header buffer-memory zero-copy mechanism is used to reduce the buffer-to-memory copy overhead during data transmission, including: The buffer is defined as a circular linked list, where each table size of the circular linked list is , and the number of cycles is , then obviously there is ; Set the size of each table Memory bandwidth value and the maximum delay allowed by the system At the same time, correspondingly, a buffer-memory pre-allocation mapping is performed, and the buffer-memory pre-allocation mapping is expressed as: in, is the ratio of the protocol header overhead to the MTU value, is the ratio of each table size to the memory bandwidth value, ,coefficient Make Approaching one.

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