ZYNQ-based high-speed file system

Abstract

A high-speed file system based on ZYNQ comprises a storage board and a DSP data processing board, the storage board comprises a ZYNQ chip of an ARM + FPGA architecture and an SRIO switch, the DSP data processing board comprises a plurality of 8-core DSP chips, the DSP chips communicate with the ZYNQ chip through the SRIO switch, and the ZYNQ chip communicates with the DSP data processing board through the SRIO switch. A DDR space of an ARM side of a ZYNQ chip is divided into a message receiving address, a data receiving address, a message sending address and a data sending address, each type of address is divided into a plurality of areas, and each area is provided for a DSP chip to use. Based on protocols of two data types of messages and data, multiple cores of multiple DSPs in the system can operate files, folders and disks at the same time, the DSP scale supported by the storage system can be greatly improved on the premise that the number of storage board cards is not increased, a basically complete file system at the DSP end is achieved, and the storage efficiency is improved. And the stored data can be exported through the network port of the DSP end, so that the network port specially used for exporting the data is saved.

Description

Technical Field

[0001] The present invention relates to the technical field of data processing, and in particular, to a high-speed file system based on ZYNQ. Background Art

[0002] In a DSP-based signal processing system, there are two traditional data storage methods. One is to send data to an FPGA, and the FPGA starts storage, and the FPGA writes the data to an EMMC or SSD. The data is exported through a gigabit network or a 10-gigabit network. Due to the limitation of the logic resource scale at the FPGA end, it is difficult to implement a complete file system function in the traditional method, and the FPGA is not good at processing program flows, so it is difficult to implement functions such as processing standard disk formats, repartitioning, and file pointer offsets. This method has at least three defects: 1. The supported functions are relatively single, and the DSP end can only perform simple file reading and writing, and cannot perform refined management of files, such as obtaining disk or file information, formatting disks or repartitioning, etc.; 2. The number of supported DSPs is limited, and it is difficult to expand the number of supported DSPs; 3. A separate data export interface is required, increasing costs and power consumption.

[0003] The other is to use a ZYNQ chip platform. After the FPGA receives the data sent by the DSP, it writes the data to the DDR of the ARM through an internal bus, and notifies the ARM of data readiness through an interrupt, and then the ARM writes the data to disk. This method has only a one-way data stream without control instructions and reverse data transmission functions, does not support functions such as file reading, pointer offset, and file size acquisition, and the number of supported DSPs in this direct operation method is small, and a separate data export interface is required.

[0004] Therefore, it is necessary to design a high-speed file system based on ZYNQ to overcome the above problems. Summary of the Invention

[0005] In order to avoid the above problems, a high-speed file system based on ZYNQ is provided. Based on a protocol of two data types, namely messages and data, it can enable multiple cores of multiple DSPs in the system to simultaneously operate on files, folders, and disks, can greatly increase the scale of DSPs supported by the storage system without increasing the number of storage boards, meet the needs of multiple cores of multiple DSPs for high-speed file reading and writing, and at the same time, a basically complete file system is implemented at the DSP end, and the stored data can be exported through the network port at the DSP end, saving the network port dedicated to data export.

[0006] A high-speed file system based on ZYNQ provided by the present invention includes: a storage board and a DSP data processing board. The storage board includes a ZYNQ chip with an ARM+FPGA architecture and an SRIO switch. The DSP data processing board includes multiple 8-core DSP chips. The DSP chips communicate with the ZYNQ chip through the SRIO switch. By dividing the DDR space on the ARM side of the ZYNQ chip into a receive message address, a receive data address, a send message address, and a send data address, each type of address is divided into multiple regions, and each region is provided for one DSP chip to use.

[0007] Preferably, it includes DSP software, FPGA path interface software, and ARM software; the DSP software includes a file system interface module, a bottom-layer data management module, and a protocol implementation module. The file system interface module is used to provide operation interfaces for files, directories, and disks called by application programs. The bottom-layer data management module is used to uniformly organize the data and messages of 8 cores, encapsulate and transform them through the protocol implementation module into SRIO data, and send them to the ZYNQ chip through the SRIO switch; the FPGA path interface software is used to split the received SRIO switch data packets into two types of data, data and messages, and send them to the corresponding DDR functions of the ARM respectively, including the SRIO protocol IP core, DMA, and control programs; the ARM software is used to parse the messages sent by the DSP, write the received data to disk, and prepare the data for the DSP to read.

[0008] Preferably, the DSP software further includes an ftp service module. The file system interface module is used to provide a file system interface API for upper-layer applications. The upper-layer applications, ftp service, and user programs access the storage function through the file system interface module. The ftp service module is an ftp-lite service running on the basis of this protocol, and is connected and accessed through the upper computer, and is used to export and play back the data in the file system through the DSP.

[0009] Preferably, the FPGA path interface software runs on the PL side of the ZYNQ chip, and is used to store the messages and data sent by the DSP into the DDR on the PS side of the ZYNQ chip in the form of circular queues through the internal bus respectively. Each time a message is stored, an interrupt will be sent to the PS side.

[0010] Preferably, in the bottom-layer data management module, each core of the DSP sends the data packet to the circular queue of core 0 through notify, and then the protocol implementation module of core 0 performs protocol encapsulation and sends it to the ZYNQ chip through the SRIO switch.

[0011] Preferably, the message data from the PS side of the ZYNQ chip to the DSP is data uplink, and the message data from the DSP to the PS side of the ZYNQ chip is data downlink; the DDR storage part on the PS side is divided into an uplink message data space and a downlink message data space. Both the uplink data message space and the downlink data message space are divided into 8 data spaces and 8 message spaces for use in message data uplink and downlink; the uplink message data space is all linear array spaces, and the downlink message data space is all circular queue spaces.

[0012] Preferably, the message protocol format is 32 bytes in length and is divided into 5 fields, namely the hc field, the rdia field, the ext1 field, the ext2 field, the parameters field, and the checksum field; the extension 1 and extension 2 fields are used to send the real length, alignment length of the data, or the length information merged into 64 bits. The parameters field is 12 bytes in total and is used to carry string information in the message and jointly use the rdia field to send long strings.

[0013] Preferably, the hc field consists of a 16-bit message header and a 16-bit command. The message header is used for protocol identification, and the command is used to indicate the specific function of this message; the rdia field contains the rioID sub-field, the Doorbell info sub-field, the index sub-field, and the all sub-field. Each sub-field occupies 8 bits. The rioID sub-field is the Rapid IO address of the sender of this message. The Doorbell info sub-field is used to indicate the specific core number of the sender of this message. The index sub-field and the all sub-field are used in combination. When the storage space of the parameters field of a message is not enough, the sent message will be split into multiple message frames. Among them, the index sub-field is used to indicate which frame of this message it is currently, and the all sub-field is used to indicate how many frames this message has in total. When the ZYNQ chip receives it, a complete message will be merged through these two sub-fields; the ext1 field and the ext2 field are used to store integer data types; the parameters field is used to store string data types; the checksum field is used to calculate the correctness of the message protocol during transmission.

[0014] Compared with the prior art, the present invention has the following beneficial effects: The present invention formulates two data paths for data and messages, and on this basis, invents a set of operation protocols to achieve precise control of data. For example, common file operation functions such as opening, closing, writing, reading, deleting, pointer offset, obtaining the current pointer position, obtaining file attributes, opening folders, creating folders, obtaining files under the folder, disk formatting, and repartitioning can be achieved through this protocol; in addition, the protocol reserves rich expansion interfaces to achieve function expansion in different applications. Description of the Drawings

[0015] Figure 1 Schematic diagram of the hardware structure connection of the ZYNQ-based high-speed file system according to a preferred embodiment of the present invention;

[0016] Figure 2 DSP software block diagram according to a preferred embodiment of the present invention;

[0017] Figure 3 DSP data packet circular queue diagram according to a preferred embodiment of the present invention;

[0018] Figure 4 Message format diagram according to a preferred embodiment of the present invention. Detailed Description of the Invention

[0019] In order to make the objectives, technical solutions, and advantages of the present invention clearer, the technical solutions of the present invention will be introduced below in conjunction with the embodiments and the drawings.

[0020] As Figures 1 to 3 shown, a ZYNQ-based high-speed file system provided in this embodiment takes the following hardware example as a prerequisite and can work in similar hardware. Here is just an example. As Figure 1 shown, the hardware circuit is divided into a total of five boards, namely a storage board, a base board, and three DSP data processing boards. Among them, the storage board is equipped with a ZYNQ with an ARM+FPGA architecture and an SRIO switch. Each DSP data processing board includes two 8-core DSP chips, and each DSP is connected to the SRIO switch on the storage board through the SRIO bus.

[0021] The software part is divided into three parts: DSP software, FPGA path interface software, and ARM software. Among them, the DSP software includes a file system interface module, a low-level data management module, and a protocol implementation module. The file system interface software provides operation interfaces for files, directories, and disks for application programs to call. The low-level data management software organizes the data and messages of 8 cores uniformly and sends them to the ZYNQ through the SRIO. By dividing the DDR space on the ARM side of the ZYNQ chip into a receive message address, a receive data address, a send message address, and a send data address, the FPGA path interface software realizes the function of splitting the received SRIO data packets into two types of data, namely data and messages, and sending them to the corresponding DDR address spaces of the ARM, including the SRIO protocol IP core, DMA, and control programs. The ARM software realizes parsing the messages sent by the DSP, writing the received data to disk, and preparing the data for the DSP to read.

[0022] This embodiment is implemented through the above three parts of software. The software framework designed for the ZYNQ-based high-speed file system is a client-server framework (CS framework).

[0023] Among them, the DSP software serves as the front-end software stack of the file system. As Figure 2 shown, the DSP software consists of four parts: the file system interface module, the ftp service module, the underlying data management module, and the protocol implementation module. The file system interface module provides the file system interface (API) for upper-layer applications. Upper-layer applications, the ftp service, and user programs access the storage function through this module. The ftp service module is an ftp-lite service running on the basis of this protocol, which can be connected and accessed through the host computer and is used to export and play back the data in the file system through the DSP. This module is an optional item and does not affect the normal operation of the file system. The protocol implementation module, the underlying data management module, and the ftp service module are threads running in the background of the specified core in the multi-core system. After other cores in the multi-core system call the file system interface module (API), the executed functions and data will be sent to this module, which will process and send them to the protocol implementation module. The protocol implementation module encapsulates the data sent by all underlying data management modules into protocols and converts them into SRIO data, which is sent to the ZYNQ chip through the SRIO switch.

[0024] The FPGA path interface software runs on the PL side (programmable logic side) of the ZYNQ chip. The function of this software is to store the messages and data sent by the DSP into the DDR of the PS side (processing system) of the ZYNQ chip in a circular queue manner through the internal bus respectively. Each time a message is stored, an interrupt will be sent to the PS side.

[0025] The ARM software serves as the back-end of the file system and is responsible for protocol parsing of the messages and data in the DDR, and after performing corresponding operations such as disk writing, formatting, and read-back, it sends the operation results to the corresponding DSP core through the protocol.

[0026] In this embodiment, the high-speed file system consists of six 8-core DSPs, an SRIO switch, and a ZYNQ, and the communication between the DSP and the ZYNQ is realized through the SRIO switch. The SRIO receiving addresses on the PL side of the ZYNQ are divided into two addresses, the message address and the data address. Each type of address is divided into multiple regions, and each region is provided for one DSP to use. The PL writes the received messages and data to the DDR on the PS side through the HP interface, and the PS performs disk writing on the received data. As Figure 1 .

[0027] As Figure 3 shown, the core function working principle of the underlying data management module is that each core of the DSP sends data packets to the circular queue of core 0 through notify, and then the protocol implementation module of core 0 performs protocol encapsulation and sends it to the ZYNQ chip through SRIO.

[0028] Define that the message data from the PS to the DSP is data uplink, and the message data from the DSP to the PS is data downlink. The DDR storage part at the PS end is divided into an uplink message data space and a downlink message data space. Both the uplink data message space and the downlink data message space are divided into 8 data spaces and 8 message spaces for the use of message data uplink and downlink. The uplink message data space is all linear array spaces, and the downlink message data space is all circular queue spaces.

[0029] As Figure 4 shown, the length of each message protocol format is 32 bytes and is divided into 5 fields. They are the hc (message header and command) field, the rdia (sender RIO address, sender core's doorbell message, current packet sequence number, and total number of packets) field, the ext1 (extension 1) field, the ext2 (extension 2) field, the parameters field, and the checksum field. The extension 1 and extension 2 fields are used for the real length, alignment length of the transmitted data, or length information merged into 64 bits. The parameters field is 12 bytes in total and is used to carry string information in the message. A long string can be sent jointly through the rdia field.

[0030] The functions of each message protocol field are as follows:

[0031] 1. hc (message header and command) field

[0032] This field consists of a 16-bit message header and a 16-bit command. The message header is used for protocol identification, and the command is used to indicate the specific function of this message. The example is as follows:

[0033]

[0034] 2. rdia (sender RIO address, sender core's doorbell message, current packet sequence number, and total number of packets) field

[0035] The rdia field contains 4 sub-fields as Figure 4As shown, each subfield occupies 8 bits. The rioID subfield is the Rapid IO address of the sender of this message. When this message requires a response from the ZYNQ storage board, the corresponding response content will be sent to the DSP at this Rapid IO address. The Doorbell info subfield is used to indicate the specific core number of the sender of this message. In a DSP multi-core system, multiple cores of each DSP share a single Rapid IO address. Therefore, this field is needed to cooperate to confirm the specific core that sends the message. The index subfield and the all subfield are used in combination. When the storage space of the parameters field of a message is not enough, the sent message will be split into multiple message frames. Among them, the index subfield is used to indicate which frame of this message it is currently, and the all subfield is used to indicate how many frames this message has in total. When the ZYNQ storage board receives it, it will merge these two subfields into a complete message.

[0036] 3. ext1 (Extension 1) field, ext2 (Extension 2) field

[0037] The extension fields are used to store integer data types. They can be used alone. For example, when writing data with an unaligned length, ext1 can be used to store the actual length of the data, and ext2 can be used to store the alignment length of the data (SRIO data transmission requires byte alignment). They can also be used in combination. For example, when obtaining the size of a large file (a file larger than 4GB), ext1 and ext2 need to be combined into a long long data type to store a length exceeding 4GB.

[0038] 4. parameters (Parameters) field

[0039] This field is used to store string data types. In cooperation with the rdia field, it can send strings of any length. It is often used to transmit paths and file names.

[0040] 5. checksum (Checksum) field

[0041] This field is used to calculate the correctness of the message protocol during transmission. If the checksum fails, it is considered that this message is illegal and will be discarded.

[0042] The core of the high-speed file system solution based on ZYNQ in the present invention is Figure 4 the message protocol shown. This message protocol can enable multiple cores of multiple DSPs to read and write files in the file system simultaneously by summarizing all common file, folder, and disk operations into 5 message fields, and provides rich operation expansion capabilities.

[0043] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A high-speed file system based on ZYNQ, characterized in that: include: Storage board and DSP data processing board. The storage board includes a ZYNQ chip with ARM+FPGA architecture and an SRIO switch. The DSP data processing board includes multiple 8-core DSP chips. The DSP chip communicates with the ZYNQ chip through the SRIO switch. The DDR space on the ARM side of the ZYNQ chip is divided into receive message address, receive data address, send message address and send data address. Each type of address is divided into multiple areas, and each area is provided to a DSP chip for use.

2. The high-speed file system based on ZYNQ as claimed in claim 1, characterized in that: It includes DSP software, FPGA channel interface software and ARM software; the DSP software includes file system interface module, underlying data management module and protocol implementation module. The file system interface module is used to provide operation interfaces for files, directories and disks called by applications. The underlying data management module is used to organize the data and messages of 8 cores in a unified manner, encapsulate them through the protocol implementation module, convert them into SRIO data and send them to the ZYNQ chip through the SRIO switch; the FPGA channel interface software is used to split the received SRIO switch data packets into data and messages, and send them to the corresponding DDR functions of ARM respectively, including SRIO protocol IP core, DMA and control program; the ARM software is used to parse the messages sent by DSP, put the received data into disk and prepare the data to be read by DSP.

3. The high-speed file system based on ZYNQ as claimed in claim 2, characterized in that: The DSP software also includes an ftp service module. The file system interface module is used to provide a file system interface API used by upper-level applications. Upper-level applications, ftp services and user programs access storage functions through the file system interface module. The ftp service module is an ftp-lite service that runs on the basis of this protocol. It is connected and accessed through the host computer and is used to export and playback data in the file system through the DSP.

4. The high-speed file system based on ZYNQ as claimed in claim 2, characterized in that: The FPGA channel interface software runs on the PL side of the ZYNQ chip, and is used to store the messages and data sent by the DSP in the DDR of the PS side of the ZYNQ chip in a circular queue through the internal bus. Each time a message is stored, an interrupt will be sent to the PS side.

5. The ZYNQ-based high-speed file system as claimed in claim 2, characterized in that: In the underlying data management module, each DSP core sends the data packet to the circular queue of core 0 through notify, and then the protocol implementation module of core 0 encapsulates the protocol and sends it to the ZYNQ chip through the SRIO switch.

6. The high-speed file system based on ZYNQ as claimed in claim 1, characterized in that: The message data from the PS end of the ZYNQ chip to the DSP is data uplink, and the message data from the DSP to the PS end of the ZYNQ chip is data downlink; the DDR storage part of the PS end is divided into uplink message data space and downlink message data space, and the uplink data message space and the downlink data message space are both divided into 8 data spaces and 8 message spaces, providing uplink and downlink use of message data; the uplink message data space is a linear array space, and the downlink message data space is a circular queue space.

7. The high-speed file system based on ZYNQ as claimed in claim 1, characterized in that: The message protocol format is 32 bytes long and is divided into five fields, namely, the hc field, the rdia field, the ext1 field, the ext2 field, the parameters field, and the checksum field. The extension 1 and extension 2 fields are used to send the actual length of the data, the alignment length, or the length information combined into 64 bits. The parameter field is 12 bytes in total and is used to carry string information in the message. The rdia field is used together to send long strings.

8. The high-speed file system based on ZYNQ as claimed in claim 7, characterized in that: The hc field consists of a 16-bit message header and a 16-bit command. The message header is used to identify the protocol, and the command is used to indicate the specific function of the message. The rdia field contains the rioID subfield, the Doorbell info subfield, the index subfield, and the all subfield. Each subfield occupies 8 bits. The rioID subfield is the Rapid IO address of the sender of the message. The Doorbell info subfield is used to indicate the specific core number of the sender of the message. The index subfield and the all subfield are used together. When the parameters field of a message does not have enough storage space, the sent message will be split into multiple message frames. The index subfield is used to indicate the current frame of the message, and the all subfield is used to indicate the total number of frames of the message. When the ZYNQ chip receives it, these two subfields will be merged into a complete message. The ext1 field and the ext2 field are used to store integer data types. The parameters field is used to store string data types. The checksum field is used to calculate the correctness of the message protocol during transmission.

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