Schottky diode and mask

Abstract

The invention provides a Schottky diode and a mask plate. The Schottky diode comprises a semiconductor layer, a groove unit, a barrier layer and a metal layer. The semiconductor layer comprises a first side and a second side which are opposite to each other, the groove units are formed on the first side of the semiconductor layer, the groove units are arranged on the first side in an array mode, each groove unit comprises a plurality of first-shaped grooves and a plurality of second-shaped grooves, the area where the groove units are located comprises a plurality of adjacent sub-areas, and each sub-area comprises a plurality of first-shaped grooves and a plurality of second-shaped grooves. Each sub-region is internally provided with first shape grooves and second shape grooves located between the first shape grooves. The barrier layer is located on the first side of the semiconductor layer, the metal layer comprises a first metal layer and a second metal layer, the first metal layer is located on the side, away from the semiconductor layer, of the barrier layer, and the second metal layer is located on the second side of the semiconductor layer. Therefore, through the above structure, the voltage resistance and the surge capacity of the Schottky diode can be effectively improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing, and more particularly, to a Schottky diode and a mask plate. Background Art

[0002] The trench MOS barrier Schottky (TMBS) is a high-performance semiconductor device that optimizes the characteristics of traditional Schottky diodes by introducing a trench structure. Compared with traditional Schottky diodes, TMBS has better reverse blocking characteristics and lower reverse leakage current, making it widely used in the field of photovoltaic cells. However, the breakdown voltage and surge capability of current trench Schottky diodes are not satisfactory. Summary of the Invention

[0003] To overcome the technical problems mentioned in the above technical background, an embodiment of the present application provides a Schottky diode, which includes:

[0004] A semiconductor layer including opposite first and second sides;

[0005] A trench unit formed on the first side of the semiconductor layer, and a plurality of the trench units are arranged in an array on the first side. The trench unit includes a plurality of first-shaped trenches and a plurality of second-shaped trenches. Wherein, the area where the trench unit is located includes a plurality of adjacent sub-regions, and each sub-region is provided with a first-shaped trench and a second-shaped trench located between the first-shaped trenches;

[0006] A barrier layer located on the first side of the semiconductor layer;

[0007] A metal layer including a first metal layer and a second metal layer. The first metal layer is located on the side of the barrier layer away from the semiconductor layer, and the second metal layer is located on the second side of the semiconductor layer.

[0008] In a possible implementation, the first-shaped trench is a strip-shaped trench, and the second-shaped trench is a dot-shaped trench;

[0009] In any one of the sub-regions, two of the first-shaped trenches are disposed opposite to each other, and at least one of the second-shaped trenches is located between the two first-shaped trenches.

[0010] In a possible implementation, the area where the trench unit is located includes a first sub-region, a second sub-region, a third sub-region, and a fourth sub-region, and the shapes of the first sub-region, the second sub-region, the third sub-region, and the fourth sub-region are rectangular;

[0011] The first sub-region is adjacent to the second sub-region and the third sub-region, the second sub-region is adjacent to the first sub-region and the fourth sub-region, the first sub-region and the fourth sub-region are opposite to each other, and the second sub-region and the third sub-region are opposite to each other;

[0012] The first sub-region and the second sub-region are distributed along a first direction, the third sub-region and the fourth sub-region are distributed along the first direction, the first sub-region and the third sub-region are distributed along a second direction, and the second sub-region and the fourth sub-region are distributed along the second direction, where the first direction and the second direction are perpendicular to each other;

[0013] In any one of the sub-regions, two first-shaped grooves are distributed along the first direction or the second direction, and at least one second-shaped groove is located between the two first-shaped grooves.

[0014] In a possible implementation manner, the groove distributions in the first sub-region and the fourth sub-region are the same, the groove distributions in the second sub-region and the third sub-region are the same, and the groove distributions in the first sub-region and the second sub-region are different.

[0015] In a possible implementation manner, the first sub-region and the fourth sub-region include first-shaped grooves oppositely arranged along a first direction and second-shaped grooves located between the first-shaped grooves, and the second sub-region and the third sub-region include first-shaped grooves oppositely arranged along a second direction and second-shaped grooves located between the first-shaped grooves.

[0016] In a possible implementation manner, the number of the second-shaped grooves is multiple, the second-shaped grooves in the first sub-region and the fourth sub-region are arranged between the oppositely arranged first-shaped grooves along the second direction, and the second-shaped grooves in the second sub-region and the third sub-region are arranged between the oppositely arranged first-shaped grooves along the first direction.

[0017] In a possible implementation manner, the first-shaped groove and the second-shaped groove include a groove body, an oxide layer, and a conductor, where the oxide layer is disposed in contact with the inner wall of the groove body, and the conductor is disposed on the oxide layer;

[0018] The positive projections of the oxide layer and the conductor on the semiconductor layer are located within the positive projection of the groove body on the semiconductor layer, and the positive projection of the conductor on the semiconductor layer is located within the positive projection of the oxide layer on the semiconductor layer.

[0019] In a possible implementation, the semiconductor layer includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer and the second semiconductor layer are stacked, and the trench unit is formed on a side of the first semiconductor layer away from the second semiconductor layer;

[0020] The first semiconductor layer is an N-type semiconductor layer, and the second semiconductor layer is an N+-type semiconductor layer.

[0021] In a possible implementation, a positive projection of the trench unit on the semiconductor layer is located within a positive projection of the barrier layer on the semiconductor layer, and a positive projection of the metal layer on the semiconductor layer coincides with the positive projection of the barrier layer on the semiconductor layer.

[0022] Another object of the present application is to provide a mask plate for forming trench units in a plurality of Schottky diodes provided by the present application.

[0023] Based on any of the above aspects, a Schottky diode and a mask plate provided by an embodiment of the present application. The trench with the first shape helps to disperse the electric field, reduce the electric field concentration, and thus improve the breakdown voltage performance of the Schottky diode. The trench with the second shape increases the area of the Schottky barrier, reduces the forward voltage drop, and improves the surge current withstand capacity. Thus, the above structure divides the trench unit into multiple sub-regions, and opposite trenches with the first shape and the second shape are provided in each sub-region, so that each sub-region can make full use of the advantages of the trenches with the first shape and the second shape, and can effectively improve the breakdown voltage and surge capacity of the Schottky diode. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required to be referred to in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0025] Figure 1 A top view of a Schottky diode with a strip-shaped trench provided in this embodiment;

[0026] Figure 2 A top view of a Schottky diode with a dot-shaped trench provided in this embodiment;

[0027] Figure 3 A top view of a Schottky diode combining a strip-shaped trench and a dot-shaped trench provided in this embodiment;

[0028] Figure 4The second top view of the Schottky diode combining strip grooves and dot grooves provided in this embodiment;

[0029] Figure 5 The schematic diagram of a Schottky diode provided in this embodiment;

[0030] Figure 6 The top view of a Schottky diode provided in this embodiment;

[0031] Figure 7 For Figure 6 The partial enlarged view of the dashed box in

[0032] Figure 8 The schematic diagram of a trench unit provided in this embodiment;

[0033] Figure 9 The process step diagram of a preparation method of a Schottky diode provided in this embodiment;

[0034] Figures 10a - 10c For Figure 9 The corresponding process flow chart.

[0035] Icon: 10 - strip groove, 11 - dot groove, 2 - Schottky diode, 20 - semiconductor layer, 200 - first semiconductor layer, 201 - second semiconductor layer, 21 - trench unit, 210 - first-shaped trench, 211 - second-shaped trench, 212 - sub-region, 2120 - first sub-region, 2121 - second sub-region, 2122 - third sub-region, 2123 - fourth sub-region, 213 - trench body, 214 - oxide layer, 215 - conductor, 22 - barrier layer, 23 - metal layer, 230 - first metal layer, 231 - second metal layer, 24 - insulating layer, 240 - insulating layer window. Detailed implementation manners

[0036] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Apparently, the described embodiments are some, but not all, of the embodiments of the present application. Usually, the components of the embodiments of the present application described and illustrated herein can be arranged and designed in various different configurations.

[0037] Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the present application claimed, but merely represents the selected embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts fall within the scope of protection of the present application.

[0038] It should be noted that similar reference numerals and letters denote similar items in the following figures. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0039] In the description of the present application, it should be noted that the orientation or positional relationship indicated by terms such as "upper", "lower", etc. is based on the orientation or positional relationship shown in the figures, or the orientation or positional relationship in which the product of this application is customarily placed during use. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be construed as a limitation of the present application. In addition, terms such as "first", "second", etc. are only used for distinguishing descriptions and cannot be construed as indicating or implying relative importance.

[0040] It should be noted that, without conflict, different features in the embodiments of the present application can be combined with each other.

[0041] The inventors have found that the trench structures of current trench-type Schottky diodes are mainly in the form of strip trenches, dot trenches, or a simple combination of strip trenches and dot trenches. Specifically, for example Figure 1 and Figure 2 as shown, Figure 1 is a top view of a Schottky diode with a strip trench 10 provided in this embodiment, Figure 2 is a top view of a Schottky diode with a dot trench 11 provided in this embodiment. Since the strip trench 10 has continuous trenches, it has the advantage of high breakdown voltage, but has a high forward voltage drop and poor surge capability. The dot trench 11 has the advantages of low forward voltage drop and strong surge capability due to its large Schottky barrier area, but has poor breakdown voltage. Therefore, a Schottky diode having only a strip trench 10 or a dot trench 11 cannot achieve both an ideal breakdown voltage and surge capability at the same time.

[0042] In addition, for example Figure 3 and Figure 4 as shown, Figure 3 and Figure 4 are top views of two Schottky diodes with a combination of a strip trench 10 and a dot trench 11 provided in this embodiment. However, these two combination methods only simply piece together the strip trench 10 and the dot trench 11, and their unit cell structures are either strip trenches 10 or dot trenches 11. Therefore, their breakdown voltages and surge capabilities are still not ideal. Therefore, in order to solve the technical problems in the background art and those mentioned above, the inventors have innovatively designed the following technical solutions, and the specific implementation solutions of the present application will be described in detail below with reference to the figures.

[0043] Please refer to Figure 5 、 Figure 6 and Figure 7 , Figure 5A schematic diagram of a Schottky diode 2 provided in this embodiment, Figure 6 A top view of a Schottky diode 2 provided in this embodiment, Figure 7 for Figure 6 The Schottky diode 2 includes a semiconductor layer 20 , a trench unit 21 , a barrier layer 22 and a metal layer 23 .

[0044] The semiconductor layer 20 includes a first side and a second side relative to each other, a groove unit 21 is formed on the first side of the semiconductor layer 20, and a plurality of groove units 21 are arranged in an array on the first side, the groove unit 21 includes a plurality of first shape grooves 210 and a plurality of second shape grooves 211, wherein the area where the groove unit 21 is located includes a plurality of adjacent sub-areas 212, each sub-area 212 is provided with a first shape groove 210 and a second shape groove 211 located between the first shape grooves 210.

[0045] In this embodiment, the semiconductor layer 20 forms the basis of the Schottky diode 2, and is generally made of N-type semiconductor material. The trench units 21 are formed on the first side of the semiconductor layer 20 and arranged in an array on the first side, wherein the region where the trench units 21 are located can be divided into a plurality of adjacent sub-regions 212, and each adjacent sub-region 212 is provided with a first-shaped trench 210 and a second-shaped trench 211.

[0046] Specifically, the first shape groove 210 can be a strip groove. Since the strip groove is continuous, it can effectively disperse the electric field and reduce the concentration of the electric field, and has the advantage of high withstand voltage. However, since the carriers are highly concentrated in the strip groove, it leads to a higher forward voltage drop and poor surge capacity. The second shape groove 211 can be a point-shaped groove. Since the Schottky barrier area is large, the point-shaped groove increases the flow path of the current and reduces the resistance, so it has a lower forward voltage drop and a higher surge capacity. However, due to the concentration of the electric field, the withstand voltage performance of the point-shaped groove is relatively poor.

[0047] In this embodiment, by optimizing the groove design of the groove unit 21, a first-shaped groove 210 and a second-shaped groove 211 are set in each adjacent sub-region 212, and the second-shaped groove 211 is located between the first-shaped grooves 210, which cleverly combines the respective advantages of the first-shaped groove 210 and the second-shaped groove 211, so that the Schottky diode 2 maintains high voltage resistance while also obtaining good surge capability.

[0048] It is worth noting that each trench unit 21 constitutes a unit cell structure, and this unit cell structure is arranged on the first side of the semiconductor layer 20 .

[0049] The barrier layer 22 is located on the first side of the semiconductor layer 20. The metal layer 23 includes a first metal layer 230 and a second metal layer 231. The first metal layer 230 is located on the side of the barrier layer 22 away from the semiconductor layer 20, and the second metal layer 231 is located on the second side of the semiconductor layer 20.

[0050] In this embodiment, the barrier layer 22 contacts the semiconductor layer 20 to form a Schottky barrier, which is the key for the Schottky diode 2 to achieve the rectification function. It can effectively reduce the reverse leakage current and improve the reverse blocking ability of the Schottky diode 2, thereby ensuring the stable operation of the Schottky diode 2 in the circuit.

[0051] The first metal layer 230 covers the barrier layer 22 to form the anode of the Schottky diode 2, and the second metal layer 231 covers the second side of the semiconductor layer 20 to form the cathode of the Schottky diode 2, such that the Schottky diode 2 has a low resistance during forward conduction and exhibits a high impedance characteristic during reverse blocking.

[0052] It should be noted that the material of the barrier layer 22 can be metals such as titanium and nickel, and the materials of the first metal layer 230 and the second metal layer 231 can be metals such as aluminum and titanium. The specific materials of the barrier layer 22, the first metal layer 230, and the second metal layer 231 are not specifically limited herein and need to be selected according to the actual situation.

[0053] Further, please refer to Figure 6 and Figure 7 , the first-shaped groove 210 is a strip-shaped groove, and the second-shaped groove 211 is a dot-shaped groove.

[0054] In any sub-region 212, two first-shaped grooves 210 are arranged oppositely, and at least one second-shaped groove 211 is located between the two first-shaped grooves 210.

[0055] In this embodiment, the design of the strip-shaped groove helps to disperse the electric field, reduce the electric field concentration, thereby improving the breakdown voltage performance of the Schottky diode 2. Due to the continuity of the strip-shaped groove, it can effectively reduce the electric field strength and reduce the risk of reverse breakdown. The design of the dot-shaped groove increases the area of the Schottky barrier, thereby increasing the current flow path, reducing the forward voltage drop, and improving the surge current withstand ability.

[0056] In any sub-region 212 of the groove unit 21, opposite strip-shaped grooves and dot-shaped grooves located between the two strip-shaped grooves are provided. This layout enables each sub-region 212 to make full use of the high-voltage resistance characteristic of the strip-shaped groove and the low forward voltage drop and high surge ability of the dot-shaped groove.

[0057] Further, please refer to again Figure 6 and Figure 7, the area where the trench unit 21 is located includes a first sub-region 2120, a second sub-region 2121, a third sub-region 2122, and a fourth sub-region 2123, and the shapes of the first sub-region 2120, the second sub-region 2121, the third sub-region 2122, and the fourth sub-region 2123 are rectangular.

[0058] The first sub-region 2120 is adjacent to the second sub-region 2121 and the third sub-region 2122, the second sub-region 2121 is adjacent to the first sub-region 2120 and the fourth sub-region 2123, the first sub-region 2120 and the fourth sub-region 2123 are opposite to each other, and the second sub-region 2121 and the third sub-region 2122 are opposite to each other.

[0059] The first sub-region 2120 and the second sub-region 2121 are distributed along the first direction A1, the third sub-region 2122 and the fourth sub-region 2123 are distributed along the first direction A1, the first sub-region 2120 and the third sub-region 2122 are distributed along the second direction A2, and the second sub-region 2121 and the fourth sub-region 2123 are distributed along the second direction A2, where the first direction A1 and the second direction A2 are perpendicular to each other.

[0060] In any one of the sub-regions 212, two first-shaped trenches 210 are distributed along the first direction A1 or the second direction A2, and at least one second-shaped trench 211 is located between the two first-shaped trenches 210.

[0061] In this embodiment, the sub-regions 212 of the trench unit 21 are arranged adjacent to each other in a specific arrangement. Specifically, the first sub-region 2120 and the second sub-region 2121 are linearly arranged in the first direction A1, the third sub-region 2122 and the fourth sub-region 2123 are linearly arranged in the first direction A1, and are arranged parallel to the first sub-region 2120 and the second sub-region 2121. The first sub-region 2120 and the third sub-region 2122 are linearly arranged in the second direction A2, and the second sub-region 2121 and the fourth sub-region 2123 are linearly arranged in the second direction A2, and are arranged parallel to the first sub-region 2120 and the third sub-region 2122.

[0062] Further, please refer to again Figure 7 , the trench distributions in the first sub-region 2120 and the fourth sub-region 2123 are the same, the trench distributions in the second sub-region 2121 and the third sub-region 2122 are the same, where the trench distributions in the first sub-region 2120 and the second sub-region 2121 are different.

[0063] In this embodiment, the first sub-region 2120 and the fourth sub-region 2123 are symmetrically distributed about the center of the trench unit 21. Similarly, the second sub-region 2121 and the third sub-region 2122 are symmetrically distributed about the center of the trench unit 21. This arrangement provides symmetry in the trench distribution within the first sub-region 2120, the second sub-region 2121, the third sub-region 2122, and the fourth sub-region 2123, which helps to balance the electric field and current, enabling the Schottky diode 2 to achieve a low forward voltage drop and high surge capability while maintaining high breakdown voltage.

[0064] Further, please refer again to Figure 7 , the first sub-region 2120 and the fourth sub-region 2123 include first-shaped trenches 210 disposed opposite each other along the first direction A1 and second-shaped trenches 211 located between the first-shaped trenches 210. The second sub-region 2121 and the third sub-region 2122 include first-shaped trenches 210 disposed opposite each other along the second direction A2 and second-shaped trenches 211 located between the first-shaped trenches 210.

[0065] In this embodiment, the first sub-region 2120 and the fourth sub-region 2123 include first-shaped trenches 210, which are strip trenches, disposed opposite each other along the first direction A1, and second-shaped trenches 211, which are dot trenches, located between the two first-shaped trenches 210, forming an interleaved arrangement pattern. The second sub-region 2121 and the third sub-region 2122 include first-shaped trenches 210, which are strip trenches, disposed opposite each other along the second direction A2, and second-shaped trenches 211, which are dot trenches, located between the two first-shaped trenches 210, forming another interleaved arrangement pattern. The strip trenches in these two different arrangement patterns can increase the current flow path, thereby reducing the forward voltage drop and improving the conduction efficiency of the Schottky diode 2. The dot trenches can serve as electric field buffer zones, reducing electric field concentration and improving the breakdown voltage capability of the Schottky diode 2. Therefore, the combination of the two can improve the breakdown voltage and surge capability of the Schottky diode 2.

[0066] Further, please refer to Figure 8 , Figure 8 is a top view of a trench unit 21 provided in this embodiment. The number of the second-shaped trenches 211 is multiple. The second-shaped trenches 211 in the first sub-region 2120 and the fourth sub-region 2123 are arranged along the second direction A2 between the relatively disposed first-shaped trenches 210. The second-shaped trenches 211 in the second sub-region 2121 and the third sub-region 2122 are arranged along the first direction A1 between the relatively disposed first-shaped trenches 210.

[0067] In this embodiment, between the relatively arranged first-shaped grooves 210, the number of second-shaped grooves 211 can be multiple, allowing the number of second-shaped grooves 211 to be selected and set under different circumstances, increasing the complexity of the structure of the Schottky diode 2.

[0068] Further, please refer to Figure 5 , the first-shaped groove 210 and the second-shaped groove 211 include a groove body 213, an oxide layer 214, and a conductor 215. Among them, the oxide layer 214 is attached to the inner wall of the groove body 213, and the conductor 215 is arranged on the oxide layer 214.

[0069] The orthographic projections of the oxide layer 214 and the conductor 215 on the semiconductor layer 20 are located within the orthographic projection of the groove body 213 on the semiconductor layer 20, and the orthographic projection of the conductor 215 on the semiconductor layer 20 is located within the orthographic projection of the oxide layer 214 on the semiconductor layer 20.

[0070] In this embodiment, the oxide layer 214 is attached to the inner wall of the groove body 213 as an insulating medium, and its main function is to provide electrical isolation to improve the stability of the Schottky diode 2. The conductor 215 is arranged in the accommodation space formed by the enclosure of the oxide layer 214 and is used to establish electrical connections and conduct charge transfer in the trench unit 21.

[0071] It should be noted that the material of the oxide layer 214 can be silicon dioxide, and it can usually be formed on the inner wall of the groove body 213 by using techniques such as thermal oxidation and chemical vapor deposition (CVD). The material of the conductor 215 can be polysilicon, metal, etc.

[0072] Further, please refer to again Figure 5 , the semiconductor layer 20 includes a first semiconductor layer 200 and a second semiconductor layer 201. The first semiconductor layer 200 and the second semiconductor layer 201 are stacked, and the trench unit 21 is formed on the side of the first semiconductor layer 200 away from the second semiconductor layer 201.

[0073] The first semiconductor layer 200 is an N-type semiconductor layer 20, and the second semiconductor layer 201 is an N+-type semiconductor layer 20.

[0074] In this embodiment, the first semiconductor layer 200 is an N-type semiconductor layer (N-type lightly doped semiconductor layer), and the number of its free electrons (negative charge carriers) is more than the number of holes (positive charge carriers). The second semiconductor layer 201 is an N+-type semiconductor (N-type heavily doped semiconductor layer). By adding a large amount of donor impurities to it, the concentration of its free electrons is significantly increased, and an effective electrical contact can be formed when it comes into contact with the first semiconductor layer 200.

[0075] Further, please refer to againFigure 5 , the orthographic projection of the trench unit 21 on the semiconductor layer 20 is located within the orthographic projection of the barrier layer 22 on the semiconductor layer 20, and the orthographic projection of the metal layer 23 on the semiconductor layer 20 coincides with the orthographic projection of the barrier layer 22 on the semiconductor layer 20.

[0076] In this embodiment, when the barrier layer 22 is disposed on the trench unit 21, the control of electrons in the trench unit 21 can be enhanced, and the current regulation ability of the gate to the trench unit 21 can be improved. A tight contact interface is formed between the metal layer 23 and the barrier layer 22, thereby ensuring the effective transmission of electrical signals between the metal layer 23 and the semiconductor layer 20 and improving the electrical performance of the Schottky diode 2.

[0077] Based on the same inventive concept, another object of the present application is to provide a mask plate for forming the trench unit 21 in any one of the foregoing Schottky diodes 2. The mask plate is mainly used in the photolithography step during the preparation of the Schottky diode 2. Usually, a layer of photoresist is coated on the oxide layer 214 formed in the Schottky diode 2, and the specific pattern on the mask plate is transferred to the photoresist by photolithography and then transferred to the oxide layer 214, and then the trench unit 21 is formed by etching and other operations.

[0078] Specifically, please refer to Figure 9 , Figure 10a , Figure 10b and Figure 10c , Figure 9 is a process step diagram of a Schottky diode 2 provided in this embodiment, Figures 10a - 10c is Figure 9 The corresponding process flow chart. The preparation of the Schottky diode 2 using the above mask plate includes the following steps.

[0079] Step S110, providing a semiconductor layer 20, wherein the semiconductor layer 20 includes opposite first and second sides.

[0080] In this embodiment, the semiconductor layer 20 includes a first semiconductor layer 200 and a second semiconductor layer 201 stacked, the first semiconductor layer 200 is an N-type semiconductor layer, and the second semiconductor layer 201 is an N+-type semiconductor layer.

[0081] Step S120, fabricating an insulating layer 24 on the first side of the semiconductor layer 20.

[0082] In this embodiment, an insulating layer 24 with a thickness of 400 nm to 600 nm is grown or deposited on the first side of the semiconductor layer 20. Exemplarily, an insulating layer 24 with a thickness of 400 nm, 500 nm, 600 nm, etc. is grown or deposited on the first side of the semiconductor layer 20, and the insulating layer 24 is usually silicon dioxide.

[0083] Step S130: Coat a layer of photoresist on the side of the insulating layer 24 away from the semiconductor layer 20, pattern the photoresist using a mask to form a photoresist window, and etch the insulating layer 24 based on the photoresist window to form an insulating layer window 240 for forming the trench unit 21.

[0084] Step S140: Etch the semiconductor layer 20 based on the insulating layer window 240 to form a trench body 213.

[0085] In this embodiment, first transfer the pattern on the mask to the insulating layer 24, use the insulating layer 24 as a hard mask, and perform dry etching on the semiconductor layer 20 based on the insulating layer window 240 to form a trench body 213.

[0086] Step S150: Fabricate an oxide layer 214 on the inner wall of the trench body 213.

[0087] In this embodiment, fabricate an oxide layer 214 with a thickness of 100 nm to 300 nm on the inner wall of the trench body 213. Exemplarily, fabricate an oxide layer 214 with a thickness of 100 nm, 200 nm, 300 nm, etc. on the inner wall of the trench body 213. The oxide layer 214 is also the gate oxide layer 214, which plays an insulating role between the gate and the semiconductor layer 20.

[0088] Step S160: Fabricate a conductor 215 on the oxide layer 214.

[0089] In this embodiment, phosphorus-doped polysilicon can be deposited on the oxide layer 214 to form a conductor 215.

[0090] Step S170: Remove the insulating layer 24 and the conductor 215 on the surface of the semiconductor layer 20 to form a trench unit 21.

[0091] In this embodiment, use dry etching to remove the insulating layer 24 and the conductor 215 on the surface of the semiconductor layer 20, and retain the oxide layer 214 and the conductor 215 in the trench body 213.

[0092] Step S180: Fabricate a barrier layer 22 on the first side of the semiconductor layer 20.

[0093] In this embodiment, deposit Schottky barrier metals such as titanium and nickel on the first side of the semiconductor layer 20 to form a barrier layer 22 required for Schottky contact.

[0094] Step S190: Fabricate a first metal layer 230 on the side of the barrier layer 22 away from the semiconductor layer 20, and fabricate a second metal layer 231 on the second side of the semiconductor layer 20 to form a Schottky diode 2.

[0095] In this embodiment, a first metal layer 230 and a second metal layer 231 are respectively formed on the side of the barrier layer 22 away from the semiconductor layer 20 and the second side of the semiconductor layer 20 to form the anode and cathode of the Schottky diode 2.

[0096] In summary, a Schottky diode and a mask provided by the present application. The Schottky diode includes a semiconductor layer, a trench unit, a barrier layer, and a metal layer. The semiconductor layer includes opposite first and second sides. The trench unit is formed on the first side of the semiconductor layer, and a plurality of trench units are arranged in an array on the first side. The trench unit includes a plurality of first-shaped trenches and a plurality of second-shaped trenches. Among them, the area where the trench unit is located includes a plurality of adjacent sub-regions, and each sub-region is provided with a first-shaped trench and a second-shaped trench located between the first-shaped trenches. The barrier layer is located on the first side of the semiconductor layer. The metal layer includes a first metal layer and a second metal layer. The first metal layer is located on the side of the barrier layer away from the semiconductor layer, and the second metal layer is located on the second side of the semiconductor layer. In this way, through the above structure, the breakdown voltage and surge capacity of the Schottky diode can be effectively improved.

[0097] The foregoing are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included within the protection scope of the present application.

Claims

1. A Schottky diode, characterized in that: The Schottky diode comprises: a semiconductor layer comprising a first side and a second side that are opposite; A trench unit is formed on a first side of the semiconductor layer, a plurality of the trench units are arrayed on the first side, the trench unit comprises a plurality of first-shaped trenches and a plurality of second-shaped trenches, wherein the region where the trench unit is located comprises a plurality of adjacent sub-regions, each of the sub-regions is provided with a first-shaped trench and a second-shaped trench located between the first-shaped trenches; a barrier layer, located on a first side of the semiconductor layer; The metal layer includes a first metal layer and a second metal layer, wherein the first metal layer is located on a side of the barrier layer away from the semiconductor layer, and the second metal layer is located on a second side of the semiconductor layer.

2. The Schottky diode according to claim 1, characterized in that: The first-shaped groove is a strip-shaped groove, and the second-shaped groove is a dot-shaped groove; In any of the sub-regions, two grooves of the first shape are arranged opposite to each other, and at least one groove of the second shape is located between the two grooves of the first shape.

3. The Schottky diode according to claim 1, characterized in that: The region where the trench unit is located includes a first sub-region, a second sub-region, a third sub-region and a fourth sub-region, and the first sub-region, the second sub-region, the third sub-region and the fourth sub-region are rectangular in shape; The first sub-region is adjacent to the second sub-region and the third sub-region, the second sub-region is adjacent to the first sub-region and the fourth sub-region, the first sub-region is opposite to the fourth sub-region, and the second sub-region is opposite to the third sub-region; The first sub-region and the second sub-region are distributed along a first direction, the third sub-region and the fourth sub-region are distributed along the first direction, the first sub-region and the third sub-region are distributed along a second direction, and the second sub-region and the fourth sub-region are distributed along the second direction, wherein the first direction and the second direction are perpendicular to each other; In any of the sub-regions, two grooves of the first shape are distributed along the first direction or the second direction, and at least one groove of the second shape is located between two grooves of the first shape.

4. The Schottky diode according to claim 3, characterized in that: The groove distribution in the first sub-region is the same as that in the fourth sub-region, and the groove distribution in the second sub-region is the same as that in the third sub-region, wherein the groove distribution in the first sub-region is different from that in the second sub-region.

5. The Schottky diode according to claim 3, characterized in that: The first sub-region and the fourth sub-region include first-shaped grooves arranged opposite to each other along a first direction and second-shaped grooves located between the first-shaped grooves, and the second sub-region and the third sub-region include first-shaped grooves arranged opposite to each other along a second direction and second-shaped grooves located between the first-shaped grooves.

6. The Schottky diode according to claim 3, characterized in that: There are multiple second-shape grooves, the second-shape grooves in the first sub-region and the fourth sub-region are arranged between the oppositely arranged first-shape grooves along the second direction, and the second-shape grooves in the second sub-region and the third sub-region are arranged between the oppositely arranged first-shape grooves along the first direction.

7. The Schottky diode according to claim 1, characterized in that: The first-shaped groove and the second-shaped groove include a groove body, an oxide layer and a conductor, wherein the oxide layer is arranged in contact with the inner wall of the groove body, and the conductor is arranged on the oxide layer; The orthographic projections of the oxide layer and the conductor on the semiconductor layer are located within the orthographic projection of the trench body on the semiconductor layer, and the orthographic projection of the conductor on the semiconductor layer is located within the orthographic projection of the oxide layer on the semiconductor layer.

8. The Schottky diode according to claim 1, characterized in that: The semiconductor layer comprises a first semiconductor layer and a second semiconductor layer, the first semiconductor layer and the second semiconductor layer are stacked, and the trench unit is formed on a side of the first semiconductor layer away from the second semiconductor layer; The first semiconductor layer is an N-type semiconductor layer, and the second semiconductor layer is an N+ type semiconductor layer.

9. The Schottky diode according to claim 1, characterized in that: The orthographic projection of the trench unit on the semiconductor layer is located within the orthographic projection of the barrier layer on the semiconductor layer, and the orthographic projection of the metal layer on the semiconductor layer coincides with the orthographic projection of the barrier layer on the semiconductor layer.

10. A mask, characterized in that: The mask is used to form a trench unit in the Schottky diode according to any one of claims 1-9.

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