A digital circuit logic optimization method based on the semi-tensor product of matrices

Abstract

The present invention discloses a digital circuit logic optimization method based on the semi-tensor product of matrices. The method is as follows: Calculate the re-convergence driving cut and the maximum fan-out free cone of the target node n to obtain the divisor set; simulate the internal nodes of the maximum fan-out free cone of the node n and the nodes in the divisor set, and then perform a reduction operation on the divisor set; use the semi-tensor product to calculate all feasible dependence functions of the node n with respect to the redundant divisor set removed; synthesize a new implementation of the node n based on a logic network with a smaller scale of dependence functions; if the number of logic gates in the new implementation of the node n is less than the number of internal nodes of its maximum fan-out free cone, then replace the maximum fan-out free cone with its new implementation; traverse all the target nodes in the logic network to complete the circuit size optimization. The optimization method of the present invention is based on a rigorous mathematical framework, with the core being the theory of semi-tensor product of matrices and the precise synthesis technology, and the optimization ability and stability are significantly improved.

Description

Technical Field

[0001] The present invention belongs to the field of digital circuit electronic design automation, and particularly relates to a digital circuit logic optimization method based on matrix semi-tensor product. Background Art

[0002] As the core technology of Electronic Design Automation (EDA), logic synthesis undertakes the key task of transforming the register transfer level circuit description into an optimized gate-level netlist. Among them, logic optimization is a crucial step, and its core optimization goal is to minimize the number of gates after technology mapping through the logic network. Boolean Resubstitution is a classic digital circuit logic optimization method. Its core idea is to use the nodes in the existing network (called divisors) to re-express the function of the target node, and replace the original implementation with a new implementation, that is, replace the maximum fanout free cone (MFFC) of the target node to achieve logic simplification. If this replacement can effectively reduce the scale of the logic network, a more efficient circuit structure can be obtained.

[0003] The traditional Boolean Resubstitution algorithm uses a heuristic enumeration strategy to implement the reconstruction of the target node. Its standard process includes: 1) calculating the re-convergence driving cut of the target node to determine the available divisors and the scale parameters of the maximum fanout free cone m ; 2) under the gate insertion amount constraint i ≤ min { m-1,3}, starting from i=0 to perform progressive enumeration search, gradually increasing the enumeration of new implementation schemes; 3) terminating immediately when a feasible solution is detected or i reaching the m-1 upper bound but still no solution is obtained; 4) when i increases to the threshold ( i =3 ), triggering heuristic decomposition: selecting j divisors ( j ∈ { 1,2}) to decompose the objective function. Since j logic gates need to be inserted, the constraint condition is updated synchronously to i≤ { m - 1 - j, 3} and i=0 is reset, and then the core processing flow is recursively executed for the decomposed objective function until the constraint condition is satisfied. When a feasible solution is found by this process, the maximum fanout free cone of the target node will be immediately replaced with this feasible solution.

[0004] The limitations of the traditional Boolean resubstitution algorithm are reflected in: 1) the premature convergence problem of the greedy search strategy - terminating the iteration when the first cost-reducing solution is found, and only being able to traverse a limited subset of the solution space; 2) the systematic lack of a mathematical framework - the lack of a quantitative evaluation model for optimizing path selection, resulting in the solution quality being sensitive to the initial conditions and search order, and it is difficult to ensure optimization stability. This double defect causes the traditional Boolean resubstitution algorithm to be prone to low optimization efficiency and quality fluctuations in the very large scale integrated circuit scenario. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a digital circuit logic optimization method based on the semi-tensor product (Semi-Tensor Product, STP) with significantly improved optimization ability and stability in view of the deficiencies of the prior art.

[0006] The technical solution adopted by the present invention to solve the above technical problem is: a digital circuit logic optimization method based on the semi-tensor product, and the method is as follows:

[0007] Traverse the logic network of the digital circuit to be optimized in topological order, and select a node in the logic network n as the target node to be optimized, calculate the reconvergence-driven cut and the maximum fanout free cone (MFFC, Maximum Fanout Free Cone) of the node n , and then collect the divisors to obtain a divisor set; simulate the internal nodes of the maximum fanout free cone of the node n and the nodes in the divisor set, and then perform a reduction operation on the divisor set according to the simulation results to obtain a divisor set with redundant divisors removed; then use the semi-tensor product to calculate all feasible dependence functions of the node n with respect to the divisor set with redundant divisors removed;

[0008] Select a dependence function with a smaller implementation scale of the logic network from all feasible dependence functions, and synthesize a new implementation of the node n based on this dependence function; if the number of logic gates in the new implementation of the node n is less than the number of internal nodes of the maximum fanout free cone of the node n , then replace the maximum fanout free cone of the node n with the new implementation of the node n ;

[0009] Traverse all target nodes in the logic network according to the above method to complete the circuit size optimization.

[0010] Preferably, the digital circuit logic optimization method based on the semi-tensor product of the present invention specifically includes the following steps:

[0011] Step 1: Traverse the logic network of the digital circuit to be optimized in topological order, select a node in the logic network n as the target node to be optimized, calculate the reconvergence drive cut and the maximum fan-out free cone of the node n , and then collect the divisors to obtain a divisor set;

[0012] The reconvergence drive cut and the divisors of the node n constitute a sub-network in the logic network. Consider the n leaf nodes of the reconvergence drive cut of the node q as the primary inputs of this sub-network, and characterize the internal nodes of the maximum fan-out free cone of the node n and the nodes in the collected divisor set as the Boolean functions of these q leaf nodes. Simulate the internal nodes of the maximum fan-out free cone of the node n and the nodes in the collected divisor set, and then perform a reduction operation on the collected divisor set according to the simulation results to obtain a divisor set with redundant divisors removed;

[0013] Step 2: Use semi-tensor product to calculate all feasible dependence functions of the node n with respect to the divisor set with redundant divisors removed;

[0014] Step 3: Use the open-source logic synthesis tool Espresso to solve the problem. According to the solution results, select a dependence function with a smaller implementation scale in the logic network from all feasible dependence functions. If the support of the obtained dependence function is not greater than 4, directly perform exact synthesis on it to obtain a new implementation of the node n . Otherwise, call the dec command in the open-source logic synthesis tool also to decompose the obtained dependence function into a LUT network composed of 4-LUTs, and perform exact synthesis on each LUT in this LUT network to obtain a new implementation of the node n ;

[0015] If the number of logic gates in the new implementation of the node n is less than the number of internal nodes of the maximum fan-out free cone of the node n , then replace the maximum fan-out free cone of the node n with the new implementation of the node n ;

[0016] Step 4: Repeat Step 1 to Step 3 until all target nodes in the logic network are traversed to complete the circuit size optimization.

[0017] Preferably, in Step 1, the method for performing a reduction operation on the collected divisor set is:

[0018] Step 1.1. Given a theorem, based on this theorem, transform the problem of reducing the divisor set into a problem of covering sets. The specific description of this theorem is as follows: Define a variable X= { x 1 , x 2 , ... , x q}, based on this variable X Given a Boolean function f ( X ) and an initial divisor set { z 1 , z 2 , ... , z p}, where p , q are positive integers, and the p divisors in this initial divisor set are all Boolean functions of X : g z1 ( X ) ，g z2 ( X ) ， ... ，g zp ( X ). If and only if there does not exist a pair of minterms ( M i , M j ) such that f ( M i ) ≠ f ( M j ), where i, j ∈{ 1, 2, ... ,2 q}, but for all k ∈{ 1, 2, ... ,p} there is g zk ( M i ) = g zk ( M j ), then the Boolean function f ( X ) is covered by the initial divisor set { z1 , z 2 , ... , z p}Redefine as f ( X ) = h(g z1 ( X ) ， g z2 ( X ) ， ... ，g zp ( X ))), where the Boolean function h is defined as a dependent function;

[0019] Step 1.2: The pairs of minterms distinguished by the node n form a set M . Iteratively select divisors from the initial divisor set of the node n . In each iteration, select the divisor that can cover the largest number of pairs of minterms not covered in the set M . Stop the iteration until the set M is completely covered, and obtain the divisor set with redundant ones removed.

[0020] Preferably, in the said Step 2, the method for calculating all feasible dependent functions of the node n with respect to the divisor set with redundant ones removed is as follows:

[0021] Step 2.1: Denote the divisor set with redundant ones removed as { d 1 , d 2 , ... , d p}. Denote the n leaf nodes of the re-convergence-driven cut of the node q as ( x 1 , x 2 , ... , x q ). Enter Step 2.2, and describe the Boolean logic of the node n and the divisor set with redundant ones removed through a structure matrix;

[0022] Step 2.2: Define the structure matrix of the Boolean function of the node n with respect to the original input as: ;

[0023] Among them , m f each column in f j is a binary column vector, taking values from the set , similarly, define the Boolean function structure matrix of the p divisors in the redundant divisor set removed with respect to the original input as:

[0024] ;

[0025] Among them , , m c each column in di j is a binary column vector, taking values from the set S v ;

[0026] Step 2.3. Represent the structure matrix of the dependency function as:

[0027] ;

[0028] Among them , m x each column in f j ’ is a binary column vector, taking values from the set S v , and establish the following equation:

[0029] ;

[0030] Normalize to , among which , at this time, equation (4) is converted to:

[0031] ;

[0032] Among them m f is known, while m y is obtained through calculation, and thus m x is deduced. Let m y be the calculation result of:

[0033] ;

[0034] Since at the calculation noden In each column of each matrix encountered in all feasible dependency functions regarding the divisor set, there is only one non - zero element 1. Let the matrix m y The j column of the only element that is 1 is in the r ( j ) row, where j ∈{ 1,2,…,2 q} and r ( j ) ∈{ 1,2,…,2 p}. After performing the multiplication of matrices m x and m y , the following equation is established:

[0035] ;

[0036] In addition, if for any j ∈{ 1,2,…,2 q}, there exists k ∈{ 1,2,…,2 p} such that r ( j ) ≠ k , then f ’ k can be either or , and they both satisfy equation (5). Therefore, through a single calculation using equation (7), all feasible dependency functions of node n regarding the divisor set can be obtained.

[0037] Compared with the prior art, the present invention has the following advantages: The digital circuit logic optimization method based on the semi - tensor product of matrices of the present invention is a new re - replacement algorithm. This digital circuit logic optimization method is based on a rigorous mathematical framework, and its optimization ability and stability are significantly improved. The core of the method of the present invention is the theory of the semi - tensor product of matrices and the exact synthesis technology. By performing the semi - tensor product operation of matrices to construct an algebraic representation model of Boolean logical relationships, combined with the exact synthesis technology for systematic mathematical derivation, it breaks through the local convergence limitation of the traditional heuristic enumeration algorithm, innovatively integrates the exact synthesis technology into the re - replacement process, systematically enhances the ability to explore the solution space and improves the optimization quality. For each target node of the logic network of the digital circuit to be optimized, all feasible dependency functions can be calculated once through the method of the present invention, which is the basis for its powerful digital circuit logic optimization ability. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 A sub-network of the logic network of the digital circuit to be optimized for the example;

[0039] Figure 2 The result of the precise synthesis of the dependency function in the embodiment;

[0040] Figure 3 For the node n The sub-network after the maximum fan-out free cone of is replaced by a new implementation. Detailed implementation mode

[0041] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments.

[0042] Embodiment: Figure 1 A sub-network of the logic network of the digital circuit to be optimized for the example. The logic network is optimized by using the digital circuit logic optimization method based on matrix semi-tensor product of the present invention, including the following steps:

[0043] Step 1, traverse the logic network of the digital circuit to be optimized in topological order, select the node n As the target node to be optimized, calculate the reconvergence drive cut and the maximum fan-out free cone of the node n , and then collect the divisors to obtain the divisor set. Figure 1 Shows the reconvergence drive cut and the divisors of the node n , Figure 1 There are 6 AND gates in total. The reconvergence drive cut of the node n has 4 leaf nodes x 1 , x 2 , x 3 , x 4 , and the collected divisors are x 1 , x 2 , x 3 , x 4 , z 5 , z 6 , z 7 , z 8 , among which x 1 , x 2 , x3 , x 4 is both the leaf node of the re-convergence-driven cut of the node n and the divisor. And the nodes n and the nodes n’ are the nodes in the maximum fan-out free cone of the node n . The re-convergence-driven cut and the divisor of the node n constitute a sub-network in the logic network, regarding the leaf nodes x 1 , x 2 , x 3 , x 4 as the original inputs of this sub-network, characterizing the internal nodes of the maximum fan-out free cone of the node n and the nodes in the collected divisor set as the Boolean functions of these 4 leaf nodes, and simulating the internal nodes of the maximum fan-out free cone of the node n and the nodes in the collected divisor set. The simulation results are as follows:

[0044] x 1 : 0xaaaa,

[0045] x ２ : 0xcccc,

[0046] x ３ : 0xe0e0,

[0047] x ４ : 0xee00,

[0048] z 1 ：0x8888，

[0049] z ２ : 0x0a0a,

[0050] z ３ ：0x0088，

[0051] z ４ : 0x000a,

[0052] n: 0x0008,

[0053] n’: 0x000e。

[0054] Then, according to the simulation results, perform a reduction operation on the collected divisor set. The method of the reduction operation is as follows:

[0055] Step 1.1: Given a theorem, based on this theorem, transform the problem of reducing the divisor set into a problem of covering sets. The specific description of this theorem is as follows: Define a variable X= { x 1 , x 2 , ... , x q}, based on this variable X Given a Boolean function f ( X ) and an initial divisor set { z 1 , z 2 , ... , z p}, where p , q are positive integers, and the p divisors in this initial divisor set are all Boolean functions about X : g z1 ( X ) ，g z2 ( X ) ， ... ，g zp ( X ). If and only if there does not exist a pair of minterms ( M i , M j ) such that f ( M i ) ≠ f ( M j ), where i, j ∈{ 1, 2, ... ,2 q}, but for all k ∈{ 1, 2, ... ,p} there is g zk ( M i ) = g zk (M j ) then the Boolean function f ( X ) is re-expressed by the initial divisor set { z 1 , z 2 , ... , z p} as f ( X ) = h(g z1 ( X ) ， g z2 ( X ) ， ... ，g zp ( X )) where the Boolean function h is defined as the dependence function;

[0056] Step 1.2. The pairs of minterms distinguished by the node n form a set M . Divisors are iteratively selected from the initial divisor set of the node n . In each iteration, the divisor that can cover the largest number of pairs of minterms not covered in the set M is selected until the set M is completely covered. Then the iteration stops, and a divisor set with redundant ones removed is obtained, which contains two divisors: z 7 , z 8 .

[0057] Step 2. Calculate all feasible dependence functions of the node n with respect to the divisor set with redundant ones removed by the following method:

[0058] Step 2.1. Denote the divisor set with redundant ones removed as { d 1 , d 2}, where d 1 is z 7 , d 2 is z 8 . Denote the 4 leaf nodes of the re-convergence drive cut of the node n as ( x 1 , x 2, x 3 , x 4 ), enter step 2.2, and describe the nodes through the structure matrix n and the boolean logic for eliminating redundant divisor sets;

[0059] Step 2.2, for the nodes n The boolean function structure matrix for the original input is:

[0060] ;

[0061] where , m f Each column in is a binary column vector, taking values from the set . Similarly, the boolean function structure matrix for the 2 divisors in the redundant divisor set elimination with respect to the original input is:

[0062] ;

[0063] ;

[0064] where , , m c Each column in is a binary column vector, taking values from the set S v ;

[0065] Step 2.3, represent the structure matrix of the dependency function as:

[0066] ;

[0067] where , m x Each column in is a binary column vector, taking values from the set S v , establish the following equation:

[0068] ;

[0069] Normalize to , where , and at this time the above equation is converted to:

[0070] ;

[0071] where m f is known, and my It is calculated and thus deduced that m x , let m y The calculation result of is:

[0072] ;

[0073] All feasible dependency functions of node with respect to the divisor set are obtained through a single calculation using equation (7) as n 0x8 .

[0074] n Step 3: Use the open-source logic synthesis tool Espresso to solve the problem, and select a dependency function with a smaller logic network implementation scale from all feasible dependency functions according to the solution result. Since in this embodiment, all feasible dependency functions of node with respect to the divisor set after removing redundancy are unique, and the support size of this dependency function is 3, the dependency function can be directly and precisely synthesized to obtain a new implementation of node n n . Among them, the result of the precise synthesis of the dependency function is as shown in Figure 2 .

[0075] n Since the number of logic gates in the new implementation of node is 1, which is less than the number 2 of the internal nodes of the maximum fan-out free cone of node n , the maximum fan-out free cone of node is replaced with the new implementation of node n . n n Figure 3 Figure shows the sub-network after the maximum fan-out free cone of node is replaced with the new implementation, that is, the optimized sub-network Figure 3 shows the sub-network after the maximum fan-out free cone of node is replaced with the new implementation, that is, the optimized sub-network n .

[0076] Step 4: Repeat Step 1 to Step 3 until all target nodes in the logic network are traversed to complete the circuit size optimization

Claims

1. A digital circuit logic optimization method based on the semi-tensor product of matrices, characterized in that, The method is as follows: Traverse the logic network of the digital circuit to be optimized in topological order and select a node in the logic network n as the target node to be optimized, calculate the re-convergence driving cut and the maximum fan-out free cone of the node n , then collect the divisors to obtain a divisor set; simulate the internal nodes of the maximum fan-out free cone of the node n and the nodes in the divisor set, and then perform a reduction operation on the divisor set according to the simulation results to obtain a divisor set with redundant divisors removed; then use semi-tensor product to calculate all feasible dependency functions of the node n with respect to the divisor set with redundant divisors removed; Select a dependency function with a smaller logical network implementation scale from all feasible dependency functions, and synthesize new implementations of nodes based on this dependency function n ; If the number of logic gates in the new implementation of node n is less than the number of internal nodes in the maximum fan-out free cone of node n , then replace the maximum fan-out free cone of node n with the new implementation of node n . Traverse all target nodes in the logic network according to the above method to complete the circuit size optimization.

2. The digital circuit logic optimization method based on the semi-tensor product of matrices according to claim 1, wherein This method specifically includes the following steps: Step 1. Traverse the logic network of the digital circuit to be optimized in topological order, select a node in the logic network n as the target node to be optimized, calculate the reconvergence drive cut and the maximum fanout free cone of the node n , and then collect the divisors to obtain the divisor set; Node n 's re-convergence driven cut and divisors form a sub-network in the logic network. Regarding the n leaf nodes of the re-convergence driven cut of q as the original inputs of this sub-network, and characterizing the internal nodes of the maximum fan-out free cone of node n and the nodes in the collected divisor set as the Boolean functions of these q leaf nodes. Simulating the internal nodes of the maximum fan-out free cone of node n and the nodes in the collected divisor set, and then performing a reduction operation on the collected divisor set according to the simulation results to obtain a divisor set with redundant ones removed; Step 2. Calculate the nodes using semi-tensor product n All feasible dependency functions regarding the elimination of redundant divisor sets Step 3: Use the open-source logic synthesis tool Espresso for solving. According to the solution result, select a dependency function with a smaller logic network implementation scale from all feasible dependency functions. If the support of the obtained dependency function is not greater than 4, directly perform exact synthesis on it to obtain a new implementation of the node n , otherwise, call the dec command in the open-source logic synthesis tool also to decompose the obtained dependency function into a LUT network composed of 4-LUTs, and perform exact synthesis on each LUT in this LUT network to obtain a new implementation of the node n ; If the number of logic gates in the new implementation of a node n is less than the number of internal nodes of the maximum fan-out free cone of a node n , then replace the maximum fan-out free cone of the node n with the new implementation of the node n ; Step 4: Repeat Step 1 to Step 3 until all target nodes in the logic network are traversed to complete the circuit size optimization.

3. The digital circuit logic optimization method based on the semi-tensor product of matrices according to claim 2, wherein In the said Step 1, the method for performing a reduction operation on the collected divisor set is: Step 1.

1. Given a theorem, based on this theorem, the problem of reducing the divisor set is transformed into a problem of covering sets. The specific description of this theorem is as follows: Define variables X= { x 1 , x 2 , ... , x q}, based on this variable X Given a Boolean function f ( X ) and an initial divisor set { z 1 , z 2 , ... , z p}, where p , q are positive integers, and the p divisors in this initial divisor set are all Boolean functions of X : g z1 ( X ) ，g z2 ( X ) ， ... ，g zp ( X ). If and only if there does not exist a pair of minterms ( M i , M j ) such that f ( M i ) ≠ f ( M j ), where i, j ∈{ 1, 2, ... ,2 q}, but for all k ∈{ 1, 2, ... ,p} there is g zk ( M i ) = g zk ( M j ), then the Boolean function f ( X ) is covered by the initial divisor set { z 1 , z 2 , ... , z p} reformulated as f ( X ) =h(g z1 ( X ) ， g z2 ( X ) ， ... ，g zp ( X ))), where the Boolean function h is defined as a dependency function; Step 1.

2. The minterms pairs distinguished by node n form a set M . Divisors are iteratively selected from the initial divisor set of node n . In each iteration, the divisor that can cover the largest number of minterms pairs not covered in set M is selected until set M is completely covered, at which point the iteration stops, and a divisor set with redundant elements removed is obtained.

4. The digital circuit logic optimization method based on the semi-tensor product of matrices according to claim 3, characterized in that, In the said step 2, the semi-tensor product is used to calculate the nodes n The method for eliminating all feasible dependence functions of the redundant divisor set is as follows: Step 2.1: Denote the divisor set after removing redundancy as { d 1 , d 2 , ... , d p}, and denote the n number of leaf nodes of the re-convergence-driven cut of node q as ([[]] x x 1 , x 2 , ... , x q ). Then enter Step 2.2, and describe the Boolean logic of node n and the divisor set after removing redundancy through a structure matrix; Step 2.2, Define nodes n The Boolean function structure matrix for the original input is as follows: ； Among them , m f each column in f j is a binary column vector, taking values from the set , similarly, define the Boolean function structure matrix of the p divisors in the redundant divisor set removed with respect to the original input as: ； Among them , , m c each column in di j is a binary column vector, taking values from the set S v ; Step 2.3: Represent the structure matrix of the dependency function as: ； Among them , m x each column in f j ’ is a binary column vector, taking values from the set S v , and establish the following equation: ； Convert to the normalized form , where . At this time, equation (4) is converted to: ； Among them m f is known, and m y is obtained by calculation, and thus it is deduced that m x , let m y The calculation result of is: ； Since in the computing node n each column of each matrix encountered in all feasible dependency function processes regarding the divisor set has only one non-zero element 1. Let the matrix m y The only element equal to 1 in the j th column is in the r ( j )th row, where j ∈{ 1, 2,…,2 q} and r ( j ) ∈{ 1,2,…,2 p}. After performing the multiplication of matrices m x and m y , the following equation is established: ； In addition, if for any j ∈ { 1,2,…,2 q}, there exists k ∈ { 1,2,…,2 p} such that r ( j ) ≠ k , then f ’ k can be either or , and they both satisfy equation (5). Therefore, all feasible dependence functions of node n with respect to the divisor set can be obtained through a single calculation using equation (7).

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