Clock data recovery circuit system and clock recovery operation method based thereon

Abstract

The present application discloses a clock data recovery circuit system and a clock recovery operation method based thereon. The clock data recovery circuit system includes: a data detection control module, a phase detector, a filter, and a voltage-controlled oscillator. The first input of the phase detector is used to receive a signal to be processed, and the second input of the phase detector is connected to the output of the voltage-controlled oscillator, which is the output of the clock data recovery circuit system. The filter includes: a gain module, an integration module, and an adder. The input of the gain module and the input of the integration module are both connected to the output of the phase detector. The clock data recovery circuit system and the clock recovery operation method based thereon solve the problem in the prior art that when the clock data recovery circuit system is started, the integration module is simultaneously started. Due to a large initial frequency difference and insufficient gain of the gain circuit, the integration module is locked into an error interval state, resulting in frequency tracking errors.

Description

Technical Field

[0001] The present application relates to the field of clock data recovery, and in particular to a clock data recovery circuit system and a clock recovery operation method based thereon. Background Art

[0002] A signal to be processed is sent, containing a clock. A clock data recovery circuit system in the first communication circuit then recovers the clock from the signal to be processed, obtaining a recovered clock signal. The first communication circuit then samples the signal to be processed using the recovered clock signal to obtain first recovered data, which reflects the true intent of the signal to be processed sent by the second communication circuit. The recovered clock signal directly affects the accuracy of the first recovered data, so recovering an accurate recovered clock signal is crucial for both the first and second communication circuits and is the subject of discussion in this application.

[0003] The clock data recovery circuit system includes: a phase detector, a filter and a voltage-controlled oscillator. The first input end of the phase detector is used to receive the signal to be processed. The filter includes a gain module, an integration module and an adder. The output end of the phase detector is connected to the input end of the gain module and the input end of the integration module. The output end of the gain module is connected to the first input end of the adder. The output end of the integration module is connected to the second input end of the adder. The output end of the adder is connected to the input end of the voltage-controlled oscillator. The output end of the voltage-controlled oscillator is the output end of the clock data recovery circuit system. The output end of the clock data recovery circuit system outputs a recovered clock signal. The second input end of the phase detector inputs the recovered clock signal (that is, the second input end of the phase detector is connected to the voltage-controlled oscillator).

[0004] The clock recovery principle of the clock data recovery circuit system is as follows: First, the phase detector compares the processed signal with the recovered clock signal. If there is a frequency difference between the processed signal and the recovered clock signal, a phase difference will occur. The phase detector compares this phase difference and converts it into a corresponding voltage control signal. The voltage control signal is filtered by a filter to generate a control signal for the voltage-controlled oscillator, thereby adjusting the output clock frequency of the voltage-controlled oscillator. Through repeated phase detection and adjustment, the frequency of the recovered clock signal at the output of the voltage-controlled oscillator eventually matches the clock signal in the processed signal received at the first input of the phase detector. At this point, the clock data recovery circuit system enters a state of continuous and stable frequency tracking.

[0005] In the prior art, a clock data recovery circuit system generally starts up all components together, including the integration module. After startup, when the clock data recovery circuit system tracks the changes in the clock signal in the signal to be processed, the gain module plays a leading role in tracking the clock signal in the signal to be processed because the integration module has a certain hysteresis in its response when it is first started.

[0006] When it is just started, the frequency difference between the recovered time signal and the clock signal in the signal to be processed is large. At this time, the integration module does not have the ability to track the frequency (because the integration module does not initially have accumulated frequency information). If the gain module gain is not enough, it will not be able to track the phase change in real time, resulting in phase error. If a tracking frequency error occurs during the tracking process, the integration module accumulates the effect of clock changes, and the integration module will accumulate tracking frequency errors. The integration module will accumulate phase differences (ie, frequencies), so the wrong frequencies will also be accumulated, making the tracking frequency errors larger and larger, and eventually causing the clock data recovery circuit system to be locked in the error interval state (the error interval state is: the integration module is locked in the error interval state, and the integration module has an error in tracking the frequency). This results in a difference in the frequency of the clock signal in the recovered time signal and the signal to be processed. This difference is mainly the following (such as Figure 4 As shown):①( Figure 4 (① indicates this state) There is a fixed deviation between the recovered time signal and the clock signal frequency in the signal to be processed (for example, the clock frequency range of the received signal to be processed is 4.9GHz to 5GHz, but after being locked in the error range, the frequency range of the recovered clock signal is 4.8GHz to 4.9GHz). When sampling the signal to be processed, the sampling time period will be delayed or advanced; (②) Figure 4 (② in the figure indicates this state) The recovered time signal differs significantly from the clock signal in the processed signal, and the recovered time signal completely fails to track the clock signal in the processed signal, resulting in an increasing frequency deviation. Therefore, how to prevent the integration module from being simultaneously activated when the clock data recovery circuit system starts up, causing the integration module to lock into the wrong range due to the large initial frequency difference and insufficient gain of the gain circuit, resulting in frequency tracking errors, is an urgent problem to be solved in this application. Summary of the Invention

[0007] The present application aims to provide a clock data recovery circuit system and a clock recovery operation method based thereon, so as to solve the problem in the prior art that when the clock data recovery circuit system is started, the integration module is started at the same time, and due to the large initial frequency difference and insufficient gain of the gain circuit, the integration module is locked into the error interval state, resulting in frequency tracking errors.

[0008] To achieve the above objectives, this application adopts the following technical solutions:

[0009] The present application discloses a clock data recovery circuit system, comprising: a data detection control module, a phase detector, a filter, and a voltage controlled oscillator; the first input end of the phase detector is used to access a signal to be processed, the second input end of the phase detector is connected to the output end of the voltage controlled oscillator, the output end of the voltage controlled oscillator is the output end of the clock data recovery circuit system, the output end of the clock data recovery circuit system outputs a recovered clock signal, the phase detector is used to output a voltage control signal for controlling the voltage controlled oscillator according to the signal to be processed and the recovered clock signal; the filter comprises: a gain module, an integration module, and an adder, the input end of the gain module and the input end of the integration module are both connected to the output end of the phase detector The gain module is used to perform gain processing on the voltage control signal, and the integration module is used to perform integration processing on the voltage control signal; the output end of the gain module is connected to the first input end of the adder, and the output end of the integration module is connected to the second input end of the adder. The adder is used to add the voltage control signal after gain processing and the voltage control signal after integration processing to obtain an oscillation control signal; the output end of the adder is connected to the input end of the voltage controlled oscillator; the input end of the data detection control module is connected to the output end of the clock data recovery circuit system, and the data detection control module samples the signal to be processed according to the recovered clock signal to obtain first recovered data, and obtains the condition for starting the integration module according to the first recovered data.

[0010] Preferably, the data detection control module, the phase detector, the filter and the voltage-controlled oscillator are all installed in the first communication circuit, the data detection control module obtains a training data set from the first communication circuit, the first communication circuit stores the training data set, the first communication circuit is connected to the second communication circuit through an interface protocol communication, the second communication circuit stores the training data set, the second communication circuit processes the training data set and sends it to the first communication circuit, the training data set received by the first communication circuit from the second communication circuit is a signal to be processed; the data detection control module obtains the condition for starting the integration module based on the first recovered data: the first recovered data is consistent with the training data set.

[0011] Preferably, the steps for the data detection control module to start the integration module according to the first recovery data command are as follows: first, the data detection control module generates a comparison clock signal whose phase difference with the recovery clock signal is a degree, and the value range of a is 30~90; then, the data detection control module uses the comparison clock signal to recover the second recovery data from the signal to be processed; finally, the data detection control module obtains the condition for starting the integration module according to the first recovery data, and the condition for starting the integration module obtained by the data detection control module according to the first recovery data is: the first recovery data is consistent with the second recovery data.

[0012] Preferably, the integration module includes: a first integrator, the first integrator input end is connected to the phase detector output end, the first integrator output end is connected to the adder second input end, when the clock data recovery circuit system is started, the data detection control module disables the first integrator, and the data detection control module determines whether the conditions for starting the first integrator are met, and the conditions for starting the first integrator are that the first recovered data is consistent with the training data set, or that the first recovered data is consistent with the second recovered data.

[0013] Preferably, the integration module further includes: a second integrator, the second integrator input end is connected to the phase detector output end, the second integrator output end is connected to the adder third input end, and the second integrator tracking jitter capability is smaller than the tracking jitter capability of the first integrator.

[0014] Preferably, the filter is a loop filter including a gain module and an integration module.

[0015] Preferably, the value of a is 60.

[0016] The present application also discloses a clock recovery operation method, which is implemented based on the above-mentioned clock data recovery circuit system; the clock recovery operation method includes the following steps: S1, starting the clock data recovery circuit system, and at the same time, the data detection control module disables the first integrator in the integration module of the filter, and the clock data recovery circuit system performs phase detection and adjustment without the first integrator; S2, the data detection control module samples the signal to be processed according to the recovered clock signal to obtain the first recovered data, obtains the condition of the first integrator according to the first recovered data, and determines whether the condition is met. If not, wait; if so, proceed to step S3; S3, the data detection control module starts the first integrator in the filter; S4, the clock data recovery circuit system performs phase detection and adjustment with the first integrator; S5, the clock data recovery circuit system enters a stable tracking state.

[0017] Preferably, in step S1 , the clock data recovery circuit system is started and the second integrator is started at the same time.

[0018] Preferably, in step S1 , the clock data recovery circuit system is started while the second integrator is not started, and in step S3 , the first integrator in the filter is started while the second integrator is started.

[0019] Compared with the existing technology, this application has the following beneficial effects:

[0020] In the present application, a data detection control module is used to detect the recovered clock signal output by the clock data recovery circuit system in real time, and the recovered clock signal is used to sample the signal to be processed to obtain the first recovered data. The first recovered data is used to capture the conditions suitable for starting the first integrator in the integration module. Then, capturing the appropriate conditions is the key point to control the start-up operation of the first integrator. The conditions for starting the first integrator provided in the present application are: the first recovered data is consistent with the second recovered data, or the first recovered data is consistent with the training data set. This avoids starting the first integrator before the frequency difference between the recovered clock signal and the signal to be processed is large, causing the first integrator to be locked into the error interval state, thereby achieving the goal that the first integrator of the integration module is not connected until the clock signal in the signal to be processed is close to the recovered clock signal, and the first integrator can perform the accumulation effect in the filter, avoiding the accumulation of the following frequency error when the frequency difference is large, and avoiding the amplification of the following frequency error. The first integrator is started after the frequency difference is small, and the clock data recovery circuit system retains the original recovered clock signal when the frequency difference is small. At this time, the accumulation effect of the first integrator is turned on, so that the final recovered clock signal is closer to the clock signal in the signal to be processed, so the accuracy of the first recovered data subsequently recovered using the recovered clock signal is higher, avoiding the entire clock data recovery circuit system being locked in the error interval state and causing the first recovered data obtained by sampling to be wrong.

[0021] Other advantages, objectives and features of the present application will be reflected in part through the following description, and in part will be understood by those skilled in the art through study and practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 This is the circuit block diagram of the clock data recovery circuit system.

[0023] Figure 2 A circuit block diagram between a phase detector and an adder in one embodiment.

[0024] Figure 3 FIG. 4 is a circuit block diagram between a phase detector and an adder in another embodiment.

[0025] Figure 4 This is a comparison diagram of the clock signal recovered in the error interval state and the clock signal in the signal to be processed.

[0026] Figure 5 It is a comparison diagram of the signal to be processed RXD, the recovered clock signal HCLK and the comparison clock signal DCLK.

[0027] Figure 6 This is a comparison diagram of the signal to be processed RXD, the clock signal of the signal to be processed RXD, the recovered clock signal HCLK of the present application, and the recovered clock signal in the error interval state. DETAILED DESCRIPTION

[0028] In order to make the technical means, creative features, objectives and functions achieved by this application clearer and easier to understand, this application is further elaborated below in conjunction with the accompanying drawings and specific implementation methods.

[0029] like Figure 1 As shown, the present application first discloses a clock data recovery circuit system, including: a data detection control module, a phase detector, a filter and a voltage controlled oscillator; the first input end of the phase detector is used to access the signal to be processed RXD, the second input end of the phase detector is connected to the output end of the voltage controlled oscillator, the output end of the voltage controlled oscillator is the output end of the clock data recovery circuit system, the output end of the clock data recovery circuit system outputs the recovered clock signal HCLK, the phase detector is used to output a voltage control signal for controlling the voltage controlled oscillator according to the signal to be processed RXD and the recovered clock signal HCLK; the filter includes: a gain module, an integration module and an adder, the input end of the gain module and the input end of the integration module are both connected to the output end of the phase detector, the gain module is used to perform gain processing on the voltage control signal, and the integration module is used to perform voltage control processing on the voltage control signal. The voltage control signal is integrated; the output end of the gain module is connected to the first input end of the adder, the output end of the integration module is connected to the second input end of the adder, and the adder is used to add the voltage control signal after the gain processing and the voltage control signal after the integration processing to obtain an oscillation control signal; the output end of the adder is connected to the input end of the voltage controlled oscillator; the input end of the data detection control module is connected to the output end of the clock data recovery circuit system, the data detection control module samples the signal to be processed RXD according to the recovered clock signal HCLK to obtain first recovered data, and obtains a condition for starting the integration module according to the first recovered data (when the integration module is started without distinguishing between the first integrator and the second integrator, the condition for starting the integration module is that the first recovered data is consistent with the training data set, or that the first recovered data is consistent with the second recovered data).

[0030] As an embodiment of controlling an integration module based on a recovered clock signal HCLK, a data detection control module, a phase detector, a filter, and a voltage-controlled oscillator are all installed in a first communication circuit. The data detection control module obtains a training data set from the first communication circuit, the training data set being stored in the first communication circuit. The first communication circuit is connected to a second communication circuit via an interface protocol, the second communication circuit being stored in the training data set. The second communication circuit processes the training data set and transmits it to the first communication circuit. The training data set received by the first communication circuit from the second communication circuit is a signal to be processed RXD. The data detection control module determines, based on the first recovered data, that a condition for activating the integration module is that the first recovered data is consistent with the training data set. In this embodiment, when the data detection control module is able to obtain the training data set from the first communication circuit, it recovers the signal to be processed RXD using the recovered clock signal HCLK to obtain a first recovered signal. During the recovery process, the recovered clock signal HCLK is used to sample the center position data of each time period of the signal to be processed RXD to obtain the first recovered signal. The consistency of the first recovered signal with the training data set is determined, that is, whether they are identical. If they are identical, it indicates that the frequency difference between the recovered clock signal HCLK and the clock signal of the processed signal RXD is not large (in other words, the recovered clock signal HCLK and the clock signal of the processed signal RXD are close, which makes the first recovered data consistent with the training data set). This indicates that the recovered clock signal HCLK is required, and the first integrator in the integration module can be driven to operate. If they are inconsistent, it is determined that the first integrator in the integration module cannot operate.

[0031] As another embodiment of controlling the integration module according to the recovered clock signal HCLK, the steps for the data detection control module to start the integration module according to the first recovered data command are as follows: first, the data detection control module generates a comparison clock signal DCLK whose phase difference with the recovered clock signal HCLK is a degree, and the value range of a is 30~90; then, the data detection control module uses the comparison clock signal DCLK to recover the second recovered data from the signal to be processed RXD; finally, the data detection control module obtains the condition for starting the integration module according to the first recovered data, and the condition for starting the integration module obtained by the data detection control module according to the first recovered data is: the first recovered data is consistent with the second recovered data. The preferred value of a is 60. Compared with the previous embodiment, this embodiment realizes the condition for starting the integration module according to the first recovered data without knowing the training data set. The data detection control module generates a comparison clock signal DCLK whose phase difference with the recovered clock signal HCLK is a degree, and the phase difference between the comparison clock signal DCLK and the recovered clock signal HCLK is a (the phase difference is reflected as follows: Figure 5There is a distance between the dotted line position of the comparison clock signal DCLK and the dotted line position of the recovery clock signal HCLK. If there is no phase difference, the dotted line position of the comparison clock signal DCLK and the dotted line position of the recovery clock signal HCLK coincide with each other). If a is small, then the phase difference between the comparison clock signal DCLK and the recovery clock signal HCLK is small. Figure 5 As shown ( Figure 5 In the figure, the X-axis is time, and the Y-axis is level amplitude value). The first recovered signal is obtained by using the recovered clock signal HCLK to recover the signal to be processed RXD (in the recovery process, the first recovered signal can be obtained by sampling the center position data of each time period of the signal to be processed RXD using the recovered clock signal HCLK). The data detection control module uses the comparison clock signal DCLK to recover the second recovered data from the signal to be processed RXD. Since the recovery is to sample the center position data of each time period, and the phase difference between the comparison clock signal DCLK and the recovered clock signal HCLK is small, it is very important to judge the consistency of the first recovered signal obtained by using the HCLK to recover the clock signal HCLK to sample the signal to be processed RXD and the second recovered signal obtained by using the comparison clock signal DCLK to sample the signal to be processed RXD (that is, to judge whether they are exactly the same). If they are the same (such as Figure 5 The dotted line corresponds to the data1 (the first data) of the signal to be processed RXD, and the next data of the signal to be processed RXD will not be sampled. This is the same situation; different situations, Figure 5 The dashed line in the middle corresponds to two data points. The frequency difference between the recovered clock signal HCLK and the clock signal to be processed RXD is determined to be small, and the first integrator can be activated. The significance of this approach is that if the recovered clock signal HCLK is close to the clock signal in the processed signal RXD, then the comparison clock signal DCLK, obtained after a phase shift of a°, can still sample the second recovered data. Furthermore, the second recovered data is consistent with the first recovered data, indicating that the frequency difference between the recovered clock signal HCLK and the clock signal to be processed RXD is small, meeting the conditions for activating the first integrator.

[0032] like Figure 1 as well as Figure 2 As shown, as an embodiment, the integration module includes: a first integrator, the first integrator input end is connected to the phase detector output end, the first integrator output end is connected to the adder second input end, when the clock data recovery circuit system is started, the data detection control module disables the first integrator, and the data detection control module determines whether the condition for starting the first integrator is met, and the condition for starting the first integrator is that the first recovered data is consistent with the training data set, or that the first recovered data is consistent with the second recovered data.

[0033] In this embodiment, the first integrator can be a general integrator. The general integrator has normal jitter tracking capability and can normally track the jitter changes of the clock signal in the signal to be processed RXD. The integration module is mainly used to track the jitter of the clock signal in the signal to be processed RXD, so as to avoid the first integrator amplifying the erroneous tracking. The first integrator is started only when the condition is met (the condition is: the first recovered data is consistent with the training data set, or the first recovered data is consistent with the second recovered data). When the condition is met, it proves that the recovered clock signal HCLK is close to the clock signal in the signal to be processed RXD. This is the time to start the first integrator. Then, when the entire clock data recovery circuit system is phase-locked, the first integrator is locked in a normal area.

[0034] like Figure 3 As shown, as another embodiment, the integration module further includes: a second integrator, the input end of the second integrator is connected to the output end of the phase detector, the output end of the second integrator is connected to the third input end of the adder, and the tracking jitter capability of the second integrator (the evaluation index of the tracking jitter capability is jitter tolerance (jitter tolerance refers to the maximum jitter amplitude that the CDR can withstand while maintaining normal operation)) is smaller than the tracking jitter capability of the first integrator (it should be noted here that: if the tracking jitter capability of the first integrator is greater than the tracking jitter capability of the second integrator, then when the condition (large difference between the recovered clock signal HCLK and the clock signal in the to-be-processed signal RXD) is not met, the tracking capability of the second integrator is small, and the tracking error will not be amplified after startup, so the second integrator is started at the same time when the integration module is started).

[0035] In this application, the filter is a ring filter including a gain module and an integration module. Of course, the filter can also be other filters including a gain module and an integration module.

[0036] How to realize the data detection control module to control the first integrator to start, such as Figure 2As shown, the first integrator includes an integration function unit and a controllable switch. The integration function unit is primarily composed of an operational amplifier, a resistor, and a capacitor. The controllable switch, for example, is a switching transistor. The collector of the switching transistor is connected to the low-voltage power supply terminal of the integration function unit, the high-voltage power supply terminal of the integration function unit is connected to the positive terminal of the power supply, and the emitter of the switching transistor is grounded. The signal output terminal of the integration function unit is the output terminal of the first integrator, and the signal input terminal of the integration function unit is the input terminal of the first integrator. The base of the switching transistor is connected to the output terminal of the data detection control module. When the output terminal of the data detection control module outputs a high level, the emitter and collector of the switching transistor are closed, thus activating the first integrator; when the output terminal of the data detection control module outputs a low level, the emitter and collector of the switching transistor are disconnected, thus disabling the first integrator. Of course, other controllable switches, such as MOSFETs, can also be provided, as long as they can enable the data detection control module to disable or activate the first integrator. Controlling the activation or disabling of the first integrator can also be achieved through digital logic.

[0037] The present application also discloses a clock recovery method, which is implemented based on the aforementioned clock data recovery circuit system. The method includes the following steps: S1: activating the clock data recovery circuit system, while the data detection control module disables the first integrator in the filter's integration module, and the clock data recovery circuit system performs phase detection and adjustment without the first integrator; S2: the data detection control module samples the processed signal RXD according to the recovered clock signal HCLK to obtain first recovered data, obtains a condition for the first integrator based on the first recovered data, and determines whether the condition is met. If not, the method waits; if so, the method proceeds to step S3; S3: the data detection control module activates the first integrator in the filter; S4: the clock data recovery circuit system performs phase detection and adjustment with the first integrator; S5: the clock data recovery circuit system enters a stable tracking state. This method can be used with a ring filter consisting only of the first integrator and the gain module.

[0038] In the above steps, only the first integrator is not started in step S1, while all other components of the clock data recovery circuit system are started. In step S2, while the data detection control module is detecting, the components of the clock data recovery circuit system, excluding the data detection control module and the first integrator, operate as follows: S21, the phase detector compares the received signal to be processed RXD with the recovered clock signal HCLK. After comparison, the phase detector outputs a voltage control signal. S22, the voltage control signal is amplified by the gain module, that is, the gain module proportionally amplifies the voltage control signal to obtain a gain-adjusted signal. If a second integrator is operating, the second integrator has only a small tracking jitter capability. The second integrator integrates the voltage control signal to obtain an integrated-adjusted signal, which does not amplify tracking frequency errors. S23, the adder adds the gain-adjusted signal and the integrated-adjusted signal to obtain an oscillation control signal. S24, the oscillation control signal is sent to the voltage-controlled oscillator, which adjusts the clock frequency of the recovered clock signal HCLK to the clock frequency of the signal to be processed RXD. This process is the phase detection and adjustment process performed by the clock data recovery circuit system without the first integrator.

[0039] During step S4, the clock data recovery circuit system continues to execute steps S21 through S24, except that the first integrator is involved in step S22. When the processed clock frequency at the output of the voltage-controlled oscillator matches the clock signal in the to-be-processed signal RXD input to the first input of the phase detector, clock data is recovered, and the clock data recovery circuit system enters a stable tracking state.

[0040] In the case of a second integrator, as another embodiment, the clock data recovery circuit system is activated in step S1 while the second integrator (the second integrator with weaker tracking capability) is also activated. Of course, the second integrator can be activated in step S1, and the maximum phase correction value that the second integrator can provide is smaller than the maximum phase correction value of the first integrator, and can even be significantly smaller than the phase correction value of the first integrator locked in the normal range.

[0041] As another embodiment, in step S3, the second integrator is started at the same time as the first integrator in the filter. In this embodiment, there may be multiple second integrators, for example, both the first integrator and the second integrator are started after the condition is met.

[0042] like Figure 6 As shown, Figure 6 The Y axis is the level amplitude value, and the X axis is the time. Figure 6The Y-axes of the signal to be processed RXD, the clock signal of the signal to be processed RXD, the recovered clock signal HCLK of the present application, and the recovered clock signal in the error interval state are all on a straight line. The recovered clock signal HCLK is basically the same as the clock signal of the signal to be processed RXD, while the clock signal in the error interval state is different from the recovered clock signal HCLK of the present application, and a clear phase deviation can be seen ( Figure 6 As can be seen from the vertical dotted line from the clock signal of the signal to be processed RXD to the error interval, the phase deviation of the state recovery clock signal in the error interval state can be improved, so the matching degree of the clock signal of the recovered clock signal HCLK and the signal to be processed RXD can be improved, and the accuracy of the first recovered data obtained by sampling the signal to be processed RXD using the recovered clock signal HCLK can be improved.

[0043] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application and are not limiting. Although the present application has been described in detail with reference to the preferred embodiments, ordinary technicians in this field should understand that the technical solutions of the present application can be modified or replaced by equivalents without departing from the purpose and scope of the technical solutions of the present application, which should be included in the scope of the claims of the present application.

Claims

1. A clock data recovery circuit system, characterized in that: include: Data detection control module, phase detector, filter and voltage controlled oscillator; The first input terminal of the phase detector is used to receive the signal to be processed, and the second input terminal of the phase detector is connected to the output terminal of the voltage controlled oscillator. The output terminal of the voltage controlled oscillator is the output terminal of the clock data recovery circuit system. The output terminal of the clock data recovery circuit system outputs a recovered clock signal. The phase detector is used to output a voltage control signal for controlling the voltage controlled oscillator according to the signal to be processed and the recovered clock signal. The filter includes: a gain module, an integration module and an adder, the input end of the gain module and the input end of the integration module are both connected to the output end of the phase detector, the gain module is used to perform gain processing on the voltage control signal, and the integration module is used to perform integration processing on the voltage control signal; The output end of the gain module is connected to the first input end of the adder, and the output end of the integration module is connected to the second input end of the adder. The adder is used to add the voltage control signal after the gain processing and the voltage control signal after the integration processing to obtain an oscillation control signal; the output end of the adder is connected to the input end of the voltage controlled oscillator; The input end of the data detection control module is connected to the output end of the clock data recovery circuit system. The data detection control module samples the signal to be processed according to the recovered clock signal to obtain first recovered data, and obtains the condition for starting the integration module according to the first recovered data. The data detection control module, the phase detector, the filter and the voltage-controlled oscillator are all installed in the first communication circuit. The data detection control module obtains a training data set from the first communication circuit. The first communication circuit stores the training data set. The first communication circuit is connected to the second communication circuit through an interface protocol. The second communication circuit stores the training data set. The second communication circuit processes the training data set and sends it to the first communication circuit. The training data set sent from the second communication circuit and received by the first communication circuit is the signal to be processed. The data detection control module obtains a condition for starting the integration module based on the first restored data: the first restored data is consistent with the training data set.

2. The clock data recovery circuit system according to claim 1, wherein: The integration module includes: a first integrator, wherein the input end of the first integrator is connected to the output end of the phase detector, and the output end of the first integrator is connected to the second input end of the adder. When the clock data recovery circuit system is started, the data detection control module disables the first integrator, and the data detection control module determines whether the condition for starting the first integrator is met. The condition for starting the first integrator is that the first recovered data is consistent with the training data set, or that the first recovered data is consistent with the second recovered data.

3. The clock data recovery circuit system according to claim 2, wherein: The integration module also includes: a second integrator, the second integrator input end is connected to the phase detector output end, the second integrator output end is connected to the adder third input end, and the second integrator tracking jitter capability is smaller than the tracking jitter capability of the first integrator.

4. The clock data recovery circuit system according to claim 3, wherein: The filter is a ring filter containing a gain block and an integration block.

5. A clock data recovery circuit system, characterized in that: include: Data detection control module, phase detector, filter and voltage controlled oscillator; The first input terminal of the phase detector is used to receive the signal to be processed, and the second input terminal of the phase detector is connected to the output terminal of the voltage controlled oscillator. The output terminal of the voltage controlled oscillator is the output terminal of the clock data recovery circuit system. The output terminal of the clock data recovery circuit system outputs a recovered clock signal. The phase detector is used to output a voltage control signal for controlling the voltage controlled oscillator according to the signal to be processed and the recovered clock signal. The filter includes: a gain module, an integration module and an adder, the input end of the gain module and the input end of the integration module are both connected to the output end of the phase detector, the gain module is used to perform gain processing on the voltage control signal, and the integration module is used to perform integration processing on the voltage control signal; The output end of the gain module is connected to the first input end of the adder, and the output end of the integration module is connected to the second input end of the adder. The adder is used to add the voltage control signal after the gain processing and the voltage control signal after the integration processing to obtain an oscillation control signal; the output end of the adder is connected to the input end of the voltage controlled oscillator; The input end of the data detection control module is connected to the output end of the clock data recovery circuit system. The data detection control module samples the signal to be processed according to the recovered clock signal to obtain first recovered data, and obtains the condition for starting the integration module according to the first recovered data; The steps of the data detection control module starting the integration module according to the first data recovery command are as follows: First, the data detection control module generates a comparison clock signal with a phase difference of a degree from the recovered clock signal, where the value of a ranges from 30 to 90 degrees; Then, the data detection control module uses the comparison clock signal to recover the second recovery data from the signal to be processed; Finally, the data detection control module obtains a condition for starting the integration module according to the first restored data, and the condition for starting the integration module obtained by the data detection control module according to the first restored data is: the first restored data is consistent with the second restored data.

6. The clock data recovery circuit system according to claim 5, wherein: The value of a is 60.

7. A clock recovery operation method, characterized in that: The clock recovery operation method is implemented based on the clock data recovery circuit system according to any one of claims 1 to 6; The clock recovery operation method comprises the following steps: S1, starting the clock data recovery circuit system, while the data detection control module disables the first integrator in the integration module of the filter, and the clock data recovery circuit system performs phase detection and adjustment without the first integrator; S2. The data detection control module samples the signal to be processed according to the recovered clock signal to obtain first recovered data, obtains a condition of the first integrator according to the first recovered data, and determines whether the condition is met. If not, wait; if so, proceed to step S3; S3, the data detection control module starts the first integrator in the filter; S4, the clock data recovery circuit system performs phase detection and adjustment by the first integrator; S5. The clock data recovery circuit system enters a stable tracking state.

8. The clock recovery operation method according to claim 7, characterized in that: In step S1 , the clock data recovery circuit system is started and the second integrator is started at the same time.

9. The clock recovery operation method according to claim 7, characterized in that: In step S1 , the clock data recovery circuit system is started while the second integrator is not started. In step S3 , the first integrator in the filter is started while the second integrator is started.

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