Equipment control device and method, storage medium and electronic equipment

Abstract

The invention discloses an equipment control device and method, a storage medium and electronic equipment, and relates to the technical field of computers, the device comprises a plurality of switch boards, and each switch board comprises a first controller, a first logic device and a plurality of switch chips; the first controller is connected with a first port of the first logic device; a second port of the first logic device is connected with a first port of the switching chip; a third port of the first logic device is connected with the first circuit board; a second port of the switch chip is connected with a plurality of heterogeneous acceleration cards; the first controller is used for controlling a target acceleration card in the heterogeneous acceleration cards, and the target acceleration card and the first controller are connected with the same switching board. Compared with the prior art, the system requirements of a plurality of heterogeneous acceleration cards can be met, the heterogeneous acceleration cards are controlled by utilizing the controllers on the switching boards, a controller on a host does not need to be called for control, the control efficiency of the heterogeneous acceleration cards is improved, and then the performance of the whole machine is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technologies, and in particular, to a device control apparatus, method, storage medium, and electronic device. Background Art

[0002] With the continuous expansion of the scale of data centers, multiple heterogeneous acceleration cards are usually required in a single machine system to improve the system computing power. Heterogeneous acceleration cards usually include multiple different types of processing units for executing different types of computing tasks.

[0003] Currently, related technologies only control heterogeneous acceleration cards through a single controller in the server motherboard. When the number of heterogeneous acceleration cards increases, the control efficiency of the controller for each heterogeneous acceleration card is reduced, affecting the overall performance of the machine. Summary of the Invention

[0004] The present disclosure provides an apparatus, method, storage medium, and electronic device. Its main purpose is to solve the problem that related technologies only control heterogeneous acceleration cards through a single controller in the server motherboard. When the number of heterogeneous acceleration cards increases, the control efficiency of the controller for each heterogeneous acceleration card is reduced, affecting the overall performance of the machine.

[0005] In a first aspect, the present application provides a device control apparatus, including:

[0006] Multiple switching boards, where each switching board includes a first controller, a first logic device, and multiple switching chips;

[0007] The first controller is connected to the first port of the first logic device;

[0008] The second port of the first logic device is connected to the first port of the switching chip;

[0009] The third port of the first logic device is connected to the first circuit board;

[0010] The second port of the switching chip is connected to multiple heterogeneous acceleration cards;

[0011] The first controller is used to control a target acceleration card in the heterogeneous acceleration cards, and the target acceleration card and the first controller are connected to the same switching board.

[0012] In a second aspect, the present application provides a device control method, including:

[0013] Using the first controller to control a target acceleration card in the heterogeneous acceleration cards, and the target acceleration card and the first controller are connected to the same switching board.

[0014] In a third aspect, the present application provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the method of the second aspect is implemented.

[0015] In a fourth aspect, the present application provides an electronic device, including a storage medium, a processor, and a computer program stored on the storage medium and executable on the processor. When the processor executes the computer program, the method of the second aspect is implemented.

[0016] In a fifth aspect, the present application provides a computer program product, on which a computer program is stored. When the computer program is executed by a processor, the method of the second aspect is implemented.

[0017] The device control device, method, storage medium, and electronic device provided by the present disclosure. The device includes a plurality of switching boards, and each switching board includes a first controller, a first logic device, and a plurality of switching chips; the first controller is connected to a first port of the first logic device; a second port of the first logic device is connected to a first port of the switching chip; a third port of the first logic device is connected to a first circuit board; a second port of the switching chip is connected to a plurality of heterogeneous acceleration cards; the first controller is used to control a target acceleration card in the heterogeneous acceleration cards, and the target acceleration card and the first controller are connected to the same switching board. Compared with the current existing technologies, in the present application, a plurality of heterogeneous acceleration cards can be connected to the switching board through corresponding switching chips, and then the device information of the heterogeneous acceleration cards is transmitted to the first controller on the corresponding switching board by using the logic device. By adding switching boards, the number of the first controller and the heterogeneous acceleration cards is increased. The first controller is used to control the target acceleration card on the same switching board, which can meet the system requirements of a plurality of heterogeneous acceleration cards. The controllers on each switching board are used to control the heterogeneous acceleration cards, and there is no need to call the controller on the host for control, which improves the control efficiency of the heterogeneous acceleration cards and further improves the overall performance of the machine.

[0018] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present application, nor is it used to limit the scope of the present application. Other features of the present application will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0020] Figure 1 The structural schematic diagram of a device control device provided by an embodiment of the present application is shown.

[0021] Figure 2 The connection schematic diagram of a switching board provided by an embodiment of the present application is shown;

[0022] Figure 3Shows a schematic connection diagram of a multi-level multiplexing module provided by an embodiment of the present application;

[0023] Figure 4 Shows a schematic connection diagram of a memory provided by an embodiment of the present application;

[0024] Figure 5 Shows a schematic connection diagram of a fan provided by an embodiment of the present application;

[0025] Figure 6 Shows a schematic overall connection diagram provided by an embodiment of the present application;

[0026] Figure 7 Shows a schematic flow diagram of a device control method provided by an embodiment of the present application;

[0027] Figure 8 Shows a schematic diagram of an example provided by an embodiment of the present application;

[0028] Figure 9 Shows a schematic diagram of another example provided by an embodiment of the present application; Detailed implementation manners

[0029] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the protection scope of the present application.

[0030] It should be noted that in the description of the present application, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present application are used to distinguish similar objects, rather than to describe a specific order or sequence.

[0031] In some examples, to meet the requirements of many complex computing scenarios such as artificial intelligence (AI), machine learning, and high-performance computing, new requirements are put forward for the data center architecture. When the single-card performance is limited and the speedup ratio of multi-card parallel computing reaches the limit of the parallel algorithm and the inter-device communication bandwidth, increasing the number of acceleration chips is a direct and effective means to improve the system computing power and training speed. It is necessary to break through the limit on the number of acceleration cards in a server (such as an 8-card AI server), and use multiple acceleration chips to work together to make up for the shortage of computing power of a single acceleration chip, so as to realize a self-controlled AI server. However, after breaking through the number limit, the server also changes greatly. In the current heterogeneous computing acceleration server, usually there is only one baseboard management controller (BMC) in a whole machine system for out-of-band management of the whole machine, which increases the difficulty of whole machine management, reduces the control efficiency of the whole machine acceleration card, and thus affects the performance of the whole machine.

[0032] As a possible implementation, according to the preset ratio of the processor to the heterogeneous acceleration card, when adding heterogeneous acceleration cards, the corresponding number of processors can be installed on the motherboard to obtain the device information of the heterogeneous acceleration cards, which is convenient for control. However, this method increases the production cost of a single-server and occupies the space of the motherboard.

[0033] To solve the technical problem in the related art that when only one controller in the server motherboard is used to control heterogeneous acceleration cards, when the number of heterogeneous acceleration cards increases, the control efficiency of the controller for each heterogeneous acceleration card is reduced, which affects the performance of the whole machine.

[0034] This embodiment provides a device control device, as Figure 1 shown. The device includes a plurality of switching boards 1. The switching board 1 includes a first controller 11, a first logic device 12, and a plurality of switching chips 13. The first controller 11 is connected to the first port of the first logic device 12. The second port of the first logic device 12 is connected to the first port of the switching chip 13. The third port of the first logic device 12 is connected to the first circuit board. The second port of the switching chip 13 is connected to a plurality of heterogeneous acceleration cards. The first controller 11 is used to control the target acceleration card in the heterogeneous acceleration cards, and the target acceleration card and the first controller 11 are connected to the same switching board 1.

[0035] Among them, multiple switch boards 1 (Switch Board, SW Board) can be configured and are at different device levels, which are used to achieve hierarchical arrangement and control of heterogeneous acceleration cards, ensure correct forwarding and efficient communication of network data packets, and realize data communication between different devices; the first controller 11 can include a Baseboard Management Controller (BMC) arranged on each switch board 1, which can be used to monitor the hardware status of the server in real time, including temperature, voltage, fan speed, power status, etc., detect hardware failures or abnormal conditions in a timely manner, and can communicate with server hardware components through the Intelligent Platform Management Interface (IPMI) to receive and execute management commands.

[0036] Correspondingly, the first logic device 12 can be a logic device installed on the switch board 1. The logic device can include, but is not limited to, a Complex Programmable Logic Device (CPLD), a Field-Programmable Gate Array (FPGA), etc., which can be used for system monitoring, power management, clock control, temperature sensing, and fault detection, etc. It can monitor the system status in real time and perform corresponding control and protection to ensure the normal operation of the server. Exemplarily, a CPLD can be used to receive and detect control data, perform line control according to the detection results. When a server failure occurs, the CPLD can detect the cause of the failure and perform emergency processing according to a preset strategy, such as automatically restarting or switching to a backup system to ensure service continuity. Specifically, the switching chip 13 (Switching Chip) can be used to connect multiple heterogeneous acceleration cards to achieve the expansion of heterogeneous acceleration cards. On the same switch board 1, at least one switching chip 13 can be installed and connected to the first logic device 12, receive the control data sent by the first logic device 12, and send corresponding device information to the first controller 11 or the first circuit board through the connected lines. While expanding the heterogeneous acceleration cards, various control methods for the heterogeneous acceleration cards are realized.

[0037] In some embodiments, the first circuit board may include a server motherboard, which can support multiple processors, such as a Central Processing Unit (CPU), and large-capacity memory expansion, providing more Peripheral Component Interconnect Express (PCIe) slots to be suitable for business scenarios such as high load and multitasking; the target acceleration card may include a heterogeneous acceleration card that needs to be controlled by the first controller 11, and is on the same switch board 1 and in the same device layer as the first controller 11. Among them, the heterogeneous acceleration card may include an FPGA acceleration card, a Graphic Processing Unit (GPU) acceleration card, an Application Specific Integrated Circuit (ASIC) acceleration card, etc., and is applied to fields such as artificial intelligence, big data analysis, high-performance computing, and edge computing, providing higher computing performance and energy efficiency ratio.

[0038] Exemplarily, in a single-machine AI server, multiple switch boards 1 can be configured to be connected to the motherboard. The multiple switch boards 1 can be deployed in multiple different device layers to reasonably utilize the space of the server. One first controller 11, one first logic device 12, and multiple switch chips 13 can be arranged on each switch board 1. Exemplarily, one first controller 11, one first logic device 12, and two switch chips 13 can be arranged. The first logic device 12 can be used to connect to the first circuit board, obtain the control data sent by the host, and can also receive the control data sent by the first controller 11, detect the control data, and switch the circuit so that the circuit between the first circuit board or the first controller 11 and the target heterogeneous card is connected.

[0039] Among them, the switch chip 13 can be used to connect to multiple heterogeneous acceleration cards respectively, use the first controller 11 to select the target acceleration card that needs to be controlled, and send the control data to the first logic device 12. Use the first logic device 12 to receive and detect the control data, determine the target acceleration card according to the detection result, and switch the connection circuit so that the first controller 11 is connected to the target acceleration card, and the device information of the target acceleration card can be obtained, realizing the control of the target acceleration card by the first controller 11.

[0040] Specifically, in the same-layer switch board 1, the first controller 11 on the switch board 1 can be used to control the connected heterogeneous acceleration cards, and the target acceleration card can be selected from the multiple heterogeneous acceleration cards connected by the switch chip 13 for control. While increasing the system computing power by adding heterogeneous acceleration cards, the number of first controllers 11 is increased, which is convenient for controlling each heterogeneous acceleration card, reducing the data processing tasks of the controller on the server motherboard, and helping to improve the overall performance of the machine.

[0041] Compared with the current existing technologies, in the present application, multiple heterogeneous acceleration cards can be connected to the switching board 1 through the corresponding switching chips 13, and then the device information of the heterogeneous acceleration cards is transmitted to the first controller 11 on the corresponding switching board 1 by using a logic device. By adding the switching board 1, the number of the first controllers 11 and the heterogeneous acceleration cards is increased. Using the first controller 11 to control the target acceleration cards on the same switching board 1 can meet the system requirements of multiple heterogeneous acceleration cards. Using the controllers on each switching board 1 to control the heterogeneous acceleration cards without calling the controller on the host for control improves the control efficiency of the heterogeneous acceleration cards, thereby improving the overall performance of the machine.

[0042] Optionally, the first logic device 12 may include a first multiplexer; the first multiplexer is used to switch the target connection line between the first logic device 12 and the target acceleration card according to the control data; the first controller 11 is used to obtain the device information of the target acceleration card according to the target connection line.

[0043] Among them, the first multiplexer may be the multiplexer (Multiplexer, MUX) in the first logic device 12, and may be a circuit module, which can select one signal from multiple input signals and transmit it to a single output line, multiplexing the multiple input signals onto one output, thereby reducing the required number of physical connections. It is used to control the connection mode of the circuit according to the detection result of the control data by the first logic device 12, connect the target connection line corresponding to the first controller 11 and the target acceleration card, so that the first controller 11 can use the target connection line to obtain the device information of the target acceleration card, realize the control and management of the target acceleration card, and can use multiple BMCs to realize out-of-band management, and can control the heterogeneous acceleration cards both when the host is not started and in the started state, which is convenient for the debugging personnel to maintain the whole machine and improves the overall management efficiency of the machine.

[0044] In this way, when expanding the heterogeneous acceleration cards, there is no need to add a corresponding processor on the main board. The first multiplexer can be used to switch the target connection line, so that the first controller 11 on the same switching board 1 can control any connected acceleration card, reducing the production cost of the single-server and the space occupied on the main board, and improving the control efficiency of the heterogeneous acceleration cards.

[0045] Optionally, the first circuit board includes a second logic device and a processor; the first port of the second logic device is connected to the first port of the processor; the second port of the second logic device is connected to the first logic device 12; the second logic device is used to determine the target control device for controlling the heterogeneous acceleration card from the processor and the first controller 11 according to the control data.

[0046] Optionally, the first circuit board and the multiple switching boards 1 may be in different device layers; the multiple switching boards 1 may be in different device layers.

[0047] In some embodiments, the first circuit board may be a server motherboard (MB). A second logic device and at least one processor may be configured on the motherboard. Among them, the second logic device may be a logic device installed on the first circuit board, which is used to detect received control data, identify a target control device that needs to be controlled, and control the connection between the second logic device and the target control device. The target control device may be a control device for reading a target acceleration card. For example: a processor on the motherboard, a BMC on the motherboard, a BMC on the switching board 1, etc. In this way, multiple methods can be used to control heterogeneous acceleration cards, which is convenient for the server to perform overall machine management and provides multiple debugging methods, facilitating the staff to perform equipment debugging.

[0048] Optionally, the first logic device 12 further includes a switching interface; the switching interface is connected to the switching chip 13; the switching chip 13 is connected to the heterogeneous acceleration card through a serial bus.

[0049] In some embodiments, a switching interface may be configured in the first logic device 12. For example: a Universal Asynchronous Receiver (UART), which is used to connect to the switching chip 13 in the switching board 1. Correspondingly, logic devices, controllers, etc. on other circuit boards can also be configured with switching interfaces for sending and receiving control data, realizing data interaction with other chips, and obtaining device information of the target acceleration card.

[0050] Optionally, the device further includes a serial bus interface; the serial bus interface is connected to the second logic device; the serial bus interface is used to receive control data and transmit it to the second logic device.

[0051] Exemplarily, the serial bus interface may include a Universal Serial Bus (USB) interface, which is used to receive control data sent externally and send it to the CPLD on the motherboard.

[0052] Exemplarily, such as Figure 2As shown, it can be used for overall machine UART management. The connection relationships among the MB, the Datacenter-ready Secure Control Module (DC-SCM), and two SW boards (SW Board0 and SWBoard1) are shown. Among them, the main board may include CPID, USB interfaces, CPU0, etc.; BMC, CPLD, UART, and at least one switching chip 13 (SW board), such as SW 0 and SW 1, are respectively configured on SW Board0 and SW Board1. The CPLD on each circuit board can be configured with corresponding MUX and UART interfaces for line switching and data transmission. Among them, the MB and the DC-SCM are in the same device layer, and SW Board0, SW Board1, and the MB are in different device layers.

[0053] Specifically, the BMC on the main board has the control right for overall machine management, and the system serial port of the overall machine is also output by the main board CPLD. The BMC serial ports on the two SW boards, the UART of the SW, and the SDB serial ports are all connected to the CPLD. A MUX is set in the CPLD. The CPLD judges by detecting the input characters to determine the device to which the MUX should be switched. At the same time, the BMC can switch the MUX switch by setting the CPLD register. The UART on the SW board can be connected to the UART SW of the main board CPLD. The UART MUX of the main board is used to switch the UARTs of the two SW boards, the UART of the DC-SCM, and the CPU UART, and finally switch the output to the Micro USB. During actual operation, the operator inputs specific characters corresponding to control data through the Micro USB. The MBCPLD can be used to detect the characters and switch the different data flow directions of the UART. When switching to CPU0, the serial port will be directly connected to CPU0 and display the print information of CPU0; when switching to SW Board0, the CPLD on SW Board0 re-detects the input characters, switches the MUX after character matching, and switches to the BMC serial port of SW Board0 or the UART of SW0 or the StorageDevice Block (SDB) serial port. SW Board1 also adopts the same control method. In this way, the operator can directly control the CPU, the BMC on each circuit board, and each SW through the MUX switch, which is convenient for maintenance and improves the maintenance efficiency.

[0054] Optionally, the first circuit board further includes a memory and a multi-level multiplexing module; the memory is connected to the first port of the multi-level multiplexing module; the second port of the multi-level multiplexing module is connected to the second port of the processor; the multi-level multiplexing module is used to switch the connection line between the processor and the target memory.

[0055] In some embodiments, the memory may include multiple sets of Dual Inline Memory Modules (DIMMs). A DIMM is a form of computer memory module that can be connected to the processor and multi-level multiplexing module on the motherboard. For example, 8 memory groups can be configured, each memory group includes 3 DIMMs, and they are marked with memory identifiers; the target memory can be the memory to be accessed; the multi-level multiplexing module may include a first-level multiplexer, a second-level multiplexer, and a third-level multiplexer. Among them, the first-level multiplexer can be used to switch the memories corresponding to multiple processors, the second-level multiplexer can be used to switch the memories in each memory group, and the third-level multiplexer can be used to switch the processor on the motherboard and the controller in the DC-SCM. In this way, the memory can be accessed by the motherboard processor or the controller in the DC-SCM, meeting the requirement that the BMC needs a separate channel to access the memory, optimizing the access circuit between the controller and multiple sets of memories, and improving the access efficiency.

[0056] Optionally, the device further includes a second circuit board, and the second circuit board includes a third logic device and a second controller; the first port of the third logic device is connected to the second port of the multi-level multiplexing module; the second port of the third logic device is connected to the third port of the processor; the third port of the third logic device is connected to the first port of the second controller; the third logic device is configured to receive control data sent by the processor or the second controller, and determine the target memory according to the control data; the multi-level multiplexing module is configured to switch the connection line between the second controller and the target memory; the first circuit board and the second circuit board can be on the same device layer.

[0057] Among them, the second circuit board can be another circuit board on the same device layer as the first circuit board, such as the circuit board corresponding to the DC-SCM, which is used for overall machine management; the third logic device can be a logic device installed on the second circuit board; the second controller can be a controller installed on the second circuit board. Exemplarily, CPLD, BMC, MUX, etc. can be configured in the DC-SCM.

[0058] Exemplarily, such as Figure 3As shown, the CPU can support 4 groups of Serial Presence Detect (SPD)_Improved Inter-Integrated Circuit (I3C). The I3C SPD signals are respectively sent by the CPU on the motherboard and the BMC on the SCM card, and are connected to the DIMM through the MUX. The switching of the MUX needs to be controlled by the CPLD, and the CPLD judges different MUXs by receiving the Inter-Integrated Circuit (I2C) commands of the CPU. Through the switching combination of the MUX, both the CPU and the BMC can send commands to the DIMM separately. After the I3C signal of the BMC passes through the connector, it passes through the first-level MUX, which switches the DIMMs of CPU0 and CPU1, and then passes through the second-level MUX, which is used to switch the memory in the DIMM group to determine the target memory to be accessed from a group of memories. The three DIMMs can be divided into a group, and according to the corresponding memory identifiers, they can be divided into: A-C, D-F, G-H, J-L. Then it passes through the third-level MUX, which switches the use of the BMC and the CPU, and finally reaches 3 DIMMs. These three DIMMs have unique addresses and can be respectively marked as A0, A4, and A8. Each of CPU0 and CPU1 uses 4 I3C ports Port, and through the third-level MUX, each I3C Port monitors the DIMM devices of 3 channels.

[0059] Optionally, the first circuit board further includes a first memory and a second multiplexer, and the second circuit board further includes a second memory and a third multiplexer; the first port of the first memory is connected to the third port of the processor; the second port of the first memory is connected to the first port of the second controller through the second multiplexer; the first port of the second memory is connected to the second port of the second controller through the third multiplexer; the second multiplexer and the third multiplexer are used to switch the target memory connected to the second controller; the first memory and the second memory are used to store the device configuration data corresponding to the second controller.

[0060] Among them, the first memory can be an accessor configured for the first circuit board, such as: Flash memory, etc., the second multiplexer can be a multiplexer configured for the first circuit board, the second memory can be an accessor configured for the second circuit board, and the third multiplexer can be a multiplexer configured for the second circuit board. Among them, the BIOS Flash can be placed on the motherboard and the DC-SCM for redundant design to provide multiple power-on methods for the BMC. Exemplarily, such as Figure 4As shown, the SPI topology design on the DC-SCM and the SPI topology design on the MB can be carried out. The DC-SCM and the MB are connected by a gold finger. In the normal initial version verification case, after the CPU is powered on, it needs to read the BIOS image in the Flash. After the SPI signal of the CPU passes through the level conversion chip, it passes through two MUXs and reaches two Flashs at the same time. The actually used Flash is determined by the switch of the MUX. These two Flashs are the main Flash and the standby Flash. For example, Flash1 and Flash2 in the main board, Flash3 and Flash4 in the DC-SCM. The selection of the two Flashs is realized by the BMC writing the CPLD register through I2C, and the CPLD controls the switches of the MUXs (such as MUX1, MUX2, MUX3, MUX4). When the BMC needs to upgrade the Flash, the SPI signal of the BMC passes through the gold finger and then passes through the SPI MUX switching with the CPU and reaches the two Flashs. The upgraded Flash can also be determined by the MUX. In this way, when powered on, the BMC can determine the target memory from the memories in the main board and the DC-SCM, and then read the corresponding device configuration data from the target memory to realize the redundant design of the memory and improve the system stability.

[0061] In some embodiments, after the server is mass-produced, the Basic Input / Output System (BIOS) function can be switched to the two Flashs on the DC-SCM. The SPI signal of the CPU directly reaches the gold finger on the DC-SCM through the Trusted Platform Module (TPM) and the CN resistor. On the DC-SCM, it passes through the gold finger and reaches the two MUXs on the DC-SCM. After passing through the MXU switching, it reaches the two Flashs on the DC-SCM. The actually used Flash is determined by the MUX on the DC-SCM. When the BMC needs to upgrade the Flash, the SPI signal of the BMC does not pass through the gold finger, but passes through the CN resistor and then passes through the SPI MUX switching with the CPU and reaches the two Flashs on the DC-SCM. The upgraded Flash can also be determined by the MUX.

[0062] Optionally, the device further includes a fourth logic device; the first port of the fourth logic device is connected to the third port of the second logic device; the second port of the fourth logic device is connected to the third port of the second controller; the third port of the fourth logic device is connected to the fan; the fourth logic device is used to control the fan according to the control signal of the second controller, and the fan is used to dissipate heat from the first circuit board and the multiple switching boards 1. The fan can be at different device layers.

[0063] In some embodiments, the fourth logic device may be the logic device corresponding to the fan board, and multiple fans can be configured to dissipate heat for multiple switching boards 1 and the main board, which are respectively located in different device layers to ensure system stability.

[0064] Exemplarily, as Figure 5 shown, the whole machine may be provided with a fan wall, and 4 fan boards are configured. The CPLD on the fan board will detect the state of the input hardware timer (Watchdog Timer, WDT) signal. When the WDT signal is normal, the pulse width modulation (Pulse Width Modulation, PWM) output to the fan is the PWM output by the BMC. When the WDT is abnormal, the CPLD of the fan board will switch the MUX of the PWM and output a fixed-value PWM. In this way, the fan heat dissipation strategy can be controlled by the BMC, and can also be regulated by the CPLD of the fan board to meet various fan regulation requirements.

[0065] As a possible implementation manner, as Figure 6 shown, the overall structural schematic diagram of the device is shown. At least one processor (such as CPU0, CPU1) and complex programmable logic devices can be arranged on the server main board. The processors can be respectively connected to multiple groups of DIMMs. Among them, each CPU can support 4-way xHCL signals, the bandwidth can be X16, and the xHCL rate can support up to 32GT / s at most. The interconnection control bus between CPUs can adopt the CFIP bus, and its transmission rate is 6.4Gb / s. Through the xHCL and CFIP buses, the two CPUs can communicate with each other, so as to achieve the data transmission rate between the processors. Among them, xHCL is a group of signals related to hardware compatibility supported by the CPU. Correspondingly, the MB CPLD can communicate with the BMC on the DC-SCM through the two-way two-wire synchronous serial bus (Inter-Integrated Circuit, IIC) and the WDT signal. The MB CPLD and the BMC on the DC-SCM can also communicate with the CPLD of the fan backplane (Fan Backplane, FAN BP). Among them, the IIC bus is suitable for short-distance and low-speed data transmission, and the hardware timer can be used to detect software system failures and automatically perform recovery operations.

[0066] Specifically, the CPLD on the DC-SCM communicates with the motherboard CPLD and the SW board through UART and SDB. The CPU communicates with the Flash memory, BMC, and TPM through a Serial Peripheral Interface (SPI) link. Exemplarily, due to the motherboard size and CPU size requirements, the memory configuration can only adopt the form of 1DPC memory. Each of the 749x CPUs uses 12 memory modules to fill 12 memory channels, totaling 24 DDR5 memory modules, with a maximum supported memory frequency of 4800 GT / s; each of the 746x / 748x CPUs uses 8 memory modules to fill 8 memory channels, totaling 16 DDR5 memory modules, with a maximum supported memory frequency of 5200 GT / s.

[0067] In this way, it is possible to manage the AI server at the hardware level, integrate multiple heterogeneous acceleration cards within a single machine system, increase the number of integrated chips in a single machine, and enable better parallelization of models and data in a multi-card server cluster. It can be applied to business scenarios such as large models, improving the computing power of a single machine while still facilitating the management of the entire machine, meeting the management requirements of the high computing power of artificial intelligence servers, and improving the overall performance of the system.

[0068] Compared with the current existing technologies, in this embodiment, when expanding heterogeneous acceleration cards, there is no need to add corresponding processors on the motherboard. The first multiplexer can be used to switch the target connection line, enabling the first controller on the same switching board 1 to control any connected acceleration card, reducing the production cost of a single machine server, reducing the space occupied on the motherboard, improving the control efficiency of heterogeneous acceleration cards, and using a multi-level multiplexing module to switch the processors on the motherboard and the controller in the DC-SCM, so that the memory can be accessed by the motherboard processor or the controller in the DC-SCM, meeting the requirement that the BMC needs a separate channel to access the memory, optimizing the access lines between the controller and multiple groups of memory, and improving the access efficiency.

[0069] This embodiment provides a device control method, as Figure 7 shown, the method includes the following steps:

[0070] Step 201: Use the first controller to control the target acceleration card in the heterogeneous acceleration card. The target acceleration card and the first controller are connected to the same switching board.

[0071] Among them, the switching board includes a first controller, a first logic device, and multiple switching chips. The switching chips are used to connect multiple heterogeneous acceleration cards. The first logic device is used to obtain and detect control data, determine the target acceleration card to be controlled by the first controller, switch the connection line between the target acceleration card and the first controller, and then use the first controller to control the target acceleration card, meeting the system requirements of multiple heterogeneous acceleration cards, enabling the controllers on each switching board to control the heterogeneous acceleration cards, without the need to call the controller on the host for control, improving the control efficiency of the heterogeneous acceleration cards, and thus improving the overall machine performance.

[0072] Optionally, the method of this embodiment may further include: hierarchically controlling the fans according to the heat dissipation strategy identifier, where the fans can be used to dissipate heat from the main board and the switching board.

[0073] Exemplarily, as Figure 8 shown, in terms of the heat dissipation strategy, it supports loading multiple heat dissipation strategies and flexibly adjusting them in the way of IPMI command configuration, using the IPMI service to meet the requirements of different application scenarios. According to the design requirements, the whole machine needs to support multiple heat dissipation strategies such as air cooling and liquid cooling. Specifically, one image of the BMC supports multiple heat dissipation strategies such as air cooling and liquid cooling at the same time. The heat dissipation strategy identifier is configured through IPMI commands and stored in the main board EEPROM, without loss of power. During the BMC startup phase, the heat dissipation strategy identifier is read, and the corresponding heat dissipation strategy configuration file is loaded according to the identifier for heat dissipation regulation. For example, configuration file 1 can be used to execute air cooling strategy 1, configuration file 2 can be used to execute air cooling strategy 2, and configuration file n can be used to execute liquid leakage detection and cold plate heat dissipation strategy.

[0074] Exemplarily, as Figure 9 shown, the heat dissipation regulation can adopt hierarchical control. The BMC and the fan board CPLD are used for fan regulation. 15 8086 fans are shared for the heat dissipation of the two-layer GPU units on the chassis, and 8 4056 fans are used for the heat dissipation of the middle-layer computing units. When the BMC is working properly, the BMC completes the status monitoring of each component of the system, the reading of the sensor temperature, the acquisition of the fan speed RPM, etc. through the protocol, and accordingly completes the temperature reading value judgment, regulation logic operation, alarm log generation, etc.; and sends the relevant fan speed duty to the fan board CPLD, and the fan board CPLD controls the fan speed. When the BMC is abnormal, after the fan board CPLD obtains the abnormal status information of the BMC, the fan board CPLD takes over the fan control management. In this way, multiple control methods for the fans are realized, the overall machine management function is improved, and it helps to ensure the stability of the system.

[0075] It should be noted that for the other corresponding descriptions of each functional unit involved in the device control device provided in this embodiment, reference can be made to the corresponding descriptions in Figure 1 and will not be elaborated here.

[0076] Based on the above method as Figure 7 shown, correspondingly, this embodiment also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the method as Figure 7 shown above is implemented.

[0077] Based on the above method as Figure 7 shown, correspondingly, this embodiment also provides a computer program product, on which a computer program is stored. When the computer program is executed by a processor, the method as Figure 7 shown above is implemented.

[0078] Based on such an understanding, the technical solution of this application can be embodied in the form of a software product. The software product can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.), and includes several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods of various implementation scenarios of this application.

[0079] Based on the above method as Figure 7 shown, to achieve the above object, this embodiment of the application also provides an electronic device, such as a personal computer or a server. The device includes a storage medium and a processor; the storage medium is used to store a computer program; the processor is used to execute the computer program to implement the method as Figure 7 shown above.

[0080] In some embodiments, the above-mentioned physical device may further include a user interface, a network interface, a camera, a radio frequency (RF) circuit, sensors, an audio circuit, a WI-FI module, and so on. The user interface may include a display screen (Display), an input unit such as a keyboard (Keyboard), etc. Optionally, the user interface may further include a USB interface, a card reader interface, etc. The network interface may include a standard wired interface, a wireless interface (such as a WI-FI interface), etc. in some embodiments.

[0081] Those skilled in the art can understand that the above-mentioned physical device structure provided in this embodiment does not limit the physical device, and it may include more or fewer components, or combine some components, or have different component arrangements.

[0082] The storage medium may further include an operating system and a network communication module. The operating system is a program for managing the hardware and software resources of the above-mentioned physical device, and supports the operation of information processing programs and other software and / or programs. The network communication module is used to implement communication between components inside the storage medium, and communication between other hardware and software in the information processing physical device.

[0083] Through the description of the above embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus a necessary general hardware platform, or can be implemented by hardware. By applying the solution of this embodiment, compared with the current existing technologies, when expanding heterogeneous acceleration cards in this embodiment, there is no need to add a corresponding processor on the motherboard, and the first multiplexer can be used to switch the target connection line, so that the first controller on the same switching board can control any acceleration card connected, reducing the production cost of the single-server and also reducing the space occupied on the motherboard, improving the control efficiency of the heterogeneous acceleration card, and the multi-level multiplexing module can be used to switch the processor on the motherboard and the controller in the DC-SCM, so that the memory can be accessed by the motherboard processor or the controller in the DC-SCM, meeting the requirement that the BMC needs a separate channel to access the memory, optimizing the access lines between the controller and multiple groups of memory, improving the access efficiency, and also being able to implement multiple control methods for the fan, improving the overall machine management function, which helps to ensure the stability of the system.

[0084] It should be noted that in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of additional identical elements in the process, method, article or device including the element.

[0085] The above are only specific embodiments of this application, enabling those skilled in the art to understand or implement this application. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application will not be limited to these embodiments herein, but will conform to the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A device control apparatus, characterized in that, Comprising: A plurality of switching boards, the switching board including a first controller, a first logic device, and a plurality of switching chips; The first controller is connected to a first port of the first logic device; A second port of the first logic device is connected to a first port of the switching chip; A third port of the first logic device is connected to a first circuit board; A second port of the switching chip is connected to a plurality of heterogeneous acceleration cards; The first controller is used to control a target acceleration card in the heterogeneous acceleration cards, and the target acceleration card and the first controller are connected to the same switching board.

2. The device according to claim 1, characterized in that The first logic device includes a first multiplexer; The first multiplexer is used to switch a target connection line between the first logic device and the target acceleration card according to control data; The first controller is used to obtain device information of the target acceleration card according to the target connection line.

3. The device according to claim 2, characterized in that, The first circuit board includes a second logic device and a processor; A first port of the second logic device is connected to a first port of the processor; A second port of the second logic device is connected to the first logic device; The second logic device is used to determine a target control device for controlling the heterogeneous acceleration card from the processor and the first controller according to the control data.

4. The device according to claim 3, characterized in that, The first circuit board further includes a memory and a multi-stage multiplexing module; The memory is connected to a first port of the multi-stage multiplexing module; A second port of the multi-stage multiplexing module is connected to a second port of the processor; The multi-stage multiplexing module is used to switch a connection line between the processor and a target memory.

5. The device according to claim 4, characterized in that The device further includes a second circuit board, the second circuit board including a third logic device and a second controller; A first port of the third logic device is connected to a second port of the multi-stage multiplexing module; A second port of the third logic device is connected to a third port of the processor; A third port of the third logic device is connected to a first port of the second controller; The third logic device is used to receive control data sent by the processor or the second controller, and determine the target memory according to the control data; The multi-stage multiplexing module is used to switch a connection line between the second controller and the target memory.

6. The device according to claim 5, characterized in that The first circuit board further includes a first memory and a second multiplexer, and the second circuit board further includes a second memory and a third multiplexer; A first port of the first memory is connected to a third port of the processor; A second port of the first memory is connected to a first port of the second controller through the second multiplexer; A first port of the second memory is connected to a second port of the second controller through the third multiplexer; The second multiplexer and the third multiplexer are used to switch the target memory connected to the second controller; The first memory and the second memory are used to store device configuration data corresponding to the second controller.

7. The device according to claim 5, characterized in that, The device further includes a fourth logic device; A first port of the fourth logic device is connected to a third port of the second logic device; A second port of the fourth logic device is connected to a third port of the second controller; A third port of the fourth logic device is connected to a fan; The fourth logic device is configured to control the fan according to the control signal of the second controller, and the fan is used to dissipate heat from the first circuit board and the plurality of switching boards.

8. The device according to claim 7, wherein The first circuit board and the second circuit board are on the same device layer; The first circuit board and the plurality of switching boards are on different device layers; The plurality of switching boards are on different device layers; The fan is on a different device layer.

9. The device according to claim 3, characterized in that, The device further includes a serial bus interface; The serial bus interface is connected to the second logic device; the serial bus interface is configured to receive control data and transmit it to the second logic device.

10. The device according to claim 1, characterized in that, The first logic device further includes a switching interface; The switching interface is connected to the switching chip; The switching chip is connected to the heterogeneous acceleration card through a serial bus.

Images