Circuit for solving output overshoot during LDO (Low Dropout Regulator) load jump

Abstract

The invention relates to the technical field of electronics, in particular to a circuit for solving output overshoot during LDO load hopping. The problems that in the prior art, a power supply of an MCU digital kernel part is unstable, and digital logic is wrong are solved. The circuit comprises a gate driving module, a gate equivalent or compensation capacitor, an output driving power tube, a feedback network and an MCU digital kernel, and further comprises an LDO output sampling module, an upshoot / undershoot detection module, a timing module and a voltage charge adjustment module which are connected in sequence. The input end of the LDO output sampling module is connected with the drain electrode of the output driving power tube; the output end of the voltage charge adjusting module is connected with the grid electrode of the output driving power tube. According to the invention, the cost is low, the control is easy, the LDO power tube gate drive is effectively controlled, and the pre-control regulation is carried out before the LDO loop response takes effect, so that the overshoot of the output voltage of the LDO is controlled, and the relative stability of the digital kernel power supply is ensured.

Description

Technical Field

[0001] The invention relates to the field of electronic technology, and in particular to a circuit for solving the problem of output overshoot when an LDO load jumps. Background Art

[0002] As the system of MCU digital-analog hybrid chips becomes more and more complex, performance improves, and resource requirements increase, its internal digital part works in the low-voltage domain, such as 1.2V, 1.5V, etc., while its IO, AD and other peripherals generally work in the high-voltage domain, such as 5V, 3.3V. The digital core power supply is indispensable, and the power supply requirements for its internal digital core part also increase accordingly. Usually, MCU will have applications such as sleep and wake-up, enter sleep after wake-up, and quickly turn on or off internal functional modules. For example, the above scenarios reflect the requirements of the digital core power supply, that is, the LDO circuit that provides the digital core power supply needs to be sufficiently stable when the load current changes sharply; for traditional off-chip LDO, when the LDO load jump increases, the LDO voltage is pulled down to nearly 1.25V. For the typical output 1.5V LDO, it has exceeded 10% drop, which can easily cause digital logic confusion or reset. The main reason for this problem is that the LDO loop bandwidth is limited. When the load changes suddenly, the output drive power tube M1 has no time to respond. The details are as follows: When the drive is small, according to the principle of MOS devices: It can be seen that the Vgs of the output driving power tube, that is, GM1-LDO_OUT, is relatively small. When the load suddenly increases, the gate voltage Vgs of the output driving power tube decreases sharply, and the ability to respond to the output current also becomes weaker, which eventually causes the output LDO_OUT to decrease. As the LDO loop gradually responds, the G output driving power tube will be adjusted to become higher, and finally the LDO can provide the desired drive to the load, and the LDO output returns to normal; a stable power supply is particularly important, which can adapt to the requirements of various working modes of the digital core, because the digital core works in high-speed clock mode, and its load changes are often very drastic, and the working current will reach the transient change of us or even ns level. In order to avoid the disorder of the core digital logic and cause the MCU system to work abnormally, some existing technologies use LDO external large capacitors, and the digital core DIGIT_CORE can extract charge from the external capacitor CLE when the power consumption suddenly changes, and the LDO output voltage LDO_OUT can remain relatively stable, which increases the cost to a certain extent; and now in some designs that pursue the ultimate in cost and performance, it is generally necessary to remove the external capacitor to reduce the cost, but the LDO without external capacitor is affected by its own loop bandwidth. When working in a clock system of tens or hundreds of MHz, it is often difficult to meet the needs when facing ns~us level load jumps. By performing more complex control on the digital logic part to avoid the situation where the core working current changes sharply, the design complexity is increased and the use of some parts is restricted.

[0003] There is an urgent need for a new circuit to solve the above problems and address output overshoot issues. Summary of the Invention

[0004] The present invention provides a circuit for solving output overshoot when the LDO load jumps, which solves the problems of unstable power supply and digital logic errors in the MCU digital core part during different mode switches, different function startups and shutdowns in the prior art.

[0005] The technical solution of the present invention is implemented as follows: A circuit for solving output overshoot when the LDO load jumps includes a gate driving module, a gate equivalent or compensating capacitor, an output driving power transistor, a feedback network, and an MCU digital core. The output end of the gate driving module, the gate equivalent or compensating capacitor, and the gate of the output driving power transistor are sequentially connected. The drain of the output driving power transistor is connected to the MCU digital core. The feedback network is respectively connected to the input end of the gate driving module and the drain of the output driving power transistor. It also includes an LDO output sampling module, an overshoot / undershoot detection module, a timing module, and a voltage charge adjustment module connected in sequence. The input end of the LDO output sampling module is connected to the drain of the output driving power transistor. The output end of the voltage charge adjustment module is connected to the gate of the output driving power transistor.

[0006] In a further technical solution, the overshoot / undershoot detection module includes an overshoot determination unit for determining whether the output voltage has an overshoot; and a degree determination unit for determining the degree of overshoot. The overshoot determination unit is connected to the degree determination unit. The overshoot determination unit can set a threshold value, and when it exceeds or is lower than the set threshold value, it determines an overshoot or an undershoot. The degree determination unit determines a mild overshoot, a severe overshoot, a mild undershoot, or a severe undershoot through threshold setting, and outputs the detection result to the timing module.

[0007] In a further technical solution, the timing module can be a system high-speed clock, an RC delay circuit, or takes the LDO mode switching signal Mode as an input, and the timing module performs timing control.

[0008] In a further technical solution, the voltage charge adjustment module includes a method adjustment unit for pre-controlling the gate signal of the driving transistor and a control quantity adjustment unit. The method adjustment unit includes:

[0009] (1) Setting a voltage value for the gate of the output driving power transistor;

[0010] (2) Pre-charging the gate of the output driving power transistor with charge.

[0011] In a preferred technical solution, the voltage value input parameter for setting the voltage value of the gate of the output driving power transistor is specifically based on the output result of the degree determination unit of the overshoot / undershoot detection module.

[0012] Further technical solution, the gate pre-charge charge for the output driving power transistor is specifically as follows:

[0013] A. When the load changes from light load to heavy load: when it is light load, the gate of the output driving power transistor is A, when it is heavy load, the gate of the output driving power transistor is B, and the equivalent and compensation capacitance of the gate of the output driving power transistor is Cc;

[0014] It can be calculated that the pre-charge charge required is Q = CV = Cc * (GB - GA), and Q = IT, where T is the timing data of the previous-stage timing module. Furthermore, the charging current I = Q / T = CV / T = Cc * (GB - GA) / T, the charging current; the input parameter set according to the output result of the degree determination unit of the above / undershoot detection module;

[0015] B. When the load changes from heavy load to light load: when it is heavy load, the gate of the output driving power transistor is C, when it is light load, the gate of the output driving power transistor is D, and the equivalent and compensation capacitance of the gate of the output driving power transistor is Cc;

[0016] It can be calculated that the pre-discharge charge required is Q = CV = Cc * (GC - GD). Similarly, Q = IT, where T is the timing data of the previous-stage timing module. Furthermore, the discharge current I = Q / T = CV / T = Cc * (GC - GD) / T, the input parameter set according to the output result of the degree determination unit of the above / undershoot detection module.

[0017] A circuit for solving the output overshoot when the LDO load jumps disclosed by the present invention has the following beneficial effects:

[0018] 1. Low cost and easy to control, making the power supply of the MCU digital core part stable when switching between different modes and turning on and off different functions, avoiding digital logic errors;

[0019] 2. When the power consumption of the digital core changes suddenly, when the LDO overshoot causes overshoot or undershoot, the present invention quickly detects the drain voltage information through the LDO output sampling module, quickly feeds the detection result back to the above / undershoot detection module. After evaluating the overshoot situation and severity, the gate of the output driving power transistor is controlled through the timing module and the voltage charge adjustment mode, achieving effective control of the gate drive of the LDO power transistor, pre-controlling and adjusting before the LDO loop response takes effect, providing sufficient driving ability when the load is large, and controlling the problem of LDO output voltage overshoot when the load is small, ensuring the relative stability of the power supply of the digital core;

[0020] 3. The present invention reduces the external capacitance overhead and reduces the control complexity of the digital part during mode switching. Description of the Drawings

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0022] Figure 1 : Circuit diagram of an LDO architecture with a capacitorless CLE using an NMOS driver transistor as an example;

[0023] Figure 2 : Circuit diagram of the LDO architecture of the present invention using an NMOS driver transistor as an example;

[0024] Figure 3 : Schematic diagram of the up / down rush detection module circuit in the present invention;

[0025] Figure 4 : Schematic diagram of the circuit for setting the voltage value at the gate of the output driving power transistor;

[0026] Figure 5 : Schematic diagram of the circuit for pre-charging the gate of the output driving power transistor;

[0027] Figure 6 : Schematic diagram of the LDO load jump output response (overshoot) waveform;

[0028] Figure 7 : Schematic diagram of the LDO load jump output response (undershoot) waveform. Detailed implementation manners

[0029] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention. Detailed implementation manner one

[0031] Combined with Figure 1 the circuit diagram of the LDO architecture with a capacitorless CLE using an NMOS driver transistor as an example and Figure 2Taking the NMOS drive transistor as an example, as shown in the circuit diagram of the LDO architecture of the present invention, the circuit for solving the output overshoot when the LDO load jumps in this embodiment includes a gate drive module (Driver), a gate equivalent or compensation capacitor (Cc), an output drive power transistor (M1), a feedback network (Feed Back), and an MCU digital core (DIGIT_CORE). The output end of the gate drive module, the gate equivalent or compensation capacitor, and the gate of the output drive power transistor are sequentially connected, and the drain of the output drive power transistor is connected to the MCU digital core; the feedback network is respectively connected to the input end of the gate drive module and the drain of the output drive power transistor. In the original LDO architecture without an external capacitor, a feedback execution loop composed of an LDO output sampling module (Sample), an overshoot / undershoot detection module (OUD), a timing module (Timer), and a voltage / charge adjustment module (V / Q Regulator) connected in sequence is added; the input end of the LDO output sampling module is connected to the drain of the output drive power transistor; the output end of the voltage / charge adjustment module is connected to the gate of the output drive power transistor. Pre-control adjustment is performed before the LDO loop response takes effect to effectively control the gate drive of the LDO power transistor, provide sufficient drive capability when the load is large, and control the overshoot of the LDO output voltage when the load is small; reduce the external capacitor cost and the control complexity of the digital part during mode switching. Specific Embodiment 2

[0033] Based on the above embodiment, as Figure 3 As shown in the circuit schematic diagram of the overshoot / undershoot detection module in the present invention, the overshoot is judged by the overshoot / undershoot detection module, and the severity of the overshoot is judged, including an overshoot judgment unit for judging whether the output voltage has an overshoot; a severity judgment unit for judging the degree of overshoot; the overshoot judgment unit is connected to the severity judgment unit; by setting a threshold for the overshoot judgment unit, when it exceeds or is lower than the set threshold, an overshoot or undershoot is judged; by setting a threshold for the severity judgment unit, a mild overshoot, a severe overshoot, a mild undershoot, and a severe undershoot are judged; and the detection result is output to the timing module; for example, for an LDO with a typical output of 1.5V, it can be set that an overshoot occurs when it exceeds 1.6V and an undershoot occurs when it is lower than 1.4V; it can also be set that a mild overshoot occurs when it exceeds 1.58V, a severe overshoot occurs when it exceeds 1.61V, a mild undershoot occurs when it is lower than 1.42V, and a severe undershoot occurs when it is lower than 1.39V, and the detection result is output to the timing module.

[0034] After feeding back the overshoot information to the timing module, timing control is performed by using the system high-speed clock, the RC delay circuit, or the LDO mode switching signal Mode as the input; the purpose is to pre-control the gate signal of the driving transistor before the LDO loop response arrives; and the timing module is to set the length of time that needs to be pre-controlled. If the time is too short, the effect of preventing the LDO output from undershooting and overshooting cannot be achieved, and if it is too long, it will affect the normal loop response of the LDO. By judging the overshoot situation and correspondingly adjusting the pre-control time through the clock module according to the judgment situation, precise control of the LDO output voltage overshoot is achieved. Specific Embodiment 3

[0036] Based on the above embodiment, the method and the adjustment of the control amount for pre-controlling the gate signal of the driving transistor are carried out through the voltage and charge adjustment module;

[0037] (1) As Figure 4 As shown in the circuit schematic diagram for setting the voltage value at the gate of the output driving power transistor, the voltage value is set at the gate of the output driving power transistor to make the gate voltage Vgs of the output driving power transistor meet the requirements of the current MCU digital core for the output driving of the output driving power transistor in advance;

[0038] The input parameters of the voltage value are determined according to the output result of the degree determination unit of the up / down overshoot detection module; when the LDO is in a mode or load change, when the LDO output voltage overshoot is within the allowable value, there will be a corresponding gate voltage value for the power transistor, and this voltage value depends on the actual process device parameters and the load change requirements in the actual case. This voltage value can be used as the initial value for setting the gate voltage. After the initial value is set, mode or load switching verification and confirmation are carried out, and gradual adjustment is made until the LDO output overshoot meets the acceptable value. The working principle of this method is that when the load changes from light load to heavy load, the output driving power transistor needs to increase, and a larger gate voltage Vgs is provided to make the driving current of the output driving power transistor increase to prevent undershoot; when the load changes from heavy load to light load, the output driving power transistor needs to decrease, and a smaller gate voltage GVgs is provided to make the driving current of the output driving power transistor decrease to prevent overshoot.

[0039] (2) As Figure 5 As shown in the circuit schematic diagram for pre-charging the gate of the output driving power transistor, the gate of the output driving power transistor is pre-charged, and charging and discharging are provided by Charge and Discharge. Specifically:

[0040] A. When the load changes from light load to heavy load: When it is light load, the gate of the output driving power transistor is A, and when it is heavy load, the gate of the output driving power transistor is B. The equivalent and compensated capacitance of the gate of the output driving power transistor is Cc;

[0041] It can be calculated that the pre-charge charge required is Q = CV = Cc*(GB - GA), and Q = IT, where T is the timing data of the previous-stage timing module. Furthermore, the charging current I = Q / T = CV / T = Cc*(GB - GA) / T can be obtained. The charging current can be flexibly set according to the overshoot situation; it is the input parameter set according to the output result of the degree determination unit of the above / undershoot detection module; such as Figure 6 From the schematic diagram of the LDO load jump output response (undershoot) waveform, it can be seen that the present invention effectively solves the problem of load jump from light load to heavy load, and the LDO output voltage is stable. According to the charge conservation formula, the pre-charge charge value is initially calculated and substituted into the simulation verification. Taking the output driving power transistor as an NMOS and the downward overshoot scenario as an example, if it is found through verification after the initial calculation of the charge setting that the downward overshoot has not reached the expected value, it means that additional pre-charge charge is needed. At this time, the pre-charge charge is adjusted until the downward overshoot meets the expected value. A similar process can be used for adjustment in other PMOS driving or upward overshoot cases.

[0042] B. When the load changes from heavy load to light load: When it is heavy load, the gate of the output driving power transistor is C; when it is light load, the gate of the output driving power transistor is C, and the equivalent and compensation capacitance of the gate of the output driving power transistor is Cc;

[0043] It can be calculated that the pre-discharge charge required is Q = CV = Cc*(GC - GD). Similarly, Q = IT, where T is the timing data of the previous-stage timing module. Furthermore, the discharge current I = Q / T = CV / T = Cc*(GC - GD) / T can be obtained. The discharge current can be flexibly set according to the overshoot situation; it is the input parameter set according to the output result of the degree determination unit of the above / undershoot detection module; such as Figure 7 From the schematic diagram of the LDO load jump output response (overshoot) waveform, it can be seen that the present invention effectively solves the problem of load jump from heavy load to light load, and the LDO output voltage is stable.

[0044] By setting the gate voltage value of the output driving power transistor to provide a smaller or smaller gate voltage GVgs, the driving current of the output driving power transistor can be made smaller or larger, preventing overshoot or undershoot; pre-charging the gate of the output driving power transistor to achieve precise control of the charging or discharging current, with flexible setting and high control accuracy.

[0045] Of course, without departing from the spirit and essence of the present invention, those skilled in the art should be able to make various corresponding changes and deformations according to the present invention, but these corresponding changes and deformations should all fall within the protection scope of the appended claims of the present invention.

Claims

1. A circuit for solving the output overshoot when the load of the LDO jumps, including a gate driving module, a gate equivalent or compensating capacitor, an output driving power transistor, a feedback network, and an MCU digital core. The output end of the gate driving module, the gate equivalent or compensating capacitor, and the gate of the output driving power transistor are sequentially connected. The drain of the output driving power transistor is connected to the MCU digital core. The feedback network is respectively connected to the input end of the gate driving module and the drain of the output driving power transistor. Its characteristics are as follows: It further includes an LDO output sampling module, an overshoot / undershoot detection module, a timing module, and a voltage charge adjustment module that are sequentially connected; The input end of the LDO output sampling module is connected to the drain of the output driving power transistor; The output end of the voltage charge adjustment module is connected to the gate of the output driving power transistor.

2. The circuit for solving the output overshoot during LDO load transition according to claim 1, wherein: The overshoot / undershoot detection module includes an overshoot determination unit for determining whether the output voltage has an overshoot; and a degree determination unit for determining the degree of overshoot; The overshoot determination unit is connected to the degree determination unit; The overshoot determination unit can set a threshold value, and when it exceeds or is lower than the set threshold value, it determines an overshoot or an undershoot; The degree determination unit determines a mild overshoot, a severe overshoot, a mild undershoot, and a severe undershoot through threshold setting; and outputs the detection result to the timing module.

3. The circuit for solving the output overshoot when the LDO load jumps according to claim 2, characterized in that: The timing module can be a system high-speed clock, an RC delay circuit, or takes the LDO mode switching signal Mode as an input, and the timing module performs timing control.

4. A circuit for solving the output overshoot when the LDO load jumps according to claim 3, characterized in that: The voltage charge adjustment module includes a method adjustment unit for pre-controlling the gate signal of the driving transistor and a control amount adjustment unit; the method adjustment unit includes: (1) Setting a voltage value for the gate of the output driving power transistor; (2) Pre-charging the gate of the output driving power transistor with charge.

5. A circuit for solving the output overshoot when the LDO load jumps, according to claim 4, characterized in that: The specific voltage value input parameter for setting the voltage of the gate of the output driving power transistor is based on the output result of the degree determination unit of the overshoot / undershoot detection module.

6. A circuit for solving the output overshoot when the LDO load jumps according to claim 4, characterized in that: The specific pre-charging of the gate of the output driving power transistor with charge is as follows: A. When the load changes from light load to heavy load: The gate of the output driving power transistor is A under light load and B under heavy load. The equivalent and compensating capacitance of the gate of the output driving power transistor is Cc; The pre-charge charge Q = CV = Cc*(GB - GA) can be calculated. And Q = IT, where T is the timing data of the previous-stage timing module. Then the charging current I = Q / T = CV / T = Cc*(GB - GA) / T can be obtained. The charging current is set with the input parameter based on the output result of the degree determination unit of the overshoot / undershoot detection module; B. When the load changes from heavy load to light load: The gate of the output driving power transistor is C under heavy load and D under light load. The equivalent and compensating capacitance of the gate of the output driving power transistor is Cc; The pre-discharge charge Q = CV = Cc*(GC - GD) can be calculated. Similarly, Q = IT, where T is the timing data of the previous-stage timing module. Then the discharge current I = Q / T = CV / T = Cc*(GC - GD) / T can be obtained. It is set with the input parameter based on the output result of the degree determination unit of the overshoot / undershoot detection module.

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