Oscillation circuit and thyristor driving circuit

Abstract

The invention relates to a power control and regulation circuit, in particular to an oscillation circuit and a thyristor driving circuit. A Discharge pin of the NE555DR chip is connected with a first modulation circuit unit which is used for adjusting the output duty ratio and the PWM waveform frequency of the NE555 chip, a Reset pin of the NE555DR chip is connected with a control signal input end, the Reset pin is connected with a signal pull-down unit, and the signal pull-down unit is connected with the first modulation circuit unit. After the pull-down unit is connected to the RESET pin, the RESET pin is kept at a low level in a normal state, after a control signal input end inputs a signal, the RESET pin reaches a high level, and the NE555DR chip starts to work to output a PWM (Pulse Width Modulation) signal. The charging and discharging characteristics of the waveform modulation capacitor are controlled through the first modulation resistor and the first modulation diode which are connected in parallel, so that the NE555DR chip outputs a PWM waveform signal, a control signal is accessed, the chip starts to work only when the control signal is input, the PWM signal is output to the outside, and the waveform integrity of the PWM signal is ensured.

Description

Technical Field

[0001] The present invention relates to a power control and regulation circuit, and particularly to an oscillation circuit and a thyristor drive circuit. Background Art

[0002] A thyristor is a semiconductor device commonly used in power electronics. When the thyristor is operating, a trigger signal is sent to it through a thyristor drive circuit. The thyristor switches from the off state to the conducting state and remains in the conducting state until the external current drops to a certain value. Thyristors can be widely applied in rectification, voltage regulation, pulse control and other fields.

[0003] The existing thyristor drive circuit uses an oscillation circuit composed of an NE555 chip and a D flip-flop to drive. After the oscillation circuit is powered on, the NE555 emits a PWM wave. The frequency of this PWM waveform is reduced to 20 kHz through a D flip-flop. The control signal and the 20 kHz PWM wave are coupled and output through an AND gate. The AND gate coupling signal is used to form a thyristor drive signal. The thyristor drive signal is enhanced in driving ability through a push-pull circuit to drive the MOSFET switch, and finally the required drive waveform is output through a transformer.

[0004] The PWM control wave modulated by the existing thyristor drive circuit is in a wave-emitting state all the time after the drive circuit is powered on. If the PWM is at a high level, as Figure 1 shown, the time to control the drive to access the first drive of the thyristor may be short, and the duration of the PWM high level is short. The thyristor may not be fully turned on. The thyristor needs to reach a certain gate trigger current (IGT) to turn on. If the duration of the drive signal is insufficient, it may not provide enough trigger current, resulting in the thyristor not being effectively turned on and the circuit not working properly. Summary of the Invention

[0005] In a first aspect, an embodiment of the present application provides an oscillation circuit to solve the problem that the high level duration of the first PWM waveform is short when the existing oscillation circuit controls a thyristor drive through a NAND gate.

[0006] The oscillation circuit of the embodiment of the present application includes an NE555DR chip. It is improved in that it includes an NE555DR chip, and is characterized in that a first modulation circuit unit for adjusting the output duty cycle and the PWM waveform frequency of the NE555 chip is connected to the Discharge pin of the NE555DR chip, a second modulation circuit unit is connected to the Threshold pin and the Trigger pin of the NE555DR chip, the second modulation circuit unit includes a waveform modulation capacitor, the Reset pin of the NE555DR chip is connected to a control signal input terminal, and the Reset pin is connected to a signal pull-down unit, the signal pull-down unit;

[0007] After the pull-down unit is connected to the RESET pin, the RESET pin is normally kept at a low level. After a signal is input at the control signal input terminal, the RESET pin reaches a high level, and the NE555DR chip starts to work and outputs a PWM signal, so that the control signal and the PWM signal are sent synchronously.

[0008] Due to the adoption of the above circuit, the oscillation circuit of the embodiment of the present application controls the charge and discharge characteristics of the waveform modulation capacitor through the first modulation resistor and the first modulation diode connected in parallel, so that the output duty cycle of the NE555DR chip is 50%, and the signal of the PWM waveform with a frequency of 20 kHz. At the same time, by adjusting the RESET pin of the NE555DR chip, a pull-down resistor is connected, and a control signal BP_SCR is connected, so that the chip starts to work only when the control signal BP_SCR is input, and outputs a PWM signal externally, ensuring the integrity of the PWM signal waveform.

[0009] In a possible implementation manner, the first modulation circuit unit includes a first modulation resistor and a first modulation diode connected in parallel.

[0010] In a possible implementation manner, the first modulation circuit unit is connected to the power input terminal through a voltage-dividing resistor.

[0011] In a possible implementation manner, the VCC pin of the NE555DR chip is connected to the power input terminal, and a 15V DC power supply is input to the power input terminal.

[0012] In a possible implementation manner, the Control pin of the NE555DR chip is connected to a third modulation circuit unit for adjusting the threshold voltage of the comparator inside the NE555DR chip. The third modulation circuit unit includes an adjustment capacitor. The positive electrode of the adjustment capacitor is connected to the Control pin, and the negative electrode of the adjustment capacitor is grounded.

[0013] In a possible implementation manner, the OUT pin of the NE555DR chip outputs a PWM signal with a duty cycle of 50% and a frequency of 20 kHz.

[0014] The embodiment of the present application further provides a thyristor drive circuit, including the oscillation circuit of the above first aspect.

[0015] In a possible implementation, the oscillation circuit and an interlock circuit are connected to an input terminal of a gate circuit. The gate circuit includes two input terminals and one output terminal. The output terminal of the oscillation circuit is connected to one of the output terminals of the gate circuit. The input terminal of the interlock circuit is connected to a control signal input terminal. The output terminal of the interlock circuit is connected to the other output terminal of the gate circuit. The output terminal of the gate circuit is connected to a thyristor. Description of the Drawings

[0016] Figure 1 It is a waveform diagram output when an existing oscillation circuit cooperates with a D flip-flop;

[0017] Figure 2 It is a schematic diagram of module connection according to the first embodiment of the present application;

[0018] Figure 3 It is a detailed circuit connection schematic diagram according to the first embodiment of the present application;

[0019] Figure 4 It is a waveform diagram output according to the first embodiment of the present application;

[0020] Figure 5 It is a schematic diagram of module connection according to the second embodiment of the present application;

[0021] Figure 6 It is a detailed circuit connection schematic diagram according to the second embodiment of the present application. Detailed Description of the Embodiments

[0022] The following further detailed description is made in conjunction with specific embodiments and the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments, rather than all of the embodiments. Based on the following embodiments, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall also fall within the protection scope of the present invention.

[0023] It should be understood that the controllers and control circuits involved in the embodiments are conventional control technologies or units in the art. For example, the control circuits of the controllers can be implemented by those of ordinary skill in the art using existing technologies.

[0024] The disclosure of the embodiments provides many different implementation manners or examples for implementing different solutions of the present invention. To simplify the disclosure of the present invention, the components and settings of specific examples are described in the embodiments. Of course, they are only examples and are not intended to limit the present invention. In addition, reference numerals and / or reference letters may be repeated in different examples in the embodiments. This repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various implementation manners and / or settings being discussed. Moreover, if examples of various specific processes and materials are provided in the embodiments, those of ordinary skill in the art can be aware of the application of other processes and / or the use of other materials.

[0025] To clearly illustrate the detailed working principle of the embodiments of the present application, the functions and principles of the NE555DR chip are briefly described first. The NE555DR is a commonly used timer chip, belonging to a model of the NE555 timer series. It is an integrated circuit (IC) and is widely used in aspects such as generating pulses, timing control, and frequency generation. The NE555 timer can set parameters such as the timing length, frequency, and pulse width through externally connected resistors and capacitors.

[0026] The NE555 timer has 8 pins, and the functions of several common pins are as follows:

[0027] Pin 1 (GND): Ground.

[0028] Pin 2 (Trigger): Trigger input terminal. Connecting a low-level signal triggers the timer to work (only applicable to the monostable and bistable modes).

[0029] Pin 3 (Output): Output terminal, outputting timing pulses.

[0030] Pin 4 (Reset): Reset input terminal. When it is at a low level, the timer is reset and the output becomes low level.

[0031] Pin 5 (Control): Voltage control terminal, usually connected to a capacitor (usually 0.01 μF), used to adjust the threshold voltage of the internal comparator and affect the timing accuracy.

[0032] Pin 6 (Threshold): Threshold input terminal, used to monitor the voltage of the capacitor.

[0033] Pin 7 (Discharge): Discharge terminal, used to discharge the capacitor to a low level.

[0034] Pin 8 (VCC): Power input terminal, usually connected to a +5V or +12V power supply.

[0035] The NE555 timer usually has three operating modes: monostable mode, astable mode, and bistable mode. As the thyristor drive circuit mainly utilizes the astable mode, in the astable mode, the output signal of the 555 timer continuously switches states, generating a continuous pulse signal.

[0036] When the existing NE555 is used as the oscillation circuit for thyristor drive, after the drive circuit is powered on, the OUT pin of the NE555DR chip is connected to the input terminal of the D flip-flop. The NE555DR emits a PWM waveform signal with a duty cycle of 50% and a frequency of 40Khz. The D flip-flop reduces the frequency of the PWM waveform signal to 20Khz. The control signal and the 20Khz PWM waveform signal are connected to the AND gate circuit for coupling to obtain a gate-coupled signal. Then, after the signal intensity is enhanced through the push-pull circuit, the thyristor is driven, and finally, the required drive waveform is output through the transformer. However, in the above circuit composition principle, the core of the D flip-flop is NAND gate control. Among them, the PWM control wave for modulation has been in the wave-emitting state since the drive circuit is powered on, and the modulation waveform is continuously output for a long time. Taking the PWM wave with a 20k duty cycle of 50% as an example, each cycle of this waveform is 50 microseconds. Since the duty cycle is 50%, the waveform is high level for 25 microseconds and low level for 25 microseconds.

[0037] If the drive waveform is emitted 15 microseconds after the high level is emitted, then a 10-microsecond drive output will be coupled with the control signal. And the normal drive waveform is a 25-microsecond drive signal. This is Figure 1 the reason for the shorter first drive time in

[0038] Ultimately, it is because the two signals are not synchronized, and it is impossible to ensure the coupling time of the control signal and the modulation waveform. Therefore, after the first drive waveform is emitted, the thyristor may not be fully turned on. The thyristor needs to reach a certain gate trigger current (IGT) to turn on. If the duration of the drive signal is insufficient, it may not provide enough trigger current, resulting in the thyristor not being effectively turned on and the circuit not working properly.

[0039] As Figure 2 and Figure 3 shown, in this embodiment, the oscillation circuit includes the NE555DR chip 10. The NE555DR includes the GND pin 1, the TRIGGER pin 2, the OUTPUT pin 3, the RESET pin 4, the CONTROL pin 5, the THRESHOLD pin 6, the DISCHARGE pin 7, and the VCC pin 8. Among them, in Figure 2 andFigure 3 Among them, the TRIGGER pin 2 is labeled as TRIG, the CONTROL pin 5 is labeled as CONT, the THRESHOLD pin 6 is labeled as THRES, and the DISCHARGE pin 7 is labeled as DISCH.

[0040] The DISCHARGE pin of the NE555DR chip 10 is connected to a first modulation circuit unit 20 for adjusting the duty cycle and PWM waveform frequency of the output of the NE555DR chip. The first modulation circuit 20 unit includes a first modulation resistor R155 and a first modulation diode D24 connected in parallel. The Threshold pin and Trigger pin of the NE555DR chip 10 are connected to a second modulation circuit unit 30. The second modulation circuit unit 30 includes a waveform modulation capacitor C88. The Reset pin of the NE555DR chip is connected to a control signal input terminal 40, and the Reset pin is connected to a signal pull-down unit 50. The signal pull-down unit 50 includes a pull-down resistor R99, and the pull-down resistor R99 is grounded.

[0041] Due to the adoption of the above circuit, the oscillation circuit of the embodiment of the present application controls the charge and discharge characteristics of the waveform modulation capacitor through the first modulation resistor R155 and the first modulation diode D24 connected in parallel, so that the output duty cycle of the NE555DR chip is 50%, and a signal of a PWM waveform with a frequency of 20 kHz is output. At the same time, by adjusting the RESET pin of the NE555DR chip, a pull-down resistor is connected, and a control signal BP_SCR is connected, so that the chip starts to work only when the control signal BP_SCR is input, and outputs a PWM signal externally, ensuring the integrity of the PWM signal waveform; at the same time, after the pull-down circuit is connected to the RESET pin, its normal state remains low level, and the chip does not work and does not output externally when the RESET pin is at low level. Only when the control signal BP_SCR is input, the RESET pin returns to high level again, and the chip continues to work, so that the control signal and the PWM wave signal are synchronously sent out, thus as Figure 4 shown, a drive signal with a drive waveform of 25 microseconds is obtained, enabling the thyristor to be fully turned on.

[0042] In order to meet the signal parameter requirements in this embodiment, the VCC pin of the NE555DR chip is connected to a power input terminal 60, and a 15V DC power supply is input to the power input terminal. When the resistance value of the first modulation resistor R155 is 33 kΩ and the capacitance of the first modulation capacitor c88 is 1 nF, a waveform with a duty cycle of 50% and a frequency of 20 kHz can be output.

[0043] In this embodiment, the first modulation circuit unit is connected to the power input terminal 60 through a voltage dividing resistor R154. Based on the above parameters, the resistance value of the first voltage dividing resistor R154 is 33 kΩ.

[0044] In this embodiment, the CONTROL pin of the NE555DR chip 10 is connected to a third modulation circuit unit 70 for adjusting the threshold voltage of the comparator inside the NE555DR chip. The third modulation circuit unit 70 includes a second modulation capacitor C89.

[0045] The OUTPUT pin is connected to the PWM signal output terminal 80.

[0046] The second embodiment of the present application further provides a thyristor drive circuit, including the oscillation circuit in the above first embodiment.

[0047] Figure 5 An application example of a thyristor drive circuit including the oscillation circuit in the above first embodiment is given, as Figure 5 shown

[0048] The thyristor circuit includes an oscillation circuit 100, an interlock circuit 200, and a gate circuit 300. The input terminal of the oscillation circuit 100 inputs a control signal and a power supply. The input terminal of the interlock circuit 200 inputs a control signal and a power supply. The oscillation circuit 100 inputs a PWM signal to one path of the gate circuit 300. The interlock circuit 200 inputs a processed control signal to the gate circuit. The gate circuit 300 outputs a coupled control signal to the thyristor.

[0049] After being processed by the interlock circuit, the control signal can stabilize the input signal, strengthen the control signal, and at the same time play an isolation and protection role for the subsequent circuit.

[0050] Figure 6 A circuit structure diagram of a specific interlock circuit connected to the oscillation circuit and the gate circuit in the first embodiment is provided as an application example.

[0051] As Figure 6 shown, in the interlock circuit 200, when the BP_SCR signal is at a low level, the base of Q1 is at a low level and Q1 is not conducting. The base of Q13 is at a high level. Since Q13 is a PNP type triode, Q13 is also not conducting. At this time, the output signal is pulled low by R212, maintaining a low level output.

[0052] When the BP_SCR signal is at a high level, the base of Q1 is at a high level and Q1 is conducting. +15V is pulled to the ground by Q1. The base of Q13 is at a low level. Since Q13 is a PNP type triode, Q13 is conducting. At this time, the output signal is pulled high, maintaining a high level output.

[0053] Due to the existence of Q13, even if the input is a small signal, the output is a high-voltage signal, which is signal enhancement.

[0054] If the BP_SCR signal and +15V are abnormal during use, only Q1 and Q13 will be damaged, and the subsequent circuit will not be affected. This is the protection function.

[0055] The foregoing are only the preferred embodiments of the embodiments of the present application, and do not limit the scope of disclosure of the embodiments of the present application. Any equivalent structure or equivalent process transformation made by using the description of the embodiments of the present application and the content of the drawings, or directly or indirectly applied to other related technical fields, are equally included in the scope of patent protection supported by the embodiments of the present application.

Claims

1. An oscillator circuit, comprising an NE555DR chip, characterized in that, The Discharge pin of the NE555DR chip is connected to a first modulation circuit unit for adjusting the duty cycle of the output of the NE555 chip and the frequency of the PWM waveform. The Threshold pin and the Trigger pin of the NE555DR chip are connected to a second modulation circuit unit. The second modulation circuit unit includes a waveform modulation capacitor. The Reset pin of the NE555DR chip is connected to a control signal input terminal, and the Reset pin is connected to a signal pull-down unit, the signal pull-down unit; After the pull-down unit is connected to the RESET pin, the RESET pin is normally kept at a low level. After a signal is input at the control signal input terminal, the RESET pin reaches a high level, and the NE555DR chip starts to work and outputs a PWM signal, so that the control signal and the PWM signal are sent out synchronously.

2. The oscillator circuit according to claim 1, characterized in that, The first modulation circuit unit includes a first modulation resistor and a first modulation diode connected in parallel.

3. The oscillating circuit according to claim 2, characterized in that, The first modulation circuit unit is connected to the power input terminal through a voltage-dividing resistor.

4. The oscillating circuit according to claim 1, wherein, The VCC pin of the NE555DR chip is connected to the power input terminal, and a 15V DC power supply is input to the power input terminal.

5. The oscillator circuit according to claim 1, wherein The Control pin of the NE555DR chip is connected to a third modulation circuit unit for adjusting the threshold voltage of the internal comparator of the NE555DR chip. The third modulation circuit unit includes an adjustment capacitor. The positive electrode of the adjustment capacitor is connected to the Control pin, and the negative electrode of the adjustment capacitor is grounded.

6. The oscillator circuit according to claim 1, characterized in that, The OUT pin of the NE555DR chip outputs a PWM signal with a duty cycle of 50% and a frequency of 20kHz.

7. A thyristor drive circuit, characterized in that, An oscillation circuit according to any one of claims 1-6 is included.

8. The thyristor drive circuit according to claim 7, characterized in that, The oscillation circuit and an interlock circuit are connected to an input terminal of a gate circuit. The gate circuit includes two input terminals and one output terminal. The output terminal of the oscillation circuit is connected to one output terminal of the gate circuit. The input terminal of the interlock circuit is connected to the control signal input terminal. The output terminal of the interlock circuit is connected to the other output terminal of the gate circuit. The output terminal of the gate circuit is connected to a thyristor.

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