Silicon carbide planar MOS device polysilicon gate self-alignment process and low-resistance structure

Abstract

The invention relates to the technical field of MOS semiconductors, and discloses a silicon carbide plane MOS device polysilicon gate self-alignment process and a low resistance structure, the silicon carbide plane MOS device polysilicon gate self-alignment process comprises a plurality of parallel MOS cells, each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode, the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, an N well layer, a P + layer and a P well layer, and the N drift layer comprises a drain electrode, a source electrode and a grid electrode. The height of the P well layer in the single MOS cell is aligned with that of the grid electrode, and the P well layer is located on the left side and the right side of the grid electrode; the N well layer and the P + layer are both located above the grid electrode and the P well layer, and the P + layer is located on the outer side of the N well layer. According to the invention, the height of the P well layer is accurately aligned with the grid electrode, the P well layer is arranged at the two sides of the grid electrode, the design of the T-shaped source electrode is combined, the conduction path is optimized, and when the voltage is applied to the grid electrode, vertical channels are formed at the two sides of the P well layer, so that the path of current flowing from the drain electrode to the source electrode through the N drift layer is shorter and the distribution is uniform.

Description

Technical Field

[0001] The present invention relates to the field of MOS semiconductor technology, and in particular to a polysilicon gate self-alignment process and a low-resistance structure for a silicon carbide planar MOS device. Background Art

[0002] Silicon carbide (SiC) planar MOS devices have significant advantages in high-voltage and high-temperature applications due to the high breakdown field strength and high thermal conductivity of the material. However, due to the low carrier mobility of SiC and the defects of traditional processes, they still face problems such as too high on-resistance (Rdson) and reliability issues caused by the alignment deviation between the gate and the well region. In the prior art, the polysilicon gate structure is prone to non-uniform channel conduction caused by lithography overlay errors, increasing the conduction loss; the source contact design has insufficient optimization of current spreading, further exacerbating the contact resistance.

[0003] The prior patent discloses a low dislocation density, high reliability high and low voltage CMOS self-alignment double well process method and device (publication number CN113380799A). The method steps are as follows: 1) forming a high-voltage N-type well and a low-voltage N-type well with low defect density; 2) forming a self-aligned P-type well; 3) compatible high and low voltage compatible thick and thin gate oxide structures; 4) compatible multi-layer metal interconnection structures. This application solves the problems of high on-resistance and electric field concentration unique to SiC MOS devices not involved in this prior patent. By precisely self-aligning the P well and the gate to form a vertical channel to shorten the current path, and the "T"-shaped source design to reduce the contact resistance, and introducing a high-resistance N layer or isolation ring under the gate to optimize the electric field distribution, thereby synergistically improving the current-carrying capacity, breakdown voltage reliability, and thermal stability of SiC devices, making up for the deficiency that the comparative document only focuses on the dislocation control of the well region of silicon-based CMOS and lacks a solution to the core bottleneck of wide bandgap semiconductor high-voltage devices. Summary of the Invention

[0004] The present invention provides a polysilicon gate self-alignment process and a low-resistance structure for a silicon carbide planar MOS device to solve the existing technical problems, and solves the problem that the electric field concentration phenomenon under the gate is significant under high-voltage conditions, restricting the breakdown voltage capacity and long-term stability of the device.

[0005] To solve the above technical problems, according to one aspect of the present invention, more specifically, a polysilicon gate low-resistance structure for a silicon carbide planar MOS device includes a plurality of MOS cells arranged in parallel. Each MOS cell includes a drain, a semiconductor epitaxial layer, a source, and a gate. The semiconductor epitaxial layer includes an N substrate layer, an N drift layer, an N well layer, a P+ layer, and a P well layer. The height of the P well layer in each MOS cell is aligned with the gate, and the P well layer is located on the left and right sides of the gate; the N well layer and the P+ layer are both located above the gate and the P well layer, and the P+ layer is located outside the N well layer; The cross-sectional profile of the source electrode is in a "T" shape. The source electrode includes a horizontal part and a vertical part. The vertical part makes ohmic contact with the inner side of the N-well layer, and the horizontal part makes ohmic contact with both the N-well layer and the P+ layer simultaneously.

[0006] Furthermore, a high-resistance N layer is formed by ion implantation inside the N-substrate layer and near the N-drift layer. This high-resistance N layer is located directly below the gate, and the width of the high-resistance N layer is not less than the width of the gate.

[0007] Furthermore, a plurality of isolation rings are formed by ion implantation inside the N-substrate layer and near the N-drift layer.

[0008] Furthermore, the cross-sectional profile of a single isolation ring is in a semi-elliptical shape, and the total width of the plurality of isolation rings does not exceed the width of the gate.

[0009] Furthermore, a doped polysilicon layer is deposited inside the N-substrate layer and directly below the gate.

[0010] Furthermore, the width of the doped polysilicon layer is not less than the width of the gate, and this doped polysilicon layer makes ohmic contact with the drain electrode.

[0011] Furthermore, a lightly doped N- layer is formed by low-concentration ion implantation inside the N-drift layer of a single MOS cell. The lightly doped N- layer is located directly below the gate, and this lightly doped N- layer divides the N-drift layer in a single MOS cell into two left and right parts.

[0012] A polysilicon gate self-alignment process for a silicon carbide planar MOS device includes the following steps: S1. Grow an N-drift layer outward on the surface of the N-substrate layer by chemical vapor deposition. S2. Deposit a composite hard mask layer on the surface of the N-drift layer, lithographically define the window of the gate region, and use the hard mask as a blocking layer to perform inclined aluminum ion implantation to form a P-well layer. S3. Lithographically define the region directly below the gate, and form a high-resistance N layer by injecting low-dose phosphorus ions; or lithographically define a semi-elliptical window at the edge of the gate, and form isolation rings by multiple energy gradient boron ion implantations. S4. Etch the back of the N-substrate to the region directly below the gate, deposit a phosphorus-doped polysilicon layer, and metallize the back to form the drain electrode. S5. Inject low-concentration nitrogen ions in the N-drift layer region to form a lightly doped N- layer, dividing the N-drift layer into left and right symmetric regions. S6. Using the edge of the P-well as an alignment reference, lithographically define the gate pattern and deposit polysilicon to form the gate, and then lithographically define the N-well region and form the N-well layer by injecting nitrogen ions. S7. Etch deep trenches in the semiconductor epitaxial layer to the inside of the N-well layer, fill the metal in contact with the N-well layer ohmically, and the filled metal extends and covers the N-well layer and the outer P+ layer to form the source electrode.

[0013] A polysilicon gate self-alignment process and a low-resistance structure for a silicon carbide planar MOS device provided by the present invention, compared with the prior art, the effects achieved by this method are as follows: 1. By precisely aligning the P-well layer height with the gate and placing it on both sides of the gate, and combining with the "T"-shaped source electrode design, the present invention optimizes the conduction path. When a voltage is applied to the gate, vertical channels are formed on both sides of the P-well layer, making the path for current to flow from the drain through the N-drift layer to the source electrode shorter and more evenly distributed. Moreover, the dual contact between the source electrode and the N-well / P+ layer further reduces the contact resistance, thereby significantly reducing the overall on-resistance of the device and enhancing the current-carrying capacity.

[0014] 2. By implanting low-dose phosphorus ions directly under the gate to form a high-resistance N layer, the width of which covers the gate region, or by using a semi-elliptical isolation ring to achieve stepped electric field dispersion. The high-resistance N layer modulates the electric field distribution to relieve the electric field concentration under the gate; the isolation ring suppresses the edge electric field peak. Both can optimize the electric field distribution, enabling the device to maintain stable blocking ability under high voltage, while significantly reducing the leakage current and enhancing the breakdown voltage reliability.

[0015] 3. By adopting a self-alignment process based on the P-well edge, lithographically defining the gate and the N-well region, the mask alignment error is reduced. Combining the gradient energy implantation of the composite hard mask with inclined implantation of the P-well and the semi-elliptical isolation ring ensures the doping accuracy of the key areas. This design reduces the process complexity, improves the device parameter consistency, and avoids performance fluctuations caused by alignment deviation.

[0016] 4. By etching the back of the N-substrate to under the gate and depositing a low-concentration phosphorus-doped polysilicon layer to form a vertical low-resistance channel in ohmic contact with the drain. By controlling the doping concentration, the resistivity of the polysilicon layer is increased to ensure uniform current expansion. This structure significantly reduces the drain series resistance, improves the power conversion efficiency, and avoids increasing the cell size at the same time.

[0017] 5. By implanting low-concentration nitrogen ions into the N-drift layer directly under the gate to form a low-doped N- layer, the drift layer is symmetrically divided into left and right parts. This layer serves as a current spreading region, weakens the carrier migration ability, and optimizes the lateral current distribution. By balancing the internal electric field and current density in the cell, the generation of local hot spots is reduced, the conduction loss is lowered, and the thermal stability of the device is enhanced. Description of the Drawings

[0018] Figure 1 It is a schematic diagram of Embodiment 1 in the present invention; Figure 2Schematic diagram of Embodiment 2 in the present invention; Figure 3 Schematic diagram of Embodiment 3 in the present invention; Figure 4 Schematic diagram of Embodiment 4 in the present invention; Figure 5 Schematic diagram of Embodiment 5 in the present invention; Figure 6 Schematic diagram of the principle of the present invention.

[0019] In the figure: 1. Drain; 2. Source; 3. Gate; 4. N-well layer; 5. P+ layer; 6. P-well layer; 7. N-substrate layer; 8. N-drift layer; 9. High-resistance N layer; 10. Isolation ring; 11. Doped polysilicon layer; 12. Low-doped N- layer. Detailed implementation manners

[0020] To make the technical solution of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0021] As Figure 1 - 6 shows, according to one aspect of the present invention, a polysilicon gate self-alignment process for a silicon carbide planar MOS device is provided, including the following steps: Step 1: Grow an N-drift layer 8 outward on the surface of the N-substrate layer 7 by chemical vapor deposition; epitaxially grow a low-doped N-drift layer 8 on the N-type substrate layer 7 by chemical vapor deposition (CVD) as the core region for high-voltage blocking of the device. This can precisely control the thickness and doping concentration of the drift layer, ensure a high breakdown voltage (≥1700V), and at the same time provide a flat substrate for subsequent ion implantation.

[0022] Step 2: Deposit a composite hard mask layer on the surface of the N-drift layer 8, photolithographically define the gate region window, and use the hard mask as a blocking layer to perform inclined implantation of aluminum ions to form the P-well layer 6; after depositing a composite hard mask on the surface of the N-drift layer 8 and photolithographically defining the gate region window, perform inclined implantation of aluminum ions with the hard mask as a blocking layer to form the P-well layer 6 symmetrically distributed on both sides of the gate. The self-alignment positioning of the P-well layer 6 is realized through inclined implantation to avoid the lithography overlay error of the traditional lithography; the height of the P-well layer 6 is aligned with the gate 3, optimizing the vertical channel formation path and reducing the on-resistance.

[0023] Step 3: Photolithograph the region directly below the gate 3, and form a high-resistance N layer 9 by injecting low-dose phosphorus ions; or photolithograph a semi-elliptical window at the edge of the gate, and form an isolation ring 10 by multiple energy gradient injections of boron ions; among them, the high-resistance N layer 9 needs to be formed by injecting extremely low-dose phosphorus ions. Its design purpose is for high-resistance characteristics, and the phosphorus ion dose needs to be strictly controlled to the lowest effective level during injection to maintain a low carrier concentration and a high resistance value.

[0024] Step 4: Etch the backside of the N substrate 7 to the area directly below the gate 3, deposit a phosphorus-doped polysilicon layer 11, and metallize the backside to form the drain 1; the doped polysilicon layer 11 needs to be doped with low-concentration phosphorus. This layer is located directly below the gate and makes an ohmic contact with the drain. Reducing the phosphorus doping concentration can increase its resistivity, thereby increasing the resistance of the conduction path.

[0025] Step 5: Inject low-concentration nitrogen ions into the N drift layer 8 region to form a lightly doped N- layer 12, dividing the N drift layer 8 into left and right symmetric regions; the lightly doped N- layer 12 needs to be injected with low-concentration nitrogen ions. This layer divides the N drift layer into left and right symmetric regions. When injecting nitrogen ions, a low concentration (close to the intrinsic doping level) needs to be maintained to weaken the carrier migration ability and increase the resistance.

[0026] Step 6: Using the edge of the P-well layer 6 as the alignment reference, lithographically define the gate 3 pattern and deposit polysilicon to form the gate 3. Then, lithographically define the N-well region and form the N-well layer 4 by injecting nitrogen ions; directly use the edge of the P-well layer 6 as the alignment reference to lithographically define the gate pattern and deposit polysilicon to form the gate 3; subsequently, lithographically inject nitrogen ions to form the N-well layer 6. Eliminate the alignment deviation between the gate and the P-well layer 6, improving the process accuracy; the self-alignment design simplifies the process, enhancing device consistency and yield. Step 7: Etch deep trenches in the semiconductor epitaxial layer to the inside of the N-well layer 4, fill with metal to make an ohmic contact with the N-well layer 4, and the filled metal extends and covers the N-well layer 4 and the outer P+ layer 5 to form the source 2. Etch deep trenches to the inside of the N-well layer 4 and fill with metal to form a T-shaped source 2 - the longitudinal part contacts the inside of the N-well layer 4, and the transverse part covers the N-well layer 4 and the outer P+ layer 5. The T-shaped structure realizes double ohmic contact of the N-well / P+ layer, significantly reducing the source contact resistance; the deep trench design shortens the current lateral path, enhancing device reliability.

[0027] Example 1 As Figure 1 、 6 shown, the polysilicon gate low-resistance structure of the silicon carbide planar MOS device is composed of several juxtaposed MOS cells. A single MOS cell includes a drain 1, a semiconductor epitaxial layer, a source 2, and a gate 3. The semiconductor epitaxial layer includes an N substrate layer 7, an N drift layer 8, an N-well layer 4, a P+ layer 5, and a P-well layer 6. It is characterized in that: in a single MOS cell, the height of the P-well layer 6 is aligned with the gate 3, and the P-well layer 6 is located on the left and right sides of the gate 3; the N-well layer 4 and the P+ layer 5 are both located above the gate 3 and the P-well layer 6, and the P+ layer 5 is located outside the N-well layer 4; the cross-sectional profile of the source 2 is in a "T" shape, where the source 2 includes a transverse part and a longitudinal part, and the longitudinal part makes an ohmic contact with the inside of the N-well layer 4, and the transverse part makes an ohmic contact with the N-well layer 4 and the P+ layer 5 simultaneously.

[0028] The working principle of this implementation is as follows: After the drain 1 is connected to the drain voltage, the gate 3 is connected to the gate voltage, and the source 3 is grounded (0V), the gate electric field will apply an electric force to the P-well layers 6 on both the left and right sides, thereby forming a charge channel (such as the black rectangular part in Figure 6 ). At this time, a conduction path will be formed between the drain 1 and the source 2 (such as the movement trajectory of the charges in Figure 6 ).

[0029] By aligning the height of the P-well layer 6 with the gate 3 and placing it on both sides of the gate, and cooperating with the "T"-shaped source 2 design (the longitudinal part contacts the inside of the N-well layer 4, and the transverse part covers both the N-well layer and the P+ layer 5), the conduction path of the device is optimized. When a voltage is applied to the gate, vertical channels are formed on both sides of the P-well layer, making the path for the current to flow from the drain 1 through the N-drift layer 8 to the source 2 shorter and more evenly distributed. This significantly reduces the on-resistance (Rdson) and improves the current-carrying capacity; the dual contact between the source and the N-well / P+ layer reduces the contact resistance and enhances the device reliability.

[0030] Example 2 As shown in Figure 2 , a high-resistance N layer 9 is formed by ion implantation inside the N-substrate layer 7 and near the N-drift layer 8; this high-resistance N layer 9 is located directly below the gate 3, and the width of the high-resistance N layer 9 is not less than the width of the gate 3. A low-dose phosphorus ion is implanted into the N-substrate layer 7 directly below the gate 3 to form the high-resistance N layer 9, and its width covers the gate region. This layer relieves the electric field concentration phenomenon below the gate by modulating the electric field distribution. This can improve the breakdown voltage of the device (such as ≥1700V), while maintaining a low leakage current; the width of the high-resistance layer matches the gate size, avoiding an additional increase in the cell area.

[0031] Example 3 As shown in Figure 3 , several isolation rings 10 are formed by ion implantation inside the N-substrate layer 7 and near the N-drift layer 8. The cross-sectional profile of a single isolation ring 10 is semi-elliptical, and the total width of several isolation rings 10 does not exceed the width of the gate 3. Boron ions are implanted into the N-substrate layer 7 below the edge of the gate to form multiple isolation rings 10 with a semi-elliptical cross-section, and the total width is controlled within the gate width. The depth distribution of the rings is optimized by gradient energy implantation to achieve a stepped dispersion of the electric field. This design can significantly suppress the peak value of the edge electric field and improve the breakdown voltage stability; the semi-elliptical structure maximizes the use of space and avoids an increase in the device size.

[0032] Example 4 As shown in Figure 4As shown, a doped polysilicon layer 11 is deposited inside the N substrate layer 7 and directly below the gate 3. The width of the doped polysilicon layer 11 is not less than the width of the gate 3, and the doped polysilicon layer 11 is in ohmic contact with the drain 1. Etch the back of the N substrate 7 to the area directly below the gate, deposit the phosphorus-doped polysilicon layer 11 and make it in ohmic contact with the drain 1 to form a low-resistance vertical current channel. This design significantly reduces the drain series resistance; the width of the polysilicon layer matches the gate to ensure uniform current conduction and improve the power conversion efficiency.

[0033] Embodiment 5 As Figure 5 shown, a lightly doped N- layer 12 is formed by low-concentration ion implantation inside the N drift layer 8 in a single MOS cell. The lightly doped N- layer 12 is directly below the gate 3, and the lightly doped N- layer 12 divides the N drift layer 8 in the single MOS cell into two left and right parts. Inject low-concentration nitrogen ions into the N drift layer 8 directly below the gate to form the lightly doped N- layer 12, symmetrically dividing the drift layer into two left and right parts. This layer serves as a current spreading region to optimize the lateral current distribution. This design balances the internal electric field and current density of the cell, reduces the on-state loss; at the same time maintains the high blocking voltage capability and improves the thermal stability of the device.

[0034] The above-described embodiments merely represent several implementation manners of the present invention. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent for the present invention. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent for the present invention shall be subject to the appended claims.

Claims

1. A low-resistance structure for the polysilicon gate of a silicon carbide planar MOS device, which is composed of a number of MOS cells arranged side by side. Each of the MOS cells includes a drain (1), a semiconductor epitaxial layer, a source (2), and a gate (3). The semiconductor epitaxial layer includes an N substrate layer (7), an N drift layer (8), an N well layer (4), a P+ layer (5), and a P well layer (6). It is characterized in that: In a single MOS cell, the height of the P-well layer (6) is aligned with the gate (3), and the P-well layer (6) is located on the left and right sides of the gate (3); the N-well layer (4) and the P+ layer (5) are both located above the gate (3) and the P-well layer (6), and the P+ layer (5) is located outside the N-well layer (4). The cross-sectional profile of the source electrode (2) is in a "T" shape, where the source electrode (2) includes a horizontal part and a vertical part. The vertical part is in ohmic contact with the inner side of the N-well layer (4), and the horizontal part is in ohmic contact with both the N-well layer (4) and the P+ layer (5).

2. The low-resistance structure of the polysilicon gate of the silicon carbide planar MOS device according to claim 1, wherein: A high-resistance N layer (9) is formed by ion implantation inside the N-substrate layer (7) and near the N-drift layer (8). The high-resistance N layer (9) is located directly below the gate (3), and the width of the high-resistance N layer (9) is not less than the width of the gate (3).

3. The low-resistance structure of the polysilicon gate of the silicon carbide planar MOS device according to claim 1, wherein: A plurality of isolation rings (10) are formed by ion implantation inside the N-substrate layer (7) and near the N-drift layer (8).

4. The polysilicon gate low-resistance structure of the silicon carbide planar MOS device according to claim 3, wherein: The cross-sectional profile of a single isolation ring (10) is in a semi-elliptical shape, and the total width of the plurality of isolation rings (10) does not exceed the width of the gate (3).

5. The polysilicon gate low-resistance structure of the silicon carbide planar MOS device according to claim 1, wherein: A doped polysilicon layer (11) is deposited inside the N-substrate layer (7) and directly below the gate (3).

6. The low-resistance structure of the polysilicon gate of the silicon carbide planar MOS device according to claim 5, characterized in that: The width of the doped polysilicon layer (11) is not less than the width of the gate (3), and the doped polysilicon layer (11) is in ohmic contact with the drain electrode (1).

7. The polysilicon gate low-resistance structure of the silicon carbide planar MOS device according to claim 1, characterized in that: A low-doped N- layer (12) is formed by low-concentration ion implantation inside the N-drift layer (8) in a single MOS cell. The low-doped N- layer (12) is located directly below the gate (3), and the low-doped N- layer (12) divides the N-drift layer (8) in a single MOS cell into two parts on the left and right.

8. A polysilicon gate self-alignment process for a silicon carbide planar MOS device, characterized in that, Applied to the polysilicon gate low-resistance structure of the silicon carbide planar MOS device according to any one of claims 1-7, the polysilicon gate self-alignment process of the silicon carbide planar MOS device includes the following steps: S1. Grow an N-drift layer (8) outward on the surface of the N-substrate layer (7) by chemical vapor deposition. S2. Deposit a composite hard mask layer on the surface of the N-drift layer (8), lithographically define the window of the gate region, and use the hard mask as a blocking layer to perform inclined aluminum ion implantation to form the P-well layer (6). S3. Lithographically define the region directly below the gate (3), and form the high-resistance N layer (9) by implanting low-dose phosphorus ions; or lithographically define a semi-elliptical window at the edge of the gate, and form the isolation ring (10) by multiple energy gradient boron ion implantations. S4. Etch the back of the N-substrate (7) to the region directly below the gate (3), deposit a phosphorus-doped polysilicon layer (11), and metallize the back to form the drain electrode (1). S5. Inject low-concentration nitrogen ions in the N-drift layer (8) region to form the low-doped N- layer (12) and divide the N-drift layer (8) into two symmetric regions on the left and right. S6. Using the edge of the P-well layer (6) as an alignment reference, lithographically define the pattern of the gate (3) and deposit polysilicon to form the gate (3), and then lithographically define the N-well region and form the N-well layer (4) by injecting nitrogen ions. S7. Etch a deep groove in the semiconductor epitaxial layer to the inside of the N-well layer (4), fill the metal to form an ohmic contact with the N-well layer (4), and the filled metal extends and covers the N-well layer (4) and the outer P+ layer (5) to form the source electrode (2).

Images