3 [mu] m SOI process integration method for on-chip beam forming and wavelength division multiplexing system

Abstract

The invention relates to a 3 [mu] m SOI process integration method for an on-chip beam forming and wavelength division multiplexing system. The method comprises the steps of silicon waveguide etching, PN ion implantation, germanium-silicon epitaxy, germanium-silicon waveguide etching, metal layer growth and the like. In order to solve the problem that the silicon PN doping annealing temperature is higher than the germanium-silicon PN doping annealing temperature, the germanium-silicon epitaxial etching postposition technological process is developed, and the non-selective epitaxy and reverse etching modes are used, so that the problem that a wafer is uneven after silicon etching doping is solved. The method has extremely high application value in large-scale silicon photon integration application, and can be used for manufacturing complex active photon chips integrated with modulators, detectors and the like.

Description

Technical Field

[0001] The present invention belongs to the field of silicon-based optoelectronic devices, and particularly relates to a 3μm SOI process integration method for an on-chip beamforming and wavelength division multiplexing system. Background Art

[0002] Silicon-based optoelectronic technology utilizes silicon and silicon-based substrates, combined with complementary metal-oxide-semiconductor (CMOS) processes, to efficiently develop and integrate optoelectronic devices, becoming one of the indispensable technical solutions in the post-Moore era. High-integration photonic chips contribute to meeting performance requirements such as high-speed signal transmission, improved efficiency through multi-functional integration, reduced packaging and assembly costs, and lower overall power consumption.

[0003] The process steps of silicon-based optoelectronic devices based on the 3μm SOI platform are different from those of the 220nm SOI platform, and it is necessary to optimize the technical details of their process integration. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a 3μm SOI process integration method for an on-chip beamforming and wavelength division multiplexing system, to solve the problems that the annealing temperature of silicon PN doping is higher than that of germanium-silicon PN doping and the wafer is uneven after silicon etching and doping.

[0005] The present invention provides a 3μm SOI process integration method for an on-chip beamforming and wavelength division multiplexing system, including the following steps:

[0006] (1) Dope both sides of the waveguide region to be etched on a 3μm SOI wafer, and then perform three-step etching to fabricate a shallow-etched waveguide, a deep-etched waveguide, and a deep-etched Trench layer respectively;

[0007] (2) Perform P and N ion heavy doping on the slab layer in the deep-etched waveguide region, and then cover it with a SiO2 layer; open the SiO2 layer in the region where germanium-silicon epitaxy is required, and etch out a deep groove for germanium-silicon epitaxy;

[0008] (3) Non-selectively epitaxially grow single-crystalline germanium-silicon and polycrystalline germanium-silicon in the above deep groove, and then reversely etch to remove the top oxide and polycrystalline germanium-silicon, and polish the wafer;

[0009] (4) Etch single-crystalline germanium-silicon and polycrystalline germanium-silicon and perform P and N ion doping;

[0010] (5) Deposit a metal layer, then deposit a SiO2 layer, and wet-etch to remove the SiO2 in the PN doping region in step (4) to fabricate a metal interconnection layer;

[0011] (6) Grow metal by ion sputtering, and etch the above metal layer to form metal wiring;

[0012] (7) Etch the VIA layer in the above metal layer and metal interconnection layer, grow metal by ion sputtering again, and etch the metal layer again to form metal wiring for the thermal tuning device;

[0013] (8) Etch the PAD window for probe testing in part of the metal area, and that's it.

[0014] Preferably, the material of the metal layer in step (5) is TiN.

[0015] Preferably, the metal grown by ion sputtering in steps (6) and (7) is an aluminum-copper alloy (containing 0.5% copper).

[0016] Beneficial effects

[0017] In view of the problem that the annealing temperature of silicon PN doping is higher than that of germanium-silicon PN doping, the present invention has developed a process flow after germanium-silicon epitaxial etching, and uses non-selective epitaxy and reverse etching methods to solve the problem of uneven wafers after silicon etching and doping. The present invention has extremely high application value in the face of large-scale silicon photon integration applications. Using the present invention, complex active photon chips integrated with modulators, detectors, etc. can be fabricated. Description of the drawings

[0018] Figure 1 It is a schematic diagram of fabricating a silicon waveguide by three-step etching in the process steps of the present invention.

[0019] Figure 2 It is a schematic diagram of PN ion doping in the process steps of the present invention.

[0020] Figure 3 It is a schematic diagram of germanium-silicon epitaxy in the process steps of the present invention.

[0021] Figure 4 It is a schematic diagram of opening the probe area in the process steps of the present invention. Detailed implementation manners

[0022] The following further elaborates the present invention in conjunction with specific embodiments. It should be understood that these embodiments are only used to illustrate the present invention and not to limit the scope of the present invention. In addition, it should be understood that after reading the content taught by the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms also fall within the scope defined by the appended claims of this application.

[0023] Example 1

[0024] This example provides a 3μm SOI process integration method for an on-chip beamforming and wavelength division multiplexing system, including the following steps:

[0025] (1) Dope both sides of the waveguide region to be etched on a 3-μm SOI wafer to absorb stray light near the waveguide and reduce crosstalk between devices during high-density integration. Then perform three-step etching to fabricate a shallow-etched waveguide, a deep-etched waveguide, and a deep-etched Trench layer, as Figure 1 shown.

[0026] (2) Perform P and N ion heavy doping on the slab layer in the deep-etched waveguide region, and then cover it with an SiO2 layer, as Figure 2 shown; Open the SiO2 layer in the region where germanium-silicon epitaxy is required, and etch out deep trenches for germanium-silicon epitaxy;

[0027] (3) Non-selectively epitaxially grow single-crystalline germanium-silicon and polycrystalline germanium-silicon in the above deep trenches, and then reverse-etch to remove the top oxide and polycrystalline germanium-silicon, and polish the wafer, as Figure 3 shown;

[0028] (4) Etch single-crystalline germanium-silicon and polycrystalline germanium-silicon and perform P and N ion doping;

[0029] (5) Deposit a layer of TiN metal, and then deposit a layer of SiO2. Wet-etch to remove the SiO2 in the PN doping region in step (4) to fabricate a metal interconnection layer;

[0030] (6) Ion sputter to grow an aluminum-copper alloy (containing 0.5% copper), and etch the above metal layer to form metal wiring;

[0031] (7) Etch the VIA layer in the TiN and metal interconnection layer, ion sputter to grow an aluminum-copper alloy (containing 0.5% copper) again, and etch the metal layer again to form TiN thermal tuning device metal wiring;

[0032] (8) Etch PAD windows for probe testing in some metal regions, that's all, as Figure 4 shown.

[0033] In view of the problem that the annealing temperature of silicon PN doping is higher than that of germanium-silicon PN doping, the present invention has developed a process flow after germanium-silicon epitaxial etching, and uses non-selective epitaxy and reverse etching methods to solve the problem of uneven wafer surface after silicon etching and doping. The present invention has extremely high application value in the face of large-scale silicon photon integration applications. Using the present invention, complex active photon chips integrated with modulators, detectors, etc. can be fabricated.

Claims

1. A 3μm SOI process integration method for on-chip beamforming and wavelength division multiplexing systems, comprising the following steps: (1) Dope both sides of the waveguide region to be etched on the 3μm SOI wafer, and then perform three-step etching to fabricate a shallow-etched waveguide, a deep-etched waveguide, and a deep-etched Trench layer respectively; (2) Perform P and N ion heavy doping on the slab layer in the deep-etched waveguide region, and then cover it with a SiO2 layer; Open the SiO2 layer in the region where germanium-silicon epitaxy is required, and etch out a deep groove for germanium-silicon epitaxy; (3) Non-selectively epitaxially grow single-crystalline germanium-silicon and polycrystalline germanium-silicon in the above deep groove, and then reverse-etch to remove the top oxide and polycrystalline germanium-silicon, and polish the wafer; (4) Etch single-crystalline germanium-silicon and polycrystalline germanium-silicon and perform P and N ion doping; (5) Deposit a metal layer, then deposit a SiO2 layer again, and wet-etch to remove the SiO2 in the PN doping region in step (4) to fabricate a metal interconnection layer; (6) Ion sputter to grow metal, and etch the above metal layer to form metal wiring; (7) Etch the VIA layer in the above metal layer and metal interconnection layer, ion sputter to grow metal again, and etch the metal layer again to form metal wiring for the thermal tuning device; (8) Etch a PAD window for probing test in some metal regions, and that's it.

2. The method according to claim 1, wherein: The metal layer material in step (5) is TiN.

3. The method according to claim 1, wherein: The metal ion sputtered and grown in steps (6) and (7) is an aluminum-copper alloy.

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