Verification method of translation lookaside buffer failure instruction, electronic equipment and computer program product

Abstract

The invention discloses a verification method for a translation lookaside buffer failure instruction, electronic equipment and a computer program product, and is applied to the technical field of memory management of a computer system. A target instruction is inserted and triggered, and the target instruction comprises a TLB failure instruction for the to-be-failed entry; a translation request carrying a target virtual address is sent to a target object, a first translation condition in the process that the target object processes the translation request is obtained, and the target object comprises a translation cache unit or a translation control unit; the target virtual address comprises a virtual address corresponding to the item to be invalid; and determining whether the to-be-invalid item is invalid or not based on the first translation condition. Compared with a mode of verifying the TLB failure instruction by means of a TLB state register, the method is undoubtedly more direct and accurate, and the verification result has higher reliability.

Description

Technical Field

[0001] This application relates to the technical field of memory management in computer systems. Specifically, it relates to the translation lookaside buffer technology in the technical field of memory management in computer systems. More specifically, it relates to a method for verifying translation lookaside buffer invalidation instructions, an electronic device, and a computer program product. Background Art

[0002] The System Memory Management Unit (SMMU) plays a crucial role in modern computing devices and is usually involved in matters such as address translation and cache management.

[0003] The TLB (Translation Lookaside Buffer) is an important part of the SMMU for cache management. It can store the mapping relationship from virtual addresses to physical addresses that have been recently used, thereby accelerating the address translation speed. And in modern processors, the content of the TLB often changes dynamically. Especially in multi-core processors or virtualized environments, each core or virtual machine may have its own copy of the TLB. Currently, when changing the content in the TLB, the TLBI (Translation Lookaside Buffer Invalidate) instruction is usually used to invalidate the entries that need to be invalidated and turn them into invalid entries.

[0004] However, in the scenario of designing a processor, it is usually necessary to verify the TLBI instruction. Although it is possible to verify by checking the TLB entries through the TLB status register, it has certain limitations. In some cases, it cannot accurately capture the status changes of the invalid entries, resulting in poor reliability of the verification results. Summary of the Invention

[0005] To solve the above technical problems, this application provides a method for verifying translation lookaside buffer invalidation instructions, an electronic device, and a computer program product to achieve the purpose of improving the reliability of TLBI instruction verification results.

[0006] To achieve the above technical purpose, the embodiments of this application provide the following technical solutions:

[0007] In a first aspect, the embodiments of this application provide a method for verifying translation lookaside buffer invalidation instructions, and the method for verifying translation lookaside buffer invalidation instructions includes:

[0008] Cache the entries to be invalidated;

[0009] Insert and trigger a target instruction, where the target instruction includes: a TLB invalidation instruction for the entry to be invalidated;

[0010] Send a translation request carrying a target virtual address to a target object, and obtain a first translation situation during the target object's processing of the translation request, where the target object includes: a translation cache unit or a translation control unit; the target virtual address includes: the virtual address corresponding to the entry to be invalidated;

[0011] Determine whether the entry to be invalidated is invalid based on the first translation situation.

[0012] In a second aspect, an embodiment of the present application provides a verification device for a translation lookaside buffer invalidation instruction. The verification device for the translation lookaside buffer invalidation instruction includes:

[0013] A cache module for caching entries to be invalidated;

[0014] An instruction module for inserting and triggering a target instruction, where the target instruction includes: a TLB invalidation instruction for the entry to be invalidated;

[0015] A translation module for sending a translation request carrying a target virtual address to a target object, and obtaining a first translation situation during the target object's processing of the translation request, where the target object includes: a translation cache unit or a translation control unit; the target virtual address includes: the virtual address corresponding to the entry to be invalidated;

[0016] An invalidation determination module for determining whether the entry to be invalidated is invalid based on the first translation situation.

[0017] In a third aspect, an embodiment of the present application provides an electronic device including a processor configured to execute the verification method for a translation lookaside buffer invalidation instruction as described in the first aspect.

[0018] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon. When the computer program is run by a processor, the verification method for a translation lookaside buffer invalidation instruction as described in the first aspect is implemented.

[0019] In a fifth aspect, an embodiment of the present application provides a computer program product or a computer program. The computer program product includes a computer program stored in a computer-readable storage medium; a processor of the computer device reads the computer program from the computer-readable storage medium, and when the processor executes the computer program, the steps of the verification method for a translation lookaside buffer invalidation instruction as described in the first aspect are implemented.

[0020] The verification method for the translation lookaside buffer (TLB) invalidation instruction provided by the embodiment of the present application, after caching the entry to be invalidated, uses the TLB invalidation instruction to invalidate the entry to be invalidated. Then, by means of the mechanism that the target object directly searches for the cache entry when processing the translation request, a translation request for the entry to be invalidated is sent to the target object, where the target object includes: a translation cache unit or a translation control unit. Thus, it can directly penetrate into the object of the cache entry, rather than the TLB status register storing the entry status. Finally, based on the translation result, the invalidation situation of the entry to be invalidated is accurately judged, so as to verify whether the TLB invalidation instruction takes effect. Compared with the method of verifying the TLB invalidation instruction by means of the TLB status register, the present application is undoubtedly more direct and accurate, and the verification result has stronger reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on the provided drawings.

[0022] Figure 1 It is a schematic diagram of a feasible application scenario of a verification method for a translation lookaside buffer invalidation instruction provided by the embodiment of the present application;

[0023] Figure 2 It is one of the flow diagrams of a verification method for a translation lookaside buffer invalidation instruction provided by the embodiment of the present application;

[0024] Figure 3 It is another flow diagram of a verification method for a translation lookaside buffer invalidation instruction provided by the embodiment of the present application;

[0025] Figure 4 It is a schematic diagram of UTLB and MTLB cache entries;

[0026] Figure 5 It is the third flow diagram of a verification method for a translation lookaside buffer invalidation instruction provided by the embodiment of the present application;

[0027] Figure 6 It is a schematic diagram of inserting TLB invalidation instructions and synchronization instructions in the embodiment of the present application;

[0028] Figure 7 It is a structural block diagram of a verification device for a translation lookaside buffer invalidation instruction provided by the embodiment of the present application;

[0029] Figure 8Schematic structural diagram of an electronic device provided for an embodiment of the present application. Detailed implementation manners

[0030] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of this specification shall have the ordinary meanings understood by those of ordinary skill in the art to which this specification pertains. The "first", "second" and similar terms used in the embodiments of this specification do not denote any order, quantity or importance, but are only used to avoid confusion of components.

[0031] Unless otherwise required by the context, throughout this specification, "a plurality" means "at least two", and "including" is interpreted in an open, inclusive sense, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "examples", "specific examples" or "some examples" etc. are intended to indicate that the specific features, structures, materials or characteristics related to the embodiment or example are included in at least one embodiment or example of this specification. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the embodiments in the following content can be understood as implementation manners.

[0032] Next, the technical solutions in the embodiments of this specification will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of this specification. Obviously, the described embodiments are only a part of the embodiments of this specification, rather than all the embodiments. Based on the embodiments in this specification, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of this specification.

[0033] For the convenience of understanding, the relevant terms and concepts mainly involved in the embodiments of the present application will be introduced first below.

[0034] TLB: Short for Translation Lookaside Buffer, that is, translation lookaside buffer. It stores the query results of address conversion that have been performed. Thus, when the same virtual address needs to perform address conversion, the result can be directly queried in the TLB, without having to access the memory multiple times to implement address conversion. Therefore, it can also be called a fast table.

[0035] TBU: Short for Translation Buffer Unit, that is, translation buffer unit. It is an important part of the SMMU. The TBU is a hardware unit that manages the TLB and is responsible for handling the lookup, update and invalidation operations of the TLB. For example, when a peripheral accesses the main memory, the SMMU will first send the virtual address to the TBU for translation. The TBU realizes address translation by querying the entries cached in the TLB.

[0036] TCU: Abbreviation for Translation Control Unit, i.e., the translation control unit. It is also an important part of the SMMU. The TCU also participates in address translation. For example, in the above example, during the translation process of the virtual address by the TBU through managing the TLB, if the TLB misses, the virtual address needs to be sent to the TCU. Then the TCU queries the entries cached in the Walk Cache and further realizes address translation based on the queried entries. Among them, the Walk Cache can cache the corresponding entries when the TCU performs address translation.

[0037] UTLB, i.e., Micro TLB, the micro translation lookaside buffer; MTLB, i.e., Main TLB, the main translation lookaside buffer. UTLB and MTLB are two different types of TLBs. During the process of the TBU realizing address translation by querying the entries cached in the TLB, the TBU first looks for the address translation that matches the translation transaction in the Micro TLB. If it cannot be found in the Micro TLB, it will then look in the Main TLB. Moreover, when caching entries in the TLB, usually the entries are first cached in the UTLB, and after the UTLB is full, the entries are continued to be cached in the MTLB.

[0038] Among them, the following translation request in this application is the memory access request, which is the request carrying the virtual address received by the TCU and the TBU during the address translation process. After receiving this request, the TCU and the TBU will start the address translation process and determine the corresponding physical address according to the virtual address.

[0039] Overview

[0040] As described in the background art, verifying by checking the TLB entries through the TLB status register is a common way to verify the TLBI instruction. Among them, the TLB status register is usually used to indicate the status of each entry in the TLB. For example, whether a certain virtual address has been mapped to a physical address, whether a certain entry is valid, etc. Although reading the TLB status register can reflect some information, there are still multiple limitations, resulting in poor reliability of the verification result of the TLBI instruction. For example, in a multi-core system environment or a high-concurrency environment, the content of the TLB status register may not be updated in real time. There may be a delay between the update and the read operation of the content in the TLB. Especially after an entry in the TLB becomes invalid, the TLB status register may not immediately reflect the change of the entry becoming invalid. Thus, the TLB status register may be out of sync with the actual cache invalidation process executed by the hardware, resulting in inaccurate entry status being read. Another example is that the information provided by the TLB status register usually cannot comprehensively reflect the specific invalidation process of the TLB. For example, when a certain entry has been removed or replaced, the TLB status register may only show a "valid" or "invalid" mark for it, but cannot provide the detailed invalidation reason of the invalid entry or whether it has been correctly cleared during the execution of the TLBI instruction.

[0041] Currently, in order to avoid the above limitations, some techniques propose obtaining snapshots of the TLB before and after executing the TLBI instruction for comparison, and determining the verification result based on the comparison result. However, this method also has limitations. For example, the status of the entries in the TLB may be updated in parallel among multiple threads or cores. If other threads or cores are modifying the entries in the TLB during the process of obtaining the snapshot, then the snapshot cannot accurately reflect the impact of the TLBI instruction. Especially on multi-core processors, the invalidation of entries may occur not only in the TLB of one core, but also involve the TLBs of multiple cores. This concurrent modification causes the snapshot to possibly not accurately capture all the entries that should be invalidated by the TLBI instruction. Another example is that the operations of obtaining the snapshot and performing the comparison itself have a delay. Especially in a large-scale concurrent system, the status of the entries in the TLB may have changed at the moment when the snapshot is obtained. Therefore, no matter which of the above methods for verifying the TLBI instruction is adopted, there will be certain limitations, resulting in poor reliability of the verification result.

[0042] In view of the above technical status quo, the inventors of the present application propose that it is possible to go deep into the object directly affected by the TLBI instruction, so as to accurately capture the invalid entries. After caching the entries, considering that if a failure occurs during retranslation, it is usually caused by the invalidation of the entries. Therefore, this situation can be simulated to verify the TLB invalidation instruction. For this purpose, an embodiment of the present application proposes a method for verifying a translation lookaside buffer invalidation instruction. After caching the entries to be invalidated, the TLB invalidation instruction is used to invalidate the entries to be invalidated. Then, by means of the mechanism that the target object directly looks up the cached entries when processing the translation request, a translation request for the entries to be invalidated is sent to the target object, where the target object includes: a translation cache unit or a translation control unit. Thus, it is possible to directly go deep into the object of the cached entry, rather than the TLB status register storing the entry status. Finally, based on the translation result, the invalidation situation of the entries to be invalidated is accurately judged, so as to verify whether the TLB invalidation instruction takes effect. Compared with the method of verifying the TLB invalidation instruction by means of the TLB status register, the present application is undoubtedly more direct and accurate, and the verification result has stronger reliability.

[0043] Exemplary Scenarios

[0044] The technical solution proposed by the embodiment of the present application is applicable to the application scenario of verifying the TLBI instruction. For the convenience of understanding, the following uses an example to illustrate the application scenario. This application scenario is only an example, and the application scenarios applicable to the technical solution of the present application are not limited to this application scenario. As Figure 1 shown, the hardware architecture in this application scenario includes:

[0045] Translation cache unit 101, translation control unit 102, DTI interconnect module 103, master device agent 104, slave device agent 105, first agent 106, second agent 107. The translation cache unit 101 is the TBU, and the translation control unit 102 is the TCU, which will not be elaborated here. Among them, the translation cache unit 101 and the translation control unit 102 interact with the DTI interconnect module 103 through DTI respectively, so that the two realize data interaction. DTI is short for Distributed Translation Interface, which is a point-to-point interface defined by ARM for the SMMU architecture. The master device agent 104 is connected to the TBS (The transaction slave) ace lite interface of the TBU, and simulates input and output to send untranslated memory access requests to the TBU. For example, the master device agent 104 can be an ACE4 master agent. The slave device agent 105 is connected to the TBM (The transaction master) ace lite interface of the TBU, and simulates the downstream of the TBU to receive the translated memory access requests sent by the TBU. For example, the slave device agent 105 can be an ACE4 slave agent. The first agent 106 is connected to the PROG (APB slave) interface of the TCU to access the internal registers through the PROG interface. For example, the first agent can be an APB4 agent. The second agent 107 is connected to the QTW / DVM (The Queue and Table Walk / Distributed Virtual Memory interface) of the TCU, receives three types of transactions including TTW, command queue read, and DVM complete sent by the TCU, and returns the corresponding data, and at the same time simulates sending DVM commands. For example, the second agent 107 can be an ACE4 agent.

[0046] It can be understood that when the TBU processes untranslated memory access requests, it will cache corresponding entries in the TLB for the virtual addresses in the memory access requests. When the TCU processes untranslated memory access requests, it will cache corresponding entries in the walk cache for the virtual addresses in the memory access requests. In some embodiments, the TLB can be a component unit of the TBU or an independent unit communicatively connected to the TBU, which is not limited here. The walk cache can be a component unit of the TCU or an independent unit communicatively connected to the TCU.

[0047] Exemplary Method

[0048] An embodiment of the present application provides a method for verifying a translation lookaside buffer (TLB) miss instruction, which can be applied to Figure 1 the application scenario shown in Figure 2 to verify the TLB miss instruction. In some embodiments, verifying the TLB miss instruction may be to verify whether the TLB miss instruction can invalidate the entry it acts on. As

[0049] shown, the method for verifying the TLB miss instruction may include:

[0050] S201: Cache the entry to be invalidated.

[0051] In this step, the entry to be invalidated is the entry corresponding to the virtual address cached in the target storage device when the translation buffer unit (TBU) or translation cache unit (TCU) processes the translation request. Among them, the virtual address corresponding to the entry to be invalidated can be any virtual address, which is not limited here. And the number of entries to be invalidated can be one or more. The target storage device includes but is not limited to TLB and walkcache. Among them, TLB may include at least one of unified TLB (UTLB) and multi-level TLB (MTLB). Figure 1 In some embodiments, by sending a translation request, relying on the mechanism of the TBU or TCU to process the translation request, the target storage device can cache the entry to be invalidated. For example, in

[0052] the application scenario shown, the master device proxy 104 can send an untranslated translation request or a memory access request to the translation cache unit 101, so that the corresponding entry can be cached by the TLB as the entry to be invalidated. In some embodiments, the entry to be invalidated can also be directly imported into the target storage device. For example, the entry to be invalidated is pre-generated in a certain electronic device according to the specified data format, and the specified data format is the data format of the entry in the target storage device. Then, the entry to be invalidated in the electronic device is imported into the target storage device. In some embodiments, before caching the entry to be invalidated, the target storage device for caching the entry can be cleared to empty the possible existing entries in it.

[0053] S202: Insert and trigger the target instruction.

[0054] In this step, the target instruction includes: the TLB miss instruction for the entry to be invalidated. After triggering the TLB miss instruction, it will act on the entry to be invalidated to make it invalid.

[0055] S203: Send a translation request carrying the target virtual address to the target object, and obtain the first translation situation during the target object's processing of the translation request.

[0056] In this step, the target object includes: a translation cache unit or a translation control unit; the translation cache unit and the translation control unit, namely the above-mentioned TBU and TCU, which will not be elaborated here. It can be understood that after receiving a translation request, the TBU and TCU will start the address translation process to translate the virtual address carried in the translation request into a physical address in memory. The first translation situation in the process of processing the translation request can represent the translation result and / or the translation process. For example, the first translation situation can represent successfully translating the target virtual address into a physical address by using the entry cached in the above-mentioned target storage device. The first translation situation can also represent a miss of the entry in the above-mentioned target storage device and successfully translating the target virtual address into a physical address through TTW (Translation Table Walk).

[0057] It should be noted that the target virtual address includes: the virtual address corresponding to the entry to be invalidated. When the entry to be invalidated in the cache has not been invalidated, the target object can successfully translate the target virtual address into a physical address by using the entry cached in the above-mentioned target storage device. In some embodiments, if the entry to be invalidated in the cache has been invalidated, then the target object cannot hit the entry in the above-mentioned target storage device during the translation process. Therefore, it can be accurately determined whether the entry to be invalidated is invalid based on the first translation situation. Moreover, the cache in the above-mentioned target storage device can directly reflect the invalidated entry, rather than just marking the status of the entry. Thus, it can provide a more direct hardware-level verification to accurately know whether the entry in the cache is invalid. At the same time, in a scenario where the TLB status register is accessed in parallel among multiple threads or cores, the above-mentioned target storage device is usually used to immediately reflect the changes in the hardware state. Thus, it can avoid misjudgment that may be caused by delay or concurrent update when reading the TLB status register. This application verifies the invalidation or effectiveness of the TLB invalidation instruction by whether the entry to be invalidated is invalid. For example, if the entry to be invalidated is invalid, it can be determined that the TLB invalidation instruction is effective and successfully changes the entry it targets to the invalid state. If the entry to be invalidated is not invalid, it can be determined that the TLB invalidation instruction is invalid and fails to successfully change the entry it targets to the invalid state.

[0058] In the embodiments of the present application, after caching the entry to be invalidated, the TLB invalidation instruction is used to invalidate the entry to be invalidated. Then, by means of the mechanism that the target object directly looks up the cache entry when processing the translation request, a translation request for the entry to be invalidated is sent to the target object, where the target object includes: a translation cache unit or a translation control unit. Thus, it is possible to directly penetrate into the object of the cache entry, rather than the TLB status register storing the entry status. Finally, based on the translation result, the invalidation situation of the entry to be invalidated is accurately judged, so as to verify whether the TLB invalidation instruction takes effect. Compared with the method of verifying the TLB invalidation instruction by means of the TLB status register, the present application is undoubtedly more direct and accurate, and the verification result has stronger reliability.

[0059] In some embodiments of the present application, when the target object is a translation control unit, caching the entry to be invalidated includes:

[0060] Sending at least two first translation requests to the target object in sequence, where at least two first translation requests both carry a target virtual address;

[0061] Obtaining the second translation situation during the target object's processing of the target translation request, where the target translation request includes: at least one first translation request other than the first translation request sent for the first time;

[0062] When the second translation situation indicates that the entry corresponding to the target virtual address is successfully cached, the entry corresponding to the target virtual address is determined as the entry to be invalidated.

[0063] It should be noted that the TLB invalidation instruction can act on the entry cached in the walk cache when the TCU processes the translation request, so that the entry in the walk cache becomes invalid. Therefore, for the case where the target object is the TCU or the object caching the entry to be invalidated is the walk cache, the characteristics of the walk cache itself can be used to implement the caching of the entry to be invalidated. In some embodiments, the entry to be invalidated can be cached through the walk cache. When the TCU processes the first translation request, the entry corresponding to the target virtual address is used as the entry to be invalidated and cached in the walk cache.

[0064] After sending the first first translation request to the TCU, since it is uncertain whether the entries to be invalidated will fail to be successfully cached in the walk cache due to other unknown reasons. In this embodiment, its success or failure will be verified. For example, after sending the first first translation request to the TCU, at least one more first translation request is sent. Based on the second translation situation of the subsequent first translation requests, it is determined whether the subsequent at least one first translation request utilizes the entries cached in the walk cache. Furthermore, it is determined whether the entries corresponding to the target virtual address are successfully cached in the walk cache. It can be understood that after sending the first first translation request, if the walk cache successfully caches the entries corresponding to the target virtual address, then the second translation situation can indicate that during the subsequent processing of at least one first translation request, the entries cached in the walk cache are utilized to implement the translation of the target virtual address. If the walk cache fails to successfully cache the entries corresponding to the target virtual address, then the second translation situation can indicate that during the subsequent processing of at least one first translation request, the target virtual address is successfully translated into a physical address through TTW.

[0065] Since the depth of the walk cache is limited, if multiple translation requests are sent at once, there is a high probability that the entries under the first few translation requests will be replaced out of the walk cache, and ultimately lead to inaccurate verification results. Therefore, in some embodiments, only two translation requests carrying the same virtual address can be sent each time.

[0066] In some embodiments, in the case of continuously verifying the TLB invalidation instruction multiple times, after each verification, all caches can be cleared to avoid interference with the next verification. As Figure 3 shown, it includes:

[0067] S301: Check whether the entries to be invalidated are successfully cached in the walk cache. For example, a translation request can be sent first, and then a translation request carrying the same virtual address is sent again. Based on the result of the TCU processing the translation request sent again, it is determined whether the entries to be invalidated are successfully cached in the walk cache. For example, it can be checked whether the result of TTW is successfully cached in the entry of the walk cache. If so, the entries to be invalidated are successfully cached in the walk cache, otherwise, the entries to be invalidated are not successfully cached in the walk cache.

[0068] S302: Insert and trigger the TLB invalidation instruction for the entries to be invalidated.

[0069] S303: Check whether the entries to be invalidated in the walk cache are invalidated.

[0070] S304: Clear all caches. For example, the SMMU_CR0 register and the SMMU_S_CR0 register can be modified to disable the SMMU; write 1 to the INV_ALL bit of the SMMU_S_INIT register and poll until it resumes to 0. Generate an INV_ALL instruction to invalidate all caches; modify the SMMU_CR0 and SMMU_S_CR0 registers again to enable the SMMU.

[0071] In the embodiments of the present application, it can be ensured that the entry to be invalidated is cached successfully, avoiding the situation where its caching fails and affecting the reliability of the final verification result.

[0072] In some embodiments of the present application, when the target object is a translation control unit, the first translation situation includes: the change situation of the first signal and the second signal within the target clock cycle, and the consistency situation between the third signal and the level of the target page table; wherein, the first signal indicates whether the look-up table request is valid, the second signal indicates whether the look-up table hits, the third signal indicates the page table level at the time of the request, and the target page table represents the last-level page table in the translation process;

[0073] Determining whether the entry to be invalidated is invalidated based on the first translation situation includes:

[0074] If the first signal and the second signal are both raised within the target clock cycle and the third signal is consistent with the level of the target page table, it is determined that the entry to be invalidated is not invalidated; otherwise, it is determined that the entry to be invalidated is invalidated.

[0075] It should be noted that during the process of the TCU handling the translation request, it usually first determines whether the translation request is valid. If it is valid, it looks up the table in the walk cache to find the entry corresponding to the virtual address in the translation request. If a page table is hit during the table lookup in the walk cache and the level of this page table is the same as the page table level of the translation request. Then, it indicates that the entry corresponding to the virtual address in the translation request is still valid in the walk cache, and the table lookup process is valid and complete. Otherwise, it can be considered that the entry corresponding to the virtual address in the translation request is already invalid. Therefore, in this embodiment, when obtaining the first translation situation, the first signal, the second signal, and the third signal can be obtained respectively, and it is determined whether all of the following are satisfied simultaneously: the first signal and the second signal are both pulled high within the target clock cycle; the third signal is the same as the level of the target page table. If all of the above are satisfied simultaneously, it can be shown that a page table is hit during the table lookup in the walk cache and the level of this page table is the same as the page table level of the translation request. It can be concluded that the entry to be invalidated has not been invalidated, so the TLB invalidate instruction is considered to have failed and has not successfully invalidated the entry it targets. If all of the above cannot be satisfied simultaneously, it can be concluded that the entry to be invalidated is invalid, and the TLB invalidate instruction can be considered to have taken effect and has successfully invalidated the entry it targets. Among them, when the first signal is pulled high, it indicates that the table lookup request is valid; when the second signal is pulled high, it indicates that a hit occurs during the table lookup.

[0076] In some embodiments, wcb2scb_lookup_rsp_valid can be used as the first signal, wcb2scb_lookup_rsp_payld.message.hit can be used as the second signal, and message.level can be used as the third signal. When it is detected that wcb2scb_lookup_rsp_valid and wcb2scb_lookup_rsp_payld.message.hit are still both pulled high within a specified number of clock cycles, it indicates that within the specified clock cycle, the entry to be invalidated cached is valid and the result of this translation request has been confirmed. If the TLB invalidate instruction for this entry to be invalidated has been executed, the relevant page table entry should have been invalidated, then wcb2scb_lookup_rsp_valid and wcb2scb_lookup_rsp_payld.message.hit will not be both pulled high. At the same time, the lookup of the page table is hierarchical, and each level has a different level value. If the result obtained for a translation request at a certain level has not been invalidated, it means that this page table entry has not been cleared by the TLB invalidate instruction at this level, which is consistent with the result returned by the walk cache. Therefore, it is necessary to jointly judge whether the entry to be invalidated is valid in combination with message.level.

[0077] It can be understood that when caching the entries to be invalidated in the above embodiments, it is also possible to determine whether the entry corresponding to the target virtual address is successfully cached according to the first signal, the second signal, and the third signal. That is, if the first signal and the second signal are both raised simultaneously within the target clock cycle, and the third signal is consistent with the level of the target page table, then the entry corresponding to the target virtual address is successfully cached.

[0078] In the embodiments of the present application, by determining whether the first signal and the second signal are both raised simultaneously within the target clock cycle, and whether the third signal is consistent with the level of the target page table, it is possible to accurately determine whether the entry to be invalidated is invalid, and then determine the situation of the TLB invalidation instruction, thereby ensuring the reliability of the verification result.

[0079] In some embodiments of the present application, when the target object is a translation cache unit, caching the entries to be invalidated includes:

[0080] Sequentially sending m second translation requests to the target object, where the m second translation requests respectively carry different virtual addresses, m is greater than the depth of the micro translation lookaside buffer, and m is less than or equal to the sum of the depths of the micro translation lookaside buffer and the main translation lookaside buffer;

[0081] Determining the entries corresponding to the virtual addresses in the m second translation requests as the entries to be invalidated.

[0082] It should be noted that the TLB invalidation instruction can act on the entries cached in the TLB when the TBU processes the translation request, so that the entries in the TLB become invalid. Therefore, for the case where the target object is the TBU or the object for caching the entries to be invalidated is the TLB, the characteristics of the TLB itself can be utilized to implement the caching of the entries to be invalidated. Among them, the TLB can include the UTLB and the MTLB, that is, the micro translation lookaside buffer and the main translation lookaside buffer, which will not be elaborated here.

[0083] When simultaneously verifying whether the TLB invalidation instruction can act on the entries in the UTLB and the MTLB, in order to fill the UTLB and the MTLB as soon as possible, translation requests carrying different virtual addresses can be sent to the target object. In some embodiments, m non-repeating virtual addresses can be generated, and then a translation request is generated for each virtual address, and finally the generated m translation requests are sent to the target object. As Figure 4 shown, during the process of sending the m translation requests, the UTLB is filled first, and then the MTLB is filled. It can be understood that the depths of the UTLB and the MTLB are determined by the verification environment or verification requirements. For example, the hardware structures of the UTLB and the MTLB provided by the verification environment determine their respective depths.

[0084] In some embodiments, in the case of continuously verifying TLB invalidation instructions multiple times, after each verification, all caches can be cleared to avoid interference with the next verification. As Figure 5 shown, it includes:

[0085] S501: Send m translation requests. Here, m is the same as m in the above embodiments and will not be elaborated here. The virtual addresses carried by the m translation requests do not have the same virtual address.

[0086] S502: Insert and trigger a TLB invalidation instruction for the entry to be invalidated.

[0087] S503: Check whether the entries to be invalidated in the UTLB and MTLB are invalidated.

[0088] S504: Clear all caches. For example, the SMMU_CR0 register and the SMMU_S_CR0 register can be modified to disable the SMMU; write 1 to the INV_ALL bit of the SMMU_S_INIT register and poll until it returns to 0. Generate an INV_ALL instruction to invalidate all caches; modify the SMMU_CR0 and SMMU_S_CR0 registers again to enable the SMMU.

[0089] In the embodiments of the present application, the entries to be invalidated can be cached through the UTLB and MTLB, so that it is possible to simultaneously verify whether the TLB invalidation instruction can act on the entries in the UTLB and MTLB.

[0090] In some embodiments of the present application, in the case where the target object is a translation cache unit, the first translation situation includes: the first number of times that the first signal and the second signal are simultaneously raised within the target clock cycle during the processing of a translation requests, the second number of times that the first signal and the second signal are simultaneously raised within the target clock cycle during the processing of b translation requests, the first signal indicates whether the look-up table request is valid, and the second signal indicates whether the look-up table hits; the a translation requests carry the virtual addresses corresponding to the entries to be invalidated in the micro translation look-aside buffer, and the b translation requests carry the virtual addresses corresponding to the entries to be invalidated in the main translation look-aside buffer;

[0091] Correspondingly, determining whether the entry to be invalidated is invalid based on the first translation situation includes:

[0092] Determine whether each entry to be invalidated in the micro translation look-aside buffer is invalid according to the first number of times, and determine whether each entry to be invalidated in the main translation look-aside buffer is invalid according to the second number of times.

[0093] It should be noted that when the target object is TBU, UTML and MTLB can be used to cache the entries to be invalidated. Further, during the process of TBU processing translation requests, it is usually first determined whether the translation request is valid, and if it is valid, a look-up table is performed in UTML and MTLB to find the entry corresponding to the virtual address in the translation request. If a page table is hit during the look-up table in UTML and MTLB. Then, it means that the entry corresponding to the virtual address in the translation request is still valid in UTML and MTLB. Otherwise, it can be regarded that the entry corresponding to the virtual address in the translation request has become invalid. This process is similar to the process of TCU processing translation requests, but the positions of the cache entries are different for the two, and there is no such third signal in the criterion for judging whether the entry is invalid here. In addition, regarding the first signal and the second signal, reference can be made to the embodiments of the above-mentioned TCU processing translation requests. And, regarding the situation where the first signal and the second signal are both raised during the target clock cycle, reference can be made to the relevant descriptions of the first signal and the second signal being both raised during the target clock cycle in the above-mentioned embodiments, which will not be elaborated here.

[0094] In this embodiment, sending a translation request carrying a target virtual address to a target object includes: sequentially sending a translation requests and b translation requests to the target object. The a translation requests carry the virtual addresses corresponding to the entries to be invalidated in the UTLB, and the b translation requests carry the virtual addresses corresponding to the entries to be invalidated in the MTLB. Among them, the process of the TBU processing each of the a translation requests is the same. For any one of the translation requests, if the first signal and the second signal are both raised within the target clock cycle, it indicates that the entry to be invalidated corresponding to this translation request is not invalidated. Otherwise, it is regarded that the entry to be invalidated corresponding to this translation request is invalidated. Since the number of entries to be invalidated in the UTLB is a, it is necessary to determine whether each entry to be invalidated in the UTLB is invalidated through the first number of times. For example, if the first number of times is equal to a times, then it can be determined that each entry to be invalidated in the UTLB is not invalidated, and the TLB invalidation instruction can be regarded as invalidated, that is, it does not take effect. Another example is that if the first number of times is equal to 0 times, then it can be determined that each entry to be invalidated in the UTLB is invalidated, and the TLB invalidation instruction can be regarded as not invalidated, that is, it works normally. Similarly, the process of the TBU processing each of the b translation requests is the same. For any one of the translation requests, if the first signal and the second signal are both raised within the target clock cycle, it indicates that the entry to be invalidated corresponding to this translation request is not invalidated. Otherwise, it is regarded that the entry to be invalidated corresponding to this translation request is invalidated. Since the number of entries to be invalidated in the MTLB is b, it is necessary to determine whether each entry to be invalidated in the MTLB is invalidated through the second number of times. For example, if the second number of times is greater than 0 times, then it can be determined that each entry to be invalidated in the MTLB is not invalidated, and the TLB invalidation instruction can be regarded as invalidated, that is, it does not take effect. Another example is that if the second number of times is equal to 0 times, then it can be determined that each entry to be invalidated in the MTLB is invalidated, and the TLB invalidation instruction can be regarded as not invalidated, that is, it works normally.

[0095] In some embodiments, through the above embodiment, m second translation requests are sequentially sent to the target object to cache the entries to be invalidated, and the sum of a and b is equal to m. That is to say, during the process of sending m second translation requests, when the TBU processes the first a translation requests, a entries to be invalidated will be cached in the UTLB; when the TBU processes the subsequent b translation requests, b entries to be invalidated will be cached in the MTLB. Correspondingly, sending a translation request carrying a target virtual address to the target object includes: sequentially sending m second translation requests to the target object.

[0096] In some embodiments, to simplify the process of sending a translation request carrying a target virtual address to a target object, only c translation requests and d translation requests may be sent, where c is less than a, and the c translation requests carry virtual addresses corresponding to some of the entries to be invalidated in the UTLB. d is less than b, and the d translation requests carry virtual addresses corresponding to some of the entries to be invalidated in the MTLB. Correspondingly, the process of determining whether each invalid entry is invalid is similar to the process of determining whether the entries to be invalidated in the UTLB and MTLB are invalid according to the first number and the second number, which will not be elaborated here.

[0097] In the embodiments of the present application, by the number of times the first signal and the second signal are both raised within a target clock cycle, it is possible to accurately determine whether the entries to be invalidated in the UTLB are invalid, and further determine the situation of the TLB invalidation instruction, thereby ensuring the reliability of the verification result.

[0098] In some embodiments of the present application, when the target object is a translation cache unit, caching the entries to be invalidated includes:

[0099] Sequentially sending m second translation requests to the target object, where the m second translation requests respectively carry different virtual addresses, m is greater than the depth of the micro translation lookaside buffer, and m is less than or equal to the sum of the depths of the micro translation lookaside buffer and the main translation lookaside buffer;

[0100] Determine the entries corresponding to the virtual addresses in the corresponding n second translation requests as the entries to be invalidated, where n is the difference obtained by subtracting the depth of the micro translation lookaside buffer from m, and the n second translation requests include: the last n second translation requests among the m second translation requests.

[0101] It should be noted that the process of sequentially sending m second translation requests to the target object is the same as the process of sequentially sending m second translation requests to the target object in the above embodiments. To avoid repetition, it will not be elaborated here. The TLB may include the UTLB and the MTLB. In this embodiment, only the entries to be invalidated in the MTLB may be verified, that is, to verify the effect of the TLB invalidation instruction on the cached entries in the MTLB. Therefore, for the n second translation requests, after caching the corresponding entries in the MTLB, send the n second translation requests to the target object again, and obtain the translation situation during the target object's processing of the n second translation requests, and then determine whether the cached entries in the MTLB are invalid based on the translation situation, thereby verifying the effect of the TLB invalidation instruction on the cached entries in the MTLB.

[0102] In some embodiments, it is also possible to only verify the entries to be invalidated in the UTLB, that is, to verify the effect of the TLB invalidation instruction on the cached entries in the UTLB. At this time, at least one third translation request can be sent to the target object, and then the entries cached by the UTLB are used as the entries to be invalidated. Then, at least one third translation request is sent again, and the translation situation during the processing of at least one third translation request by the TBU is used to determine whether the cached entries in the UTLB are invalidated, so as to verify the effect of the TLB invalidation instruction on the cached entries in the UTLB.

[0103] In the embodiments of the present application, the entries to be invalidated can be cached by the MTLB, so that the situation where the TLB invalidation instruction acts alone on the MTLB can be verified.

[0104] In some embodiments of the present application, the first translation situation includes: the third number of times that the first signal and the second signal are simultaneously raised within the target clock cycle during the processing of n translation requests, where the first signal indicates whether the look-up table request is valid, and the second signal indicates whether the look-up table hits; the n translation requests carry the virtual addresses corresponding to the entries to be invalidated in the main translation look-aside buffer.

[0105] Correspondingly, determining whether the entries to be invalidated are invalidated based on the first translation situation includes:

[0106] If the third number of times is equal to 0, it is determined that each of the entries to be invalidated in the main translation look-aside buffer is invalidated; if the third number of times is less than n, it is determined that each of the entries to be invalidated in the main translation look-aside buffer is not invalidated.

[0107] It should be noted that in the scenario where only the entries to be invalidated in the MTLB are verified, the situation of the entries to be invalidated in the MTLB can be determined through the specific value of the third number of times. Among them, when the third number of times is equal to 0, it can be regarded as the TLB invalidation instruction taking effect and successfully changing the targeted entry to an invalid state. When the third number of times is less than n, it can be regarded as determining that the TLB invalidation instruction fails and fails to successfully change the targeted entry to an invalid state.

[0108] Regarding the first signal and the second signal, reference can be made to the relevant descriptions of the first signal and the second signal in the above embodiments, which will not be elaborated here.

[0109] In the embodiments of the present application, by the number of times that the first signal and the second signal are simultaneously raised within the target clock cycle, it is possible to accurately determine whether the entries to be invalidated in the MTLB are invalidated, and then determine the situation of the TLB invalidation instruction, thereby ensuring the reliability of the verification result.

[0110] In some embodiments of the present application, the target instruction further includes: a synchronization instruction;

[0111] Triggering the target instruction includes:

[0112] Successively trigger a TLB invalidation instruction and a synchronization instruction for the entry to be invalidated.

[0113] It should be noted that the synchronization instruction is executed after the TLB invalidation instruction is executed, so as to ensure that the TLB invalidation instruction is executed completely. In some embodiments, when multiple TLB invalidation instructions need to be inserted, a synchronization instruction is inserted immediately after each TLB invalidation instruction. As Figure 6 shown, when inserting the TLB invalidation instruction and the synchronization instruction, the insertion of the instructions can be realized by means of a CONS pointer (consumer pointer) and a PROD pointer (producer pointer). Figure 6 The movement of the pointers is shown in

[0114] In the embodiment of the present application, after inserting the TLB invalidation instruction, a synchronization instruction will also be inserted to ensure that the TLB invalidation instruction is executed completely.

[0115] In some embodiments of the present application, the steps of inserting the target instruction include:

[0116] Obtain the base address of the command queue;

[0117] Determine the command queue address where the target instruction needs to be inserted according to the offset generated by the base address of the command queue and the number of target instructions;

[0118] Insert the target instruction according to the command queue address.

[0119] It should be noted that the command queue is used to store the commands that need to be executed. In this embodiment, the TLB invalidation instruction, as a command that needs to be executed, will be inserted into the command queue. The base address of the command queue is the starting address of the command queue. When the number of TLB invalidation instructions is multiple, when inserting the TLB invalidation instruction, the corresponding offset can be determined based on its number first, and then the TLB invalidation instruction can be inserted into the command queue according to its actual address and offset. In some embodiments, when the target instruction includes a TLB invalidation instruction and a synchronization instruction, the command queue addresses where each TLB invalidation instruction and each synchronization instruction need to be inserted will be determined according to the offset generated by the base address of the command queue and the number of each instruction in the target instruction; finally, each instruction will be inserted according to the determined command queue address.

[0120] In some embodiments, if the command queue is a non-secure command queue, that is, when the TLB invalidation instruction is issued from the non-secure command queue, the value read_data of the SMMU_CMDQ_CONS register can be read, and then the result of adding 1 to read_data is written into the SMMU_CMDQ_PROD register. Wait until the value of the SMMU_CMDQ_CONS register is successfully incremented by 1. At this time, a new TLB invalidation instruction is placed in the non-secure command queue. When reading and executing the TLB invalidation instruction from the non-secure command queue, the value of the SMMU_CMDQ_CONS register is incremented by 1 again and written into the SMMU_CMDQ_PROD register, and then a synchronization instruction CMD_SYNC is inserted to ensure that the TLB invalidation instruction is executed completely.

[0121] In other embodiments, if the command queue is a secure command queue, that is, when the invalidation instruction is issued from the secure command queue, the value read_data of the SMMU_S_CMDQ_CONS register is read, and the result of adding 1 to read_data is written into the SMMU_S_CMDQ_PROD register. Wait until the value of the SMMU_S_CMDQ_CONS register is successfully incremented by 1. At this time, a new TLB invalidation instruction is stored in the secure command queue. When the SMMU reads and executes the TLB invalidation instruction from the secure command queue, the value of the SMMU_S_CMDQ_CONS register is incremented by 1 again and written into the SMMU_S_CMDQ_PROD register, and then a synchronization instruction CMD_SYNC is inserted to ensure that the TLB invalidation instruction is executed completely.

[0122] In the embodiments of the present application, by inserting and triggering the target instruction through the command queue, the overall verification process is simplified.

[0123] To further improve the reliability of the verification result, in some embodiments of the present application, before caching the entries to be invalidated, the method further includes:

[0124] Sending translation requests carrying the same virtual address multiple times, and recording the changes in the first signal and the second signal;

[0125] Based on the change situation, determining the clock cycles when the first signal and the second signal are each pulled high;

[0126] Determining the duration between the two clock cycles when the pull-up change occurs as the target clock cycle.

[0127] Regarding the first signal and the second signal, reference may be made to the relevant descriptions of the first signal and the second signal in the foregoing embodiments, which will not be elaborated here. It should be noted that if the target clock cycle is too long or too short, the accuracy of the final verification result will be affected. Since the situation where the first signal and the second signal are both pulled high during testing is similar to the situation where the first signal and the second signal are both pulled high when verifying the TLB miss instruction, a reasonable duration is determined as the target clock cycle through testing. For example, the target clock cycle can be 20 clock cycles, but it is not limited thereto.

[0128] In the embodiments of the present application, determining the target clock cycle through testing can avoid the target clock cycle being too long or too short, thereby affecting the accuracy of the final verification result.

[0129] Exemplary Device

[0130] Some embodiments of the present application further provide a verification device for a translation lookaside buffer miss instruction, as Figure 7 shown. The verification device for the translation lookaside buffer miss instruction includes:

[0131] A cache module 701 for caching the entries to be invalidated;

[0132] An instruction module 702 for inserting and triggering a target instruction, where the target instruction includes: a TLB miss instruction for the entry to be invalidated;

[0133] A translation module 703 for sending a translation request carrying a target virtual address to a target object and obtaining a first translation situation during the process of the target object processing the translation request, where the target object includes: a translation cache unit or a translation control unit; the target virtual address includes: the virtual address corresponding to the entry to be invalidated;

[0134] An invalidation determination module 704 for determining whether the entry to be invalidated is invalid based on the first translation situation.

[0135] In some embodiments, when the target object is the translation control unit, the cache module 701 is specifically configured to:

[0136] Send at least two first translation requests to the target object in sequence, where the at least two first translation requests both carry the target virtual address;

[0137] Obtain a second translation situation during the process of the target object processing the target translation request, where the target translation request includes: at least one first translation request other than the first translation request sent for the first time;

[0138] When the second translation case indicates that the entry cache corresponding to the target virtual address is successful, determine the entry corresponding to the target virtual address as the entry to be invalidated.

[0139] In some embodiments, when the target object is the translation control unit, the first translation case includes: the change conditions of the first signal and the second signal within the target clock cycle, and the consistency between the third signal and the level of the target page table; wherein, the first signal indicates whether the look-up table request is valid, the second signal indicates whether the look-up table hits, the third signal indicates the page table level at the time of the request, and the target page table represents the last-level page table in the translation process.

[0140] The invalidation determination module 704 is specifically configured to determine that the entry to be invalidated is not invalidated if the first signal and the second signal are both raised within the target clock cycle and the third signal is consistent with the level of the target page table, otherwise determine that the entry to be invalidated is invalid.

[0141] In some embodiments, when the target object is the translation cache unit, the cache module 701 is specifically configured to:

[0142] Send m second translation requests to the target object in sequence, where the m second translation requests respectively carry different virtual addresses, m is greater than the depth of the micro translation look-aside buffer, and m is less than or equal to the sum of the depths of the micro translation look-aside buffer and the main translation look-aside buffer.

[0143] Determine the entries corresponding to the virtual addresses in the m second translation requests as the entries to be invalidated.

[0144] In some embodiments, when the target object is the translation cache unit, the first translation case includes: the first number of times the first signal and the second signal are both raised within the target clock cycle during the processing of a translation requests, and the second number of times the first signal and the second signal are both raised within the target clock cycle during the processing of b translation requests, where the first signal indicates whether the look-up table request is valid, and the second signal indicates whether the look-up table hits; the a translation requests carry the virtual addresses corresponding to the entries to be invalidated in the micro translation look-aside buffer, and the b translation requests carry the virtual addresses corresponding to the entries to be invalidated in the main translation look-aside buffer.

[0145] Correspondingly, the invalidation determination module 704 is specifically configured to determine whether each entry to be invalidated in the micro translation look-aside buffer is invalid according to the first number of times, and determine whether each entry to be invalidated in the main translation look-aside buffer is invalid according to the second number of times.

[0146] In some embodiments, when the target object is the translation cache unit, the cache module 701 is specifically configured to:

[0147] Send m second translation requests to the target object in sequence, where each of the m second translation requests carries a different virtual address, m is greater than the depth of the micro translation lookaside buffer, and m is less than or equal to the sum of the depths of the micro translation lookaside buffer and the main translation lookaside buffer;

[0148] Determine the entries corresponding to the virtual addresses in the n second translation requests as the entries to be invalidated, where n is the difference obtained by subtracting the depth of the micro translation lookaside buffer from m, and the n second translation requests include: the last n second translation requests among the m second translation requests.

[0149] In some embodiments, the first translation situation includes: the third number of times when the first signal and the second signal are both raised within the target clock cycle during the process of processing the n translation requests, the first signal indicates whether the look-up table request is valid, and the second signal indicates whether the look-up table hits; the n translation requests carry the virtual addresses corresponding to the entries to be invalidated in the main translation lookaside buffer;

[0150] Correspondingly, the invalidation determination module 704 is specifically configured to, if the third number of times is equal to 0, determine that each entry to be invalidated in the main translation lookaside buffer is invalid, and if the third number of times is less than n, determine that each entry to be invalidated in the main translation lookaside buffer is not invalid.

[0151] In some embodiments, the target instruction further includes: a synchronization instruction;

[0152] The instruction module 702 no longer triggers the target instruction including:

[0153] Trigger the TLB invalidation instruction and the synchronization instruction for the entry to be invalidated in sequence.

[0154] In some embodiments, the steps for the instruction module 702 to insert the target instruction include:

[0155] Obtain the base address of the command queue; determine the command queue address where the target instruction needs to be inserted according to the offset generated by the base address of the command queue and the number of target instructions; insert the target instruction according to the command queue address.

[0156] In some embodiments, the device further includes:

[0157] The clock cycle test module is used to send translation requests carrying the same virtual address multiple times and record the changes of the first signal and the second signal; based on the changes, determine the clock cycles when the first signal and the second signal respectively change to a high level; and determine the duration between the two clock cycles when the high-level change occurs as the target clock cycle.

[0158] The verification device for the translation lookaside buffer failure instruction provided in the embodiments of the present application belongs to the same inventive concept as the verification method for the translation lookaside buffer failure instruction provided in the above embodiments of the present application. For the technical details not described in detail in this embodiment, reference can be made to the specific processing content of the verification method for the translation lookaside buffer failure instruction provided in the above embodiments of the present application, which will not be elaborated here.

[0159] Exemplary Electronic Device

[0160] Another embodiment of the present application also proposes an electronic device, including a processor configured to execute the steps in the verification method for the translation lookaside buffer failure instruction according to various embodiments of the present application described in the above embodiments of the present application. Refer to Figure 8 As shown, an exemplary embodiment of the present application also provides an electronic device, including: a memory and a processor, the memory stores a computer program, and when the processor executes the computer program, it executes the steps in the verification method for the translation lookaside buffer failure instruction according to various embodiments of the present application described in the above embodiments of the present application.

[0161] The internal structure of the electronic device can be as Figure 8 As shown, the electronic device includes a processor, a memory, a network interface, and an input device connected through a system bus. Among them, the processor of the electronic device is used to provide computing and control capabilities. The memory of the electronic device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The network interface of the electronic device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, it performs the steps in the verification method for the translation lookaside buffer failure instruction according to various embodiments of the present application described in the above embodiments of the present application.

[0162] The processor may include a main processor, and may also include a baseband chip, a modem, etc.

[0163] The memory stores a program for executing the technical solution of the present invention, and may also store an operating system and other key services. Specifically, the program may include program code, and the program code includes computer operation instructions. More specifically, the memory may include a read-only memory (ROM), other types of static storage devices that can store static information and instructions, a random access memory (RAM), other types of dynamic storage devices that can store information and instructions, a disk memory, a flash memory, etc.

[0164] The processor may be a general-purpose processor, such as a general-purpose central processing unit (CPU), a microprocessor, etc., or may be an application-specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of the program of the present invention. It may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0165] The input device may include a device for receiving user input data and information, such as a keyboard, a mouse, a camera, a scanner, a light pen, a voice input device, a touch screen, a pedometer or a gravity sensor, etc.

[0166] The output device may include a device for allowing information to be output to the user, such as a display screen, a printer, a speaker, etc.

[0167] The communication interface may include a device of any transceiver type for communicating with other devices or communication networks, such as an Ethernet, a radio access network (RAN), a wireless local area network (WLAN), etc.

[0168] The processor executes the program stored in the memory and calls other devices, which can be used to implement each step of any one of the verification methods for translation lookaside buffer failure instructions provided in the above embodiments of the present application.

[0169] The electronic device may further include a display component and a voice component. The display component may be a liquid crystal display screen or an electronic ink display screen. The input device of the electronic device may be a touch layer covering the display component, or may be a button, a trackball or a touchpad provided on the housing of the electronic device, or may also be an external keyboard, a touchpad or a mouse, etc.

[0170] Those skilled in the art can understand, Figure 8The structure shown is only a block diagram of some structures related to the solution of this application, and does not constitute a limitation on the electronic device to which the solution of this application is applied. The specific electronic device may include more or fewer components than those shown in the figure, or combine some components, or have a different component arrangement.

[0171] Exemplary Computer Program Product and Storage Medium

[0172] In addition to the above methods and devices, the method for verifying the translation lookaside buffer invalidation instruction provided by the embodiments of this application may also be a computer program product, which includes computer program instructions. When the computer program instructions are run by a processor, the processor is caused to execute the steps in the method for verifying the translation lookaside buffer invalidation instruction according to various embodiments of this application described in the "Exemplary Method" section above of this application.

[0173] The computer program product can be written in any combination of one or more programming languages for the program code to perform the operations of the embodiments of this application. The programming languages include object-oriented programming languages such as Java, C++, etc., and also include conventional procedural programming languages such as the "C" language or similar programming languages. The program code can be executed entirely on the user computing device, partially on the user device, executed as an independent software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0174] In addition, the embodiments of this application also provide a computer-readable storage medium, on which a computer program is stored. The computer program is executed by a processor to perform the steps in the method for verifying the translation lookaside buffer invalidation instruction according to various embodiments of this application described in the "Exemplary Method" section above of this application.

[0175] Those of ordinary skill in the art can understand that all or part of the processes in the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, storage, database, or other medium used in the embodiments provided in this application can include non-volatile and / or volatile memories. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM), etc.

[0176] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this application.

[0177] The above-described embodiments merely represent several embodiments of this application. Their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the solutions provided by the embodiments of this application. It should be noted that for those of ordinary skill in the art, without departing from the concept of this application, several modifications and improvements can still be made, and these all belong to the protection scope of this application. Therefore, the protection scope of the patent of this application should be subject to the appended claims.

Claims

1. A verification method for a translation lookaside buffer (TLB) invalidation instruction, characterized in that, The method includes: Caching the entry to be invalidated; Inserting and triggering a target instruction, where the target instruction includes: a translation lookaside buffer (TLB) invalidation instruction for the entry to be invalidated; Sending a translation request carrying a target virtual address to a target object and obtaining a first translation situation during the target object's processing of the translation request, where the target object includes: a translation cache unit or a translation control unit; the target virtual address includes: the virtual address corresponding to the entry to be invalidated; Determining whether the entry to be invalidated is invalid based on the first translation situation.

2. The method according to claim 1, wherein When the target object is the translation control unit, caching the entry to be invalidated includes: Sequentially sending at least two first translation requests to the target object, where the at least two first translation requests both carry the target virtual address; Obtaining a second translation situation during the target object's processing of a target translation request, where the target translation request includes: at least one first translation request other than the first translation request sent first; When the second translation situation indicates that the entry corresponding to the target virtual address is successfully cached, determining the entry corresponding to the target virtual address as the entry to be invalidated.

3. The method according to claim 1, wherein When the target object is the translation control unit, the first translation situation includes: the change situation of a first signal and a second signal within a target clock cycle, and the consistency situation between a third signal and the level of a target page table; where the first signal indicates whether a look-up table request is valid, the second signal indicates whether a look-up table hit occurs, the third signal indicates the page table level at the time of the request, and the target page table represents the last-level page table during the translation process; Determining whether the entry to be invalidated is invalid based on the first translation situation includes: If the first signal and the second signal are both raised within the target clock cycle and the third signal is consistent with the level of the target page table, determining that the entry to be invalidated is not invalid; otherwise, determining that the entry to be invalidated is invalid.

4. The method according to claim 1, characterized in that When the target object is a translation cache unit, caching the entry to be invalidated includes: Sequentially sending m second translation requests to the target object, where the m second translation requests respectively carry different virtual addresses, m is greater than the depth of the micro translation lookaside buffer and less than or equal to the sum of the depths of the micro translation lookaside buffer and the main translation lookaside buffer; Determining the entry corresponding to the virtual address in the m second translation requests as the entry to be invalidated.

5. The method according to claim 1, characterized in that, When the target object is a translation cache unit, the first translation situation includes: the first number of times the first signal and the second signal are both raised within the target clock cycle during the processing of a translation requests, the second number of times the first signal and the second signal are both raised within the target clock cycle during the processing of b translation requests, the first signal indicates whether a look-up table request is valid, the second signal indicates whether a look-up table hit occurs; the a translation requests carry the virtual addresses corresponding to the entries to be invalidated in the micro translation lookaside buffer, and the b translation requests carry the virtual addresses corresponding to the entries to be invalidated in the main translation lookaside buffer; Correspondingly, determining whether the entry to be invalidated is invalid based on the first translation situation includes: Determining whether each entry to be invalidated in the microtranslation lookaside buffer is invalid according to the first number of times, and determining whether each entry to be invalidated in the main translation lookaside buffer is invalid according to the second number of times.

6. The method according to claim 1, wherein When the target object is a translation cache unit, caching the entry to be invalidated includes: Sequentially sending m second translation requests to the target object, where the m second translation requests carry different virtual addresses respectively, m is greater than the depth of the microtranslation lookaside buffer, and m is less than or equal to the sum of the depths of the microtranslation lookaside buffer and the main translation lookaside buffer; Determining the entries corresponding to the virtual addresses in the n second translation requests as the entries to be invalidated, where n is the difference obtained by subtracting the depth of the microtranslation lookaside buffer from m, and the n second translation requests include: the last n second translation requests among the m second translation requests.

7. The method according to claim 6, wherein The first translation situation includes: the third number of times when the first signal and the second signal are both raised within the target clock cycle during the process of processing the n translation requests, the first signal indicating whether the lookup request is valid, and the second signal indicating whether the lookup hits; the n translation requests carry the virtual addresses corresponding to the entries to be invalidated in the main translation lookaside buffer; Correspondingly, determining whether the entry to be invalidated is invalid based on the first translation situation includes: If the third number of times is equal to 0, determining that each entry to be invalidated in the main translation lookaside buffer is invalid, and if the third number of times is less than n, determining that each entry to be invalidated in the main translation lookaside buffer is not invalid.

8. The method according to any one of claims 1-7, characterized in that, The target instruction further includes: a synchronization instruction; The triggering target instruction includes: Sequentially triggering the TLB invalidation instruction and the synchronization instruction for the entry to be invalidated.

9. The method according to any one of claims 1-7, characterized in that, The step of inserting the target instruction includes: Obtaining the base address of the command queue; Determining the command queue address where the target instruction needs to be inserted according to the offset generated by the base address of the command queue and the number of the target instructions; Inserting the target instruction according to the command queue address.

10. The method according to claim 3 or 5 or 7, characterized in that Before caching the entry to be invalidated, the method further includes: Sending translation requests carrying the same virtual address multiple times, and recording the change situations of the first signal and the second signal; Based on the change situations, determining the clock cycles when the first signal and the second signal are each raised; Determining the duration between the two clock cycles when the raising changes occur as the target clock cycle.

11. An electronic device, characterized in that, Including a processor, the processor is configured to execute the verification method of the translation lookaside buffer invalidation instruction according to any one of claims 1 to 10.

12. A computer program product, characterized in that, A computer program is stored on the computer program product, and when the computer program is executed by the processor, the verification method of the translation lookaside buffer invalidation instruction according to any one of claims 1 to 10 is implemented.

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