Communication method of multi-core system and multi-core system

Abstract

The invention aims to provide a communication method of a multi-core system and the multi-core system, and relates to the technical field of computers. The method applied to the Mailbox hardware module in the multi-core system comprises the following steps: receiving an operation configuration instruction of a processor core to the Mailbox hardware module; under the condition that an interrupt trigger signal of the processor core corresponding to the source address is received, sending an interrupt request signal to the processor core corresponding to the destination address according to a communication channel expected to be used so as to transmit the data to be sent until a first preset condition is met, and sending a source interrupt signal to the processor core corresponding to the source address; the first preset condition is that the communication channels of the mailbox source registers recording the source addresses are all used, and the destination addresses recorded by the mailbox target registers of the communication channels are all transmitted. Therefore, the communication concurrency and throughput of the multi-core system can be improved. And meanwhile, the communication reliability of the multi-core system can be improved.

Description

Technical Field

[0001] This application relates to the field of computer technologies, and in particular, to a communication method for a multi-core system and a multi-core system. Background Art

[0002] A multi-core system refers to a system in which multiple different types of processor cores are integrated on a single chip. These processor cores may adopt different extended instruction sets and have different performance characteristics and power consumption requirements. Since multiple different types of processor cores are integrated in the multi-core system, efficient data communication and collaborative work are required between these processor cores to ensure the performance and stability of the multi-core system. Therefore, the communication mechanism between the processor cores of the multi-core system is crucial. In related technologies, when a processor core sends data to be sent to multiple other processor cores, the Mailbox hardware module needs to be reconfigured with operating configuration instructions each time; or, when a processor core sends data to be sent to the same other processor core multiple times, the Mailbox hardware module also needs to be reconfigured with operating configuration instructions each time, resulting in poor data transmission performance in the communication of the multi-core system. Summary of the Invention

[0003] The purpose of the embodiments of this application is to provide a communication method for a multi-core system and a multi-core system, so as to solve the problem of poor data transmission performance between different processor cores of the multi-core system existing in related technologies.

[0004] The embodiments of this application provide a communication method for a multi-core system, which is applied to the Mailbox hardware module in the multi-core system. The multi-core system further includes multiple processor cores; the Mailbox hardware module includes multiple communication channels; each of the communication channels is respectively provided with a mailbox destination register and a mailbox source register; the method includes: receiving an operating configuration instruction of the Mailbox hardware module by the processor core; the operating configuration instruction is used to set a destination address in the mailbox destination register of the communication channel to be used, and set a source address in the mailbox source register of the communication channel to be used; the destination address is the address of the processor core that receives the data to be sent; the source address is the address of the processor core that sends the data to be sent; in the case of receiving an interrupt trigger signal of the processor core corresponding to the source address, sending an interrupt request signal to the processor core corresponding to the destination address according to the communication channel to be used to transmit the data to be sent until a first preset condition is met, and sending a source interrupt signal to the processor core corresponding to the source address; the first preset condition is that all communication channels of the mailbox source register recording the source address have been used, and all destination addresses recorded in the mailbox destination register of this communication channel have been transmitted.

[0005] In the above implementation process, by setting mailbox destination registers and mailbox source registers in each communication channel of the Mailbox hardware module, during the data transfer in the multi-core system, it is possible to achieve that the processor core only sets the operation configuration instruction for the Mailbox hardware module once, send data to multiple other processor cores, or the processor core only sets the operation configuration instruction for the Mailbox hardware module once and can send the data to be sent to the same other processor core multiple times. In this way, the concurrency and throughput of the communication in the multi-core system can be improved. At the same time, after the sending is completed, the Mailbox hardware module sends a source interrupt signal to the processor core corresponding to the source address, enabling the processor core corresponding to the source address to understand the situation of other processor cores receiving the data to be sent, and improving the reliability of the communication in the multi-core system.

[0006] Furthermore, the operation configuration instruction further includes: setting the transmission mode of the communication channel expected to be used; sending an interrupt request signal to the processor core corresponding to the destination address according to the communication channel expected to be used to transmit the data to be sent until a first preset condition is met, including: for the communication channel that meets the second preset condition, performing a first preset operation on the processor core corresponding to the destination address recorded in the mailbox destination register of this communication channel; the first preset operation includes sending the interrupt request signal to the processor core corresponding to the destination address to transmit the data to be sent; the second preset condition is that the transmission mode of the communication channel is the auto-response mode and the source address is recorded in the mailbox source register of the communication channel; wherein, when the first preset operation is executed on the processor cores corresponding to the destination addresses of all communication channels that meet the second preset condition, it is confirmed that the first preset condition is met.

[0007] In the above implementation process, for communication channels with the same source address set and the transmission mode being the auto-response mode, continuously send interrupt request signals to the processor cores corresponding to different destination addresses in this communication channel until the processor cores corresponding to all destination addresses are triggered by interrupts. In this way, when the processor core only sets the operation configuration instruction for the Mailbox hardware module once, it is possible to achieve the transmission to multiple different other processor cores, reduce redundant operations, and reduce the operating pressure of the multi-core system.

[0008] Further, performing a first preset operation on the processor core corresponding to the destination address recorded in the mailbox target register of the communication channel includes: repeatedly performing the first preset operation on the processor core corresponding to the destination address currently located at the first position in the mailbox target register, and receiving a clear instruction from this processor core, and clearing the destination address located at the first position in the mailbox target register based on the clear instruction until the destination address is not stored in the mailbox target register.

[0009] In the above implementation process, each time the first preset operation is performed on the processor core corresponding to the destination address, the processor core corresponding to this destination address is cleared in the mailbox target register. In this way, it is convenient to check which processor cores corresponding to the destination addresses have not performed the first preset operation, and it is convenient to manage the processor cores corresponding to the destination addresses that have not performed the first preset operation.

[0010] Further, the operation configuration instruction further includes: setting the transmission mode of the communication channel to be used; sending an interrupt request signal to the processor core corresponding to the destination address according to the communication channel to be used to transmit the data to be sent until a first preset condition is met, including: performing a second preset operation on all communication channels that meet a third preset condition; the second preset operation includes sending the interrupt request signal to the processor core corresponding to the destination address recorded in the mailbox target register of this communication channel to transmit the data to be sent; the third preset condition is that the transmission mode of the communication channel is the link mode, and the source address is recorded in the mailbox source register of this communication channel; wherein, when the second preset operation is performed on all communication channels that meet the third preset condition, it is confirmed that the first preset condition is met.

[0011] In the above implementation process, for multiple communication channels with the same set source address, the same set destination address, and the transmission mode being the link mode. At this time, the multiple communication channels are essentially all performing data transmission for the same set of processor cores, that is, it is possible to achieve multiple transmissions of the data to be sent from one processor core to the same other processor core with only one setting of the operation configuration instruction for the Mailbox hardware module by the processor core, which can reduce redundant operations and reduce the operating pressure of the multi-core system.

[0012] Further, performing the second preset operation on the communication channels that meet the third preset condition includes: if the transmission mode of the communication channel is the link mode, performing the second preset operation on this communication channel and the adjacent channel until the transmission mode of the adjacent channel is the normal mode; the adjacent channel is the communication channel adjacent to this communication channel and with a channel number greater than the channel number of this communication channel.

[0013] In the above implementation process, by continuously performing a second preset operation on the communication channel with the link mode of the transmission mode until the transmission mode of the adjacent channel is the normal mode. At this time, the communication channels are actually utilized for transmission in the order of the channel numbers, which is convenient for the management of the communication channels.

[0014] Further, the processor core includes a RISC-V core; each of the RISC-V cores stores the corresponding relationship between the base address, the destination interrupt number, the source interrupt number, and the interrupt function; sending an interrupt request signal to the processor core corresponding to the destination address to transmit the data to be sent includes: sending an interrupt request signal to the processor core corresponding to the destination address to trigger the processor core to perform a third preset operation; the third preset operation includes obtaining the destination interrupt number of the processor core executing the third preset operation and the source interrupt number of the processor core generating the interrupt trigger signal, looking up the interrupt function according to the preset base address, the destination interrupt number, and the source interrupt number, executing the interrupt function and reading the data to be sent; the interrupt function is used to respond to the processor core generating the interrupt trigger signal.

[0015] In the above implementation process, in a RISC-V multi-core system, the RISC-V core can obtain the corresponding interrupt function by querying the interrupt number to respond to the interrupt. When adding or modifying the interrupt handling subsequently, only the mapping between the interrupt number and the ISR (Interrupt Service Routine) needs to be registered / unregistered, without modifying the interrupt distribution logic, which is convenient for expansion and improves the flexibility and configurability of the multi-core system.

[0016] An embodiment of the present application provides a communication method for a multi-core system, which is applied to any one of the processor cores in the multi-core system. The multi-core system further includes a Mailbox hardware module; the Mailbox hardware module includes a plurality of communication channels; the method includes: obtaining a destination address and a communication channel to be used; setting the destination address in the mailbox destination register of the communication channel to be used, and setting the source address in the mailbox source register of the communication channel to be used; the destination address is the address of the processor core that receives the data to be sent; the source address is the address of the processor core that sends the data to be sent; sending an interrupt trigger signal to trigger the Mailbox hardware module to send an interrupt request signal to the processor core corresponding to the destination address according to the communication channel to be used to transmit the data to be sent until a first preset condition is met, and receiving the source interrupt signal returned by the Mailbox hardware module.

[0017] In the above embodiments, the destination address is set in the mailbox destination register of the communication channel expected to be used, and the source address is set in the mailbox source register of the communication channel expected to be used. That is, when configuring, multiple communication channels for transmitting data to be sent are indicated, as well as the destination address for transmitting the data to be sent. Thereby, it is convenient for the subsequent Mailbox hardware module to be able to send data to multiple other processor cores or send the data to be sent to the same other processor core multiple times when running the configuration instruction once after being configured. Thus, the concurrency and throughput of communication in the multi-core system can be improved. At the same time, by receiving the source interrupt signal sent by the Mailbox hardware module to the processor core corresponding to the source address, the processor core corresponding to the source address can understand the situation of other processor cores receiving the data to be sent, improving the reliability of communication in the multi-core system.

[0018] Further, the communication channel expected to be used is obtained by the following method: determining the number of channels according to the data volume of the data to be sent; determining the communication channel expected to be used according to the number of channels and the hardware semaphore of each communication channel.

[0019] In the above embodiments, considering that the data volume that each communication channel can withstand is limited, when the data volume of the data to be sent exceeds the data volume that a single communication channel can withstand, a single communication channel cannot complete the transmission of the data to be sent. Therefore, determining the number of channels according to the data volume of the data to be sent can enable the subsequent configuration of running the configuration instruction once to complete the transmission of the data to be sent, improving the efficiency of transmitting the data to be sent. At the same time, through the hardware semaphore of the communication channel, it can be reflected whether the communication channel is idle, and since the hardware semaphore can restrict other processor cores from accessing the Mailbox hardware module, the communication channel expected to be used determined by the hardware semaphore will not affect the interaction between other processor cores, increasing the reliability of the interaction between multiple processor cores in the multi-core system.

[0020] Further, the communication method further includes: obtaining the data to be sent; writing the data to be sent to a storage location accessible by the processor core corresponding to the destination address.

[0021] In the above embodiments, by writing the data to be sent to a storage location accessible by the processor core corresponding to the destination address, the operation of moving the data to be sent is reduced, making it more convenient for the processor core corresponding to the destination address to obtain the data to be sent.

[0022] Further, the data to be sent includes: service type; the communication method further includes: transmitting the data to be sent to the service layer corresponding to the service type.

[0023] In the above-described embodiment, by directly carrying the service type in the data to be sent, when the processor core receives the data to be sent, it can directly read the service type to which the data to be sent belongs, and directly send the data to be sent to the corresponding service layer. This can reduce the steps of data analysis and improve the efficiency of data transmission.

[0024] Further, the processor core includes a RISC-V core; each RISC-V core stores the correspondence between a base address, a destination interrupt number, a source interrupt number, and an interrupt function; the method further includes: when receiving the interrupt request signal, obtaining the carried destination interrupt number and the source interrupt number of the processor core that generates the interrupt trigger signal; looking up the interrupt function according to a preset base address, the destination interrupt number, and the source interrupt number; the interrupt function is used to respond to the processor core that generates the interrupt trigger signal; executing the interrupt function and reading the data to be sent.

[0025] In the above-described embodiment, in a RISC-V multi-core system, the RISC-V core can obtain the corresponding interrupt function by querying the interrupt number to respond to the interrupt. When adding or modifying interrupt handling subsequently, only the mapping between the interrupt number and the interrupt service program needs to be registered / unregistered, without modifying the interrupt distribution logic, which is convenient for expansion and improves the flexibility and configurability of the RISC-V multi-core system.

[0026] This application provides a multi-core system, including: a processor core, configured to obtain a destination address and a communication channel to be used; set the destination address in the mailbox destination register of the communication channel to be used, and set the source address in the mailbox source register of the communication channel to be used; send an interrupt trigger signal to the Mailbox hardware module; the destination address is the address of the processor core that receives the data to be sent; the source address is the address of the processor core that sends the data to be sent; the Mailbox hardware module is configured to send an interrupt request signal to the processor core corresponding to the destination address according to the communication channel to be used to transmit the data to be sent until a first preset condition is met, and send a source interrupt signal to the processor core corresponding to the source address.

[0027] Further, the processor core is further configured to set the transmission mode of the communication channel to be used; specifically, the Mailbox hardware module is configured to send an interrupt request signal to the processor core corresponding to the destination address through the communication channel to be used to transmit the data to be sent until a first preset condition is met: for the communication channel that meets the second preset condition, perform a first preset operation on the processor core corresponding to the destination address recorded in the mailbox destination register of the communication channel; the first preset operation includes sending the interrupt request signal to the processor core corresponding to the destination address to transmit the data to be sent; the second preset condition is that the transmission mode of the communication channel is the auto-response mode, and the source address is recorded in the mailbox source register of the communication channel; wherein, when the first preset operation is performed on the processor cores corresponding to the destination addresses of all the communication channels that meet the second preset condition, it is confirmed that the first preset condition is met.

[0028] Specifically, the Mailbox hardware module is configured to perform the first preset operation on the processor core corresponding to the destination address recorded in the mailbox destination register of the communication channel in the following manner: repeatedly perform the first preset operation on the processor core corresponding to the destination address currently located at the first position in the mailbox destination register, and receive the clear instruction of this processor core, and clear the destination address located at the first position in the mailbox destination register based on the clear instruction until no destination address is stored in the mailbox destination register.

[0029] Further, the processor core is further configured to set the transmission mode of the communication channel to be used; specifically, the Mailbox hardware module is configured to send an interrupt request signal to the processor core corresponding to the destination address through the communication channel to be used to transmit the data to be sent until a first preset condition is met: perform a second preset operation on all the communication channels that meet the third preset condition; the second preset operation includes sending the interrupt request signal to the processor core corresponding to the destination address recorded in the mailbox destination register of this communication channel to transmit the data to be sent; the third preset condition is that the transmission mode of the communication channel is the linked mode, and the source address is recorded in the mailbox source register of this communication channel; wherein, when the second preset operation is performed on all the communication channels that meet the third preset condition, it is confirmed that the first preset condition is met.

[0030] Further, the Mailbox hardware module is specifically configured to perform a second preset operation on the communication channel that meets the third preset condition in the following manner: if the transmission mode of the communication channel is the link mode, perform the second preset operation on this communication channel and the adjacent channel until the transmission mode of the adjacent channel is the normal mode; the adjacent channel is the communication channel that is adjacent to the communication channel and has a channel sequence number greater than that of this communication channel.

[0031] Further, the processor core is further configured to: obtain the data to be sent; write the data to be sent to a storage location accessible by the processor core corresponding to the destination address.

[0032] Further, the data to be sent includes: service type; the processor core is further configured to: transmit the data to be sent to the service layer corresponding to the service type.

[0033] Further, the processor core includes a RISC-V core; each RISC-V core stores the corresponding relationship between the base address, the destination interrupt number, the source interrupt number, and the interrupt function; the processor core is further configured to: in the case of receiving the interrupt request signal, obtain the carried destination interrupt number and the source interrupt number of the processor core that generates the interrupt trigger signal; search for the interrupt function according to the preset base address, the destination interrupt number, and the source interrupt number; the interrupt function is used to respond to the processor core that generates the interrupt trigger signal; execute the interrupt function and read the data to be sent. Description of the Drawings

[0034] To more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required to be used in the embodiments of the present application. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation of the scope. For those of ordinary skill in the art, without creative efforts, other relevant drawings can be obtained based on these drawings.

[0035] Figure 1 It is a schematic diagram of a multi-core system provided by an embodiment of the present application;

[0036] Figure 2 It is a schematic diagram of a structural block diagram of a Mailbox hardware module provided by an embodiment of the present application;

[0037] Figure 3 It is a schematic diagram of a preset transmission data format provided by an embodiment of the present application;

[0038] Figure 4 It is a schematic diagram of a data transmission process for a single processor core provided by an embodiment of the present application;

[0039] Figure 5 Schematic diagram of a simplified model of VirtIO provided by an embodiment of the present application;

[0040] Figure 6 Schematic diagram of a data transmission process for two processor cores provided by an embodiment of the present application;

[0041] Figure 7 Flowchart of a communication method for a multi-core system provided by an embodiment of the present application;

[0042] Figure 8 Flowchart of another communication method for a multi-core system provided by an embodiment of the present application;

[0043] Figure 9 Flowchart of yet another communication method for a multi-core system provided by an embodiment of the present application.

[0044] Reference numerals:

[0045] 1: Processor core; 2: Mailbox hardware module; 3: Media access control layer; 4: Physical layer; 5: Transport layer; 6: Back-end device; 7: Front-end driver. Detailed implementation manners

[0046] In order to make the objectives, technical solutions and advantages of the embodiments of the present application clearer and more understandable, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0047] Embodiment 1:

[0048] Please refer to Figure 1 , Figure 1 A multi-core system provided by an embodiment of the present application, including: a processor core 1 and a Mailbox hardware module 2. Among them, the processor core 1 is used to obtain a destination address and a communication channel to be used; set the destination address in the mailbox target register of the communication channel to be used, and set the source address in the mailbox source register of the communication channel to be used; send an interrupt trigger signal to the Mailbox hardware module 2; the Mailbox hardware module 2 is used to send an interrupt request signal to the processor core 1 corresponding to the destination address according to the communication channel to be used to transmit the data to be sent until a first preset condition is met, and send a source interrupt signal to the processor core 1 corresponding to the source address.

[0049] Among them, the destination address is the address of the processor core 1 that receives the data to be sent; the source address is the address of the processor core 1 that sends the data to be sent.

[0050] Among them, the first preset condition is that all communication channels of the mailbox source register recording the source address are used, and the destination addresses recorded in the mailbox destination registers of these communication channels have all been transmitted.

[0051] In this way, during the process of transmitting the data to be sent, there are usually two scenarios. The first scenario: there is a situation where the same data to be sent needs to be sent to multiple processor cores. At this time, the addresses of multiple processor cores that need to receive the data to be sent are recorded in the mailbox destination register of the same communication channel, that is, multiple destination addresses are recorded in the mailbox destination register of the same communication channel. The second scenario: the amount of data to be sent is too large, and it is impossible to completely transmit the data to be sent using a single communication channel. At this time, multiple communication channels need to be used to transmit the data to be sent, that is, the same destination address is recorded in the mailbox destination registers of multiple communication channels, and the same source address is recorded in the mailbox source registers of these multiple communication channels. In both scenarios, it is necessary to ensure that all communication channels of the mailbox source register recording the source address are used, and the destination addresses recorded in the mailbox destination registers of these communication channels have all been transmitted in order to complete the transmission of the data to be sent. Therefore, by setting the above first preset condition, the data to be sent can be completely transmitted to all processor cores that need to receive it, and there is no need to reconfigure the running configuration instructions in the middle, which can improve the concurrency and throughput of communication in the multi-core system.

[0052] In some examples, as Figure 2 shown, Figure 2 is the structural block diagram of the Mailbox hardware module. As Figure 2 shown, the Mailbox hardware module includes a hardware semaphore module (Semaphore), an interrupt generation module (Interrupt Generation), a control logic module (Control Logic), an AXI (a bus protocol) bus interface, and multiple communication channels. For each communication channel, a mailbox destination register (Destination REG), a mailbox source register (Source REG), a mask register (MaskREG), a mode register (Mode REG), and an interrupt trigger register (SendREG) can be set. Optionally, a storage register (FIFO REG) can also be set for each communication channel.

[0053] The mailbox source register is used to set the source address and the communication channel expected to be used. The mailbox destination register is used to set the destination address. The mask register is used to record whether to mask the interrupt generated by the communication channel. The storage register is used to store the data to be sent. The hardware semaphore module is used to record the hardware semaphore, and through the hardware semaphore, it can be reflected whether the communication channel is being used.

[0054] The interrupt generation module is used to generate source interrupts and destination interrupts. Among them, the Mailbox hardware module is used to trigger an interrupt to the processor core corresponding to the source address, which is called a source interrupt. The Mailbox hardware module is used to trigger an interrupt to the processor core corresponding to the destination address, which is called a destination interrupt.

[0055] The mode register is used to record the transmission mode of the communication channel. Among them, the transmission modes include: link mode, auto-response mode, and normal mode.

[0056] The auto-response mode is a mode in which one processor core transfers data to multiple other processor cores. In this mode, usually a desired communication channel is used, and multiple destination addresses are recorded in the mailbox destination register of the desired communication channel, which is beneficial for sending the same data to be sent to multiple other processor cores.

[0057] The link mode is a mode in which one processor core transfers data to another processor core multiple times. In this mode, usually multiple desired communication channels are used, the same destination address is recorded in the mailbox destination register of each desired communication channel, and the same source address is recorded in the mailbox source register of each desired communication channel. It is convenient to send the data to be sent to the same other processor core multiple times.

[0058] The normal mode is the transmission mode of the processor core in the prior art, that is, each time the processor core sends data, it is necessary to reconfigure the Mailbox hardware module to run the configuration instruction.

[0059] In some embodiments, the processor core 1 is used to: obtain the data to be sent; write the data to be sent to a storage location accessible by the processor core corresponding to the destination address.

[0060] Among them, the storage location accessible by the processor core corresponding to the destination address, for example: shared memory, storage register, etc.

[0061] Among them, the data to be sent can be data accessible by the processor core. For example: the processor core is used to manage a preset peripheral device, and the data of the preset peripheral device can be obtained as the data to be sent.

[0062] Exemplarily, assume a preset peripheral device, for example: RTC (Real Time Clock), UART (Universal Asynchronous Receiver-Transmitter), etc. The processor core can obtain the clock frequency of the real-time clock as the data to be sent, and the processor core can also obtain the baud rate of the universal asynchronous receiver-transmitter as the data to be sent.

[0063] In the above embodiments, writing the data to be sent to a storage location accessible by the processor core corresponding to the destination address may be: packing the data to be sent according to a preset data transmission format, and writing the packed data to a storage location accessible by the processor core corresponding to the destination address.

[0064] Among them, the preset data transmission format includes a service type.

[0065] Exemplarily, as shown in Figure 3 , the preset data transmission format may include: struct icic_header_msg (inter-core interrupt message header), chl_status (channel status), transfer_type (transmission type), packet_length (length of the entire data packet), payload[](parameters to be carried by the command). Among them, struct icic_header_msg includes: service_type (service type) and command_id (specific command supported by the service type). service_type represents the service type. command_id represents the specific command supported by the service type. chl_status represents the channel status, that is, whether the communication channel currently used for transmission is idle. transfer_type represents the transmission type, that is, sending data or receiving data. packet_length represents the length of the entire data packet, that is, the length of the data to be sent after being packed. payload[] represents the parameters to be carried by the command referred to by command_id. payload[] is a variable-length array, aiming to facilitate compatibility with different commands.

[0066] In this way, including the service type in the preset data transmission format facilitates the processor core receiving the data to be sent to directly transmit the data to be sent to the service layer corresponding to the service type according to the service type, reducing the data analysis process of the processor core receiving the data to be sent, thereby accelerating the data transmission efficiency of the processor core receiving the data to be sent.

[0067] In some embodiments, the processor core 1 is used to obtain the destination address in the following manner: searching for the destination address corresponding to the service type of the data to be sent in a preset address database. The preset address database stores the correspondence between the service type of the data to be sent and the destination address.

[0068] In other embodiments, the processor core 1 may also receive a destination address selection instruction and obtain the destination address based on the destination address selection instruction. Among them, the destination address selection instruction may be input by the user in the multi-core system.

[0069] In some embodiments, the processor core 1 is used to obtain the communication channel to be used as follows: determine the number of channels according to the data volume of the data to be sent; determine the communication channel to be used according to the number of channels and the hardware semaphore of each communication channel.

[0070] In an alternative manner of the above embodiment, determining the number of channels according to the data volume of the data to be sent may be: calculate the data volume of the data to be sent divided by the maximum transmission volume of the communication channel to obtain the alternative number of channels; round up the alternative number of channels to obtain the number of channels.

[0071] Wherein, the maximum transmission volume of the communication channel is the maximum data volume that a single communication channel can bear, for example: 128 bytes.

[0072] In another alternative manner of the above embodiment, determining the number of channels according to the data volume of the data to be sent may be: look up the number of channels corresponding to the data volume of the data to be sent in a preset number database. The preset number database stores the correspondence between the data volume of the data to be sent and the number of channels.

[0073] In some embodiments, the communication channel to be used can be determined according to the number of channels and the hardware semaphore of each communication channel in the following way: select the communication channels with the hardware semaphore indicating idle of a preset number in ascending order of the channel number. Wherein, the preset number is equal to the number of channels.

[0074] In other embodiments, the communication channel to be used can be determined according to the number of channels and the hardware semaphore of each communication channel in the following way: randomly select the communication channels with the hardware semaphore indicating idle of a preset number.

[0075] In some embodiments, the processor core 1 may write the destination address in the mailbox destination register of the communication channel to be used, so as to complete the setting of the destination address. The processor core 1 may write the source address in the mailbox source register of the communication channel to be used to complete the setting of the source address.

[0076] In some embodiments, after the processor core 1 sets the destination address and the source address in the communication channel to be used, it may also make the hardware semaphore of the communication channel to be used indicate busy.

[0077] Optionally, the processor core 1 may also write the transmission mode of the communication channel to be used in the mode register of the communication channel to be used.

[0078] Exemplarily, specific instructions can be used to represent different transmission modes, for example: 0x02 represents the auto-response mode; 0x03 represents the link mode.

[0079] Optionally, the processor core 1 can also write an instruction in the mask register of the communication channel to be used to indicate whether to mask the interrupt signal generated by the communication channel.

[0080] Exemplarily, specific instructions can be used to represent different transmission modes. For example, 0x04 represents not masking the interrupt signal generated by the communication channel; 0x04 represents masking the interrupt signal generated by the communication channel.

[0081] In some embodiments, the interrupt trigger signal is a signal used to indicate that the Mailbox hardware module 2 generates an interrupt to the processor core 1 corresponding to the destination address.

[0082] Exemplarily, the processor core sends an interrupt trigger signal to the Mailbox hardware module, that is, the processor core writes the set instruction into the corresponding interrupt trigger register in the Mailbox hardware module. For example: the processor core writes 0x01 into the interrupt trigger register of the communication channel to be used. The Mailbox hardware module knows that 0x01 has been written into the interrupt trigger register, that is, it receives the interrupt trigger signal sent by the processor core.

[0083] In some embodiments, when sending a source interrupt signal to the processor core 1 corresponding to the source address, that is, triggering an interrupt to the processor core 1 corresponding to the source address, it is the signal received by the processor core 1 corresponding to the source address.

[0084] In one example, if there is a storage register set in the communication channel, the processor core 1 can directly write the data to be sent into the storage register of the communication channel to be used. Then the processor core 1 calls the Mailbox hardware module 2 to implement two-way communication with other processor cores 1.

[0085] In another example, as shown in Figure 4 For a single processor core 1, if this processor core 1 needs to transmit the data to be sent to other processor cores 1, it may need to go through the following process: first hand over the data to be sent to the transport layer 5 for processing, and the transport layer 5 then transmits the data to be sent to the media access control layer 3. When the data to be sent of the transport layer 5 is filled in the media access control layer 3, the media access control layer 3 will call the physical layer 4 to implement two-way communication with other processor cores 1. Among them, the Mailbox hardware module 2 is set in the physical layer 4.

[0086] Among them, two processor cores can communicate using RPMsg-Lite (a lightweight inter-core communication protocol). The VirtQueue (a data queue) mechanism can be adopted in the media access control layer for data transmission.

[0087] Among them, there are three communication mechanisms in RPMsg-Lite, which are exemplified by two processor cores, such as CoreA and Core B.

[0088] The first one: CoreA uses the copy mechanism to copy the private data of the application layer to the share memory, and sends data to Core B through the share memory and the Mailbox hardware module. Core B uses the nocopy mechanism to expose the address of the received data to the application layer, and then Core B calls the release interface to release the received data.

[0089] The second one: Core B allocates a transmission buffer in the shared memory, fills it with data, and finally sends the data using the nocopy mechanism. After CoreA receives the data, it uses the copy mechanism to copy the data in the shared memory to the application layer cache.

[0090] The third one: Both Core B and CoreA use the nocopy mechanism for data sending and receiving operations. This is the most efficient transmission method because it does not involve copying data from the shared memory to the application layer cache, but directly provides the starting address of the data transmitted in the shared memory for the application layer to use.

[0091] Combined with Figure 5 as shown, Figure 5 is a simplified model of VirtIO (a front-end and back-end architecture). That is, the front-end driver 7 and the back-end device 6 perform data transmission through a data queue. In this application, it can be considered that the front-end driver 7 is the processor core that needs to send the data to be sent, and the back-end device 6 is the processor core that receives the data to be sent.

[0092] For VirtQueue, there are three core data structures: the Descriptor Table, the Available Ring, and the Used Ring. These three core data structures are organized by the VRing (Virtual Ring Buffer) structure.

[0093] The Descriptor Table is used to save a series of descriptors, and each descriptor is used to describe a memory area. For each memory area, if the data stored is written by the front-end driver to the device, this descriptor is called an out-type descriptor; if the data stored is read by the front-end driver from the device, this descriptor is called an in-type descriptor. Each descriptor contains some key fields, such as the address field (a pointer to the memory area), the length field (indicating the size of the memory area), and the next pointer field (used to link to the next descriptor to form a descriptor chain).

[0094] An available descriptor area for storing descriptors provided by the front-end driver to the back-end device and usable by the back-end device. The main body of the available descriptor area is a ring array, which is actually a circular buffer. The front-end driver provides caches to the back-end device through the available descriptor area, indicating the cache positions incremented by the front-end driver and the current working position.

[0095] A used descriptor area for storing descriptors that have been processed by the back-end device and have not been fed back to the front-end driver. The ring array of the used descriptor area is also a circular buffer. Different from the available descriptor area, it also records the data length written back by the back-end device.

[0096] In the VirtQueue mechanism, the front-end driver fills data through the following steps: The front-end driver allocates memory and adds a cache to the VirtQueue; updates and fills the descriptor table to point to the cache; after filling is completed, the front-end driver needs to publish the descriptor table to the available descriptor area and update the descriptor index value; after publishing is completed, the cache is managed by the back-end device, and the front-end driver needs to notify the back-end device that it will send notifications if necessary.

[0097] In the VirtQueue mechanism, the back-end device fills data through the following steps: The back-end device writes bytes into the writable cache in the descriptor table and notifies the front-end driver after writing.

[0098] In some embodiments, the Mailbox hardware module 2 receives the operation configuration instructions sent by the processor core 1 corresponding to the source address to the Mailbox hardware module 2. That is, the Mailbox hardware module 2 receives the destination address written by the processor core 1 corresponding to the source address into the mailbox destination register of the communication channel expected to be used in the Mailbox hardware module 2, and the Mailbox hardware module 2 receives the source address written by the processor core 1 corresponding to the source address into the mailbox source register of the communication channel expected to be used in the Mailbox hardware module 2.

[0099] Optionally, receiving the operation configuration instructions sent by the processor core 1 corresponding to the source address to the Mailbox hardware module 2 further includes: The Mailbox hardware module 2 receives the instruction written by the processor core 1 corresponding to the source address into the mode register of the communication channel expected to be used. Among them, the instruction written into the mode register is used to indicate the transmission mode of the communication channel.

[0100] Optionally, the operation configuration instruction sent by the processor core 1 corresponding to the source address and received by the Mailbox hardware module 2 further includes: the Mailbox hardware module 2 receives an instruction written by the processor core 1 corresponding to the source address to the mask register of the communication channel expected to be used. The instruction written to the mask register is used to indicate whether to mask the interrupt generated by the communication channel.

[0101] In this way, by receiving the operation configuration instruction of the processor core 1 corresponding to the source address through the Mailbox hardware module 2, it is possible to know in what way to use the communication channel to transmit the data to be sent, which is convenient for the processor core 1 to set an operation configuration instruction once, and can send the data to be sent to multiple other processor cores 1, or can send the data to be sent to the same other processor core 1 multiple times.

[0102] In some embodiments, the Mailbox hardware module 2 is used to send an interrupt request signal to the processor core 1 corresponding to the destination address through the following method according to the communication channel expected to be used to transmit the data to be sent until the first preset condition is met: for the communication channel that meets the second preset condition, perform a first preset operation on the processor core 1 corresponding to the destination address recorded in the mailbox target register of the communication channel; in the case where the first preset operation is performed on the processor core 1 corresponding to the destination address of all communication channels that meet the second preset condition, it is confirmed that the first preset condition is met.

[0103] The first preset operation includes sending an interrupt request signal to the processor core 1 corresponding to the destination address to transmit the data to be sent.

[0104] The second preset condition is that the transmission mode of the communication channel is the auto-response mode, and the source address is recorded in the mailbox source register of the communication channel.

[0105] In the above optional method, performing the first preset operation on the processor core 1 corresponding to the destination address recorded in the mailbox target register of the communication channel may include: repeatedly performing the first preset operation on the processor core 1 corresponding to the destination address currently located in the first position of the mailbox target register, and receiving the clear instruction of the processor core 1, and clearing the destination address located in the first position of the mailbox target register based on the clear instruction until no destination address is stored in the mailbox target register.

[0106] The clear instruction is used to indicate clearing the destination address of the processor core 1 that issues the clear instruction in the mailbox target register.

[0107] Optionally, the data stored in the mailbox destination register usually needs to be operated in the storage order. Therefore, in the implementation of this application, the first preset operation needs to be performed on the processor core 1 corresponding to the destination address at the first position in the mailbox destination register each time. If there is a mailbox destination register that allows out-of-order operations, the processor core 1 corresponding to the destination address recorded in the mailbox destination register can also be randomly selected or selected in other orders to perform the first preset operation, and the clear instruction of this processor core 1 is received.

[0108] Exemplarily, assume that there are 3 processor cores, for example: CoreA, Core B, and Core C. CoreA sets the source address corresponding to CoreA in the mailbox source register of the desired communication channel "Mailbox channel0", sets the destination addresses in the mailbox destination register of Mailboxchannel0 to Core B and Core C, configures not to mask the interrupt generated by the communication channel, fills the data to be sent into the storage register of Mailbox channel0, and configures the transmission mode of Mailbox channel0 as the auto-response mode. Finally, write 0x01 to the interrupt trigger register of Mailbox channel0 to send an interrupt request signal to the processor core "CoreB" corresponding to the destination address in the mailbox destination register of Mailbox channel0. After Core B processes the data, the destination address corresponding to Core B in the mailbox destination register of Mailbox channel0 is cleared. For the Mailbox hardware module, a look-up table mechanism is newly added. When the Mailbox hardware module queries that the destination address corresponding to Core B in the mailbox destination register is cleared, it means that the current Core B has completed the transmission. Since there is still Core C in the destination address of the mailbox destination register, the Mailbox hardware module will continue to send an interrupt request signal to Core C to transmit the data to be transmitted to Core C, without the participation of CoreA. After Core C processes the data, the destination address corresponding to Core C in the mailbox destination register of Mailboxchannel0 is cleared. At this time, the Mailbox hardware module knows through querying the mailbox destination register that the data in the mailbox destination register has been cleared, and automatically triggers a source interrupt signal to CoreA, thus completing one-to-many and multiple transmissions. Here, Core A writes 0x01 to the interrupt trigger register, that is, the interrupt trigger signal of the processor core corresponding to the source address.

[0109] In this way, in the prior art, after CoreA and CoreB complete data transmission once, CoreA needs to reconfigure the running configuration instructions and then perform data transmission with CoreC. That is, by configuring the running configuration instructions once, only one other processor core can be sent a message to be sent once. And during its transmission process, additional software is required to participate, increasing the communication time between processor cores and reducing the efficiency of data communication between processor cores. That is, through the transmission method of the prior art, after CoreA and CoreB complete data transmission, it is necessary to reconfigure the running configuration instructions to enable CoreA and CoreC to perform data transmission, during which 4 interrupts will be generated, adding a lot of unnecessary overhead. Through the above method of the present application, only by configuring the running configuration instructions once, the Mailbox hardware module can autonomously complete the one-to-many transmission of processor cores in the multi-core system during the transmission process, without the need for Core A to participate multiple times, reducing the communication time between processor cores and improving the efficiency of data communication between processor cores.

[0110] In some other embodiments, the Mailbox hardware module 2 is configured to send an interrupt request signal to the processor core 1 corresponding to the destination address to transmit the data to be sent through the following manner according to the communication channel expected to be used until a first preset condition is met: performing a second preset operation on all communication channels that meet a third preset condition; and confirming that the first preset condition is met when the second preset operation has been performed on all communication channels that meet the third preset condition.

[0111] Wherein, the second preset operation includes sending an interrupt request signal to the processor core 1 corresponding to the destination address recorded in the mailbox target register of this communication channel to transmit the data to be sent.

[0112] Wherein, the third preset condition is that the transmission mode of the communication channel is the link mode, and the source address is recorded in the mailbox source register of this communication channel.

[0113] In the above optional manner, the processor core 1 corresponding to the source address selects the communication channels expected to be used in ascending order of the channel numbers. Assuming there are N communication channels expected to be used, the first N - 1 communication channels expected to be used can be set to the link mode, and the Nth communication channel expected to be used can be set to the normal mode. Wherein, N is a positive integer. Performing the second preset operation on the communication channels that meet the third preset condition may include: if the transmission mode of the communication channel is the link mode, performing the second preset operation on this communication channel and the adjacent channel until the transmission mode of the adjacent channel is the normal mode; the adjacent channel is the communication channel adjacent to this communication channel and with a channel number greater than that of this communication channel.

[0114] If the processor core 1 corresponding to the source address selects the communication channel to be used in descending order of the channel numbers, the adjacent channel may be a communication channel adjacent to the communication channel and having a channel number smaller than that of the communication channel.

[0115] In this way, the communication channel desired to be used is selected in the order of the channel number from small to large, which can facilitate the management of the communication channels.

[0116] Exemplarily, if the amount of data to be sent is greater than the maximum amount of data that a single communication channel can bear, then a single communication channel cannot transmit all the data to be transmitted at one time. In this case, the link mode can be used to set the same destination address and source address for transmission in different communication channels. Assume that there are two processor cores, CoreA and CoreB. Core A sets the source address corresponding to CoreA in the mailbox source register of the communication channels Mailbox channel0 and Mailbox channel1 that are expected to be used, and records the destination address corresponding to Core B in the mailbox target register of the communication channels Mailbox channel0 and Mailbox channel1. Configure not to mask the interrupts generated by the communication channel, fill in the storage registers of Mailbox channel0 and Mailbox channel1 with the data to be sent, configure the transmission mode of Mailbox channel0 to link mode, and finally write 0x01 to the interrupt trigger register of Mailbox channel0 to send an interrupt request signal to the processor core Core B corresponding to the destination address of the mailbox target register in Mailbox channel0. After CoreB processes the data, Core B writes 0x10 to the interrupt trigger register of Mailbox channel0. The Mailbox module detects that the current Mailbox channel0 is in link mode, and will not generate a source interrupt signal to CoreA. Instead, the Mailbox module automatically writes 0x01 to the interrupt trigger register of Mailbox channel1, and continues to send an interrupt request signal to the processor core Core B corresponding to the destination address of the mailbox target register in Mailbox channel1. After Core B processes the data, Core B writes 0x10 to the interrupt trigger register of Mailbox channel1. The Mailbox hardware module detects that the current Mailbox channel1 is not in link mode, and will generate a source interrupt signal to CoreA. At this point, the link mode transmission is completed.

[0117] In this way, in the prior art, if the amount of data to be sent from Core A to Core B is too large, it may involve multiple consecutive transmissions between Core A and Core B. After each single transmission of data between Core A and Core B, Core A needs to reconfigure the running configuration instructions before it can transmit data with Core B again, which increases the communication time between the processor cores and reduces the efficiency of data communication between the processor cores. Through the above method, the present application only needs to configure the running configuration instructions once, and the Mailbox hardware module can independently complete the one-to-one large-data-volume transmission between the processor cores in the multi-core system during the transmission process, without the need for Core A to participate multiple times, reducing the communication time between the processor cores and improving the efficiency of data communication between the processor cores.

[0118] In some embodiments, the processor core includes a RISC-V (an open-source instruction set architecture) core; each RISC-V core stores the correspondence between the base address, the destination interrupt number, the source interrupt number, and the interrupt function respectively. The processor core 1 is further configured to: when receiving an interrupt request signal, obtain the carried destination interrupt number and the source interrupt number of the processor core 1 that generates the interrupt trigger signal; search for the interrupt function according to the preset base address, destination interrupt number, and source interrupt number; execute the interrupt function and read the data to be sent.

[0119] Among them, the interrupt function is used to respond to the processor core that generates the interrupt trigger signal. The interrupt function can also be used to read the data to be sent.

[0120] In some embodiments, for each RISC-V core, an ECLIC (Enhanced Core-Local Interrupt Controller) interrupt controller is provided. The RISC-V core pre-configures the corresponding enhanced core local interrupt controller in advance, obtains the mb_tx_irq interrupt number and the mb_rx_irq interrupt number to be sent, and configures the interrupt vector mode, trigger mode, interrupt level, interrupt priority, and interrupt handler entry address according to the capabilities provided by the enhanced core local interrupt controller, and enables the interrupt. For example: set the interrupt vector mode to non-vector interrupt mode; set the trigger mode to edge or level trigger; set the interrupt level such that the larger the value, the higher the level; set the interrupt priority such that the larger the value, the higher the priority, and interrupt preemption takes precedence over the interrupt level, and the interrupt priority is compared in the same case; the set interrupt handler entry address is used to find and execute the corresponding interrupt function after the interrupt is triggered. Specifically, set the interrupt vector mode in bit0 of the [CTRL.INTATTR] register. Set the trigger mode in bits 2-1 of the [CTRL.INTATTR] register. Set the interrupt level and interrupt priority in the [CTRL.INTATTR] register. Store the base address of the interrupt vector table in the [CSR_MTVT] register, and store the interrupt handler entry address at the address of the base address of the interrupt vector table + interrupt number offset. Configure the interrupt enable in the [CTRL.INTIE] register. Among them, the [CTRL.INTATTR] register is an interrupt attribute register for configuring the attributes of the interrupt source, such as the trigger mode, interrupt priority, etc., so as to control the interrupt behavior of the processor core. The [CTRL.INTIE] register is an interrupt enable register for controlling the enable state of a specific interrupt source. The [CSR_MTVT] register is a machine trap vector table register for setting the base address of the interrupt vector table.

[0121] Among them, the non-vector interrupt mode is a mode in which all interrupts share a single handler entry address. After an interrupt occurs, it is necessary to determine the interrupt source and then allocate processing. Its general process is interrupt occurrence, jump to the unified entry, read the interrupt flag, branch to the corresponding interrupt service program, clear the flag, and interrupt return.

[0122] After the above configuration is completed, the Mailbox hardware module's send and receive interrupt handlers are registered. When the Mailbox hardware module triggers an interrupt to the processor core corresponding to the destination address, the processor core corresponding to the destination address will generate a destination interrupt. After all the processor cores corresponding to the destination addresses to be transmitted have processed the data, the Mailbox hardware module triggers an interrupt to the processor core corresponding to the source address, and the data transmission is completed.

[0123] In some embodiments, the data to be sent is packed according to a preset transmission data format, and the data to be sent includes: service type. For the processor core corresponding to the destination address, it is also used to transmit the data to be sent to the service layer corresponding to the service type.

[0124] Exemplarily, as shown in combination with Figure 6 CoreA (the processor core corresponding to the source address) packs the data to be sent according to the Figure 3 format to obtain the data to be sent. Then CoreA transmits the data to be sent to Core B (the processor core corresponding to the destination address) through the Mailbox hardware module in the media access control layer and the physical layer. After Core B obtains the data to be sent, it transmits the data to be sent to the inter-core interrupt communication service layer for parsing to determine the data to be sent of what service type. Then Core B distributes the data to be sent to the service layer corresponding to the corresponding service type for parsing, and finally issues specific operations to the driver layer through the hardware abstraction layer, and the driver layer drives the hardware to execute specific operations and reply corresponding data to CoreA.

[0125] For example: Core A sends a clock command for obtaining the real-time clock supported by the clock service. Core A packs it according to the Figure 3 format, obtains the data to be sent and transmits it to Core B. After receiving the data to be sent, Core B identifies it as the data to be sent of the service type "clock type" by the inter-core interrupt service layer, and then transmits the data to be sent to the clock service layer. After the clock service layer receives the data to be sent, it is transmitted downward to the hardware through the hardware abstraction layer and the driver layer to operate the corresponding hardware.

[0126] Embodiment 2:

[0127] Please refer to Figure 7 , Figure 7 which is a flowchart of a communication method for a multi-core system provided by an embodiment of the present application and is applied to the multi-core system of Embodiment 1; the communication method includes:

[0128] S101, the processor core corresponding to the source address obtains the destination address and the communication channel expected to be used.

[0129] S102, the processor core corresponding to the source address sends a running configuration instruction to the Mailbox hardware module.

[0130] S103, the Mailbox hardware module receives the running configuration instruction.

[0131] S104, the processor core corresponding to the source address sends an interrupt trigger signal to the Mailbox hardware module.

[0132] S105, The Mailbox hardware module receives an interrupt trigger signal from the processor core corresponding to the source address, and sends an interrupt request signal to the processor core corresponding to the destination address according to the communication channel expected to be used to transmit the data to be sent until the first preset condition is met.

[0133] S106, The Mailbox hardware module sends a source interrupt signal to the processor core corresponding to the source address.

[0134] Wherein, the running configuration instruction is used to set the destination address in the mailbox destination register of the communication channel expected to be used, and set the source address in the mailbox source register of the communication channel expected to be used.

[0135] Wherein, the destination address is the address of the processor core that receives the data to be sent; the source address is the address of the processor core that sends the data to be sent.

[0136] Wherein, the communication channel expected to be used is obtained by the following method: determining the number of channels according to the data volume of the data to be sent; determining the communication channel expected to be used according to the number of channels and the hardware semaphore of each communication channel.

[0137] In some embodiments, the processor core that sends the running configuration instruction to the Mailbox hardware module will set the source address to its own address in the mailbox source register of the communication channel expected to be used. At this time, the Mailbox hardware module receives the running configuration instruction of the Mailbox hardware module from the processor core corresponding to the source address.

[0138] Optionally, the communication method further includes: the processor core corresponding to the source address obtains the data to be sent and writes the data to be sent to a storage location accessible by the processor core corresponding to the destination address.

[0139] Optionally, the running configuration instruction further includes: setting the transmission mode of the communication channel expected to be used. Sending an interrupt request signal to the processor core corresponding to the destination address according to the communication channel expected to be used to transmit the data to be sent until the first preset condition is met may include: for the communication channel that meets the second preset condition, performing a first preset operation on the processor core corresponding to the destination address recorded in the mailbox destination register of this communication channel; when the processor cores corresponding to the destination addresses of all communication channels that meet the second preset condition have all performed the first preset operation, it is confirmed that the first preset condition is met. Wherein, the first preset operation includes sending an interrupt request signal to the processor core corresponding to the destination address to transmit the data to be sent. The second preset condition is that the transmission mode of the communication channel is the auto-response mode, and the source address is recorded in the mailbox source register of the communication channel.

[0140] Optionally, perform a first preset operation on the processor core corresponding to the destination address recorded in the mailbox destination register of the communication channel, including: repeatedly performing the first preset operation on the processor core corresponding to the destination address currently located at the first position in the mailbox destination register, and receiving a clear instruction from this processor core, and clearing the destination address located at the first position in the mailbox destination register based on the clear instruction until no destination address is stored in the mailbox destination register.

[0141] Exemplarily, assume that the processor core corresponding to the source address is the first processor core, and the communication channel expected to be used is the first communication channel; the running configuration instruction includes instructing to record two destination addresses in the mailbox destination register of the first communication channel, and the processor cores corresponding to the two destination addresses are the second processor core and the third processor core respectively, record the address of the first processor core in the mailbox source register of the first communication channel, and the transmission mode of the first communication channel is the automatic response mode; combined Figure 8 As shown, an embodiment of the present application provides another communication method for a multi-core system, including:

[0142] S201, the first processor core determines the first communication channel as the communication channel expected to be used.

[0143] S202, the first processor core writes the data to be sent into the shared memory.

[0144] S203, the first processor core sends a running configuration instruction to the Mailbox hardware module.

[0145] S204, the Mailbox hardware module receives the running configuration instruction.

[0146] S205, the first processor core modifies the hardware semaphore of the first communication channel to busy.

[0147] S206, the first processor core sends an interrupt trigger signal to the Mailbox hardware module.

[0148] S207, the Mailbox hardware module receives the interrupt trigger signal.

[0149] S208, the Mailbox hardware module sends an interrupt request signal to the second processor core.

[0150] S209, the second processor core receives the interrupt request signal and obtains the data to be sent.

[0151] S210, the second processor core sends a clear instruction to the Mailbox hardware module.

[0152] S211, The Mailbox hardware module receives a clear instruction to clear the address of the second processor core stored in the mailbox destination register of the first communication channel.

[0153] S212, The Mailbox hardware module sends an interrupt request signal to the third processor core.

[0154] S213, The third processor core receives the interrupt request signal and obtains the data to be sent.

[0155] S214, The third processor core sends a clear instruction to the Mailbox hardware module.

[0156] S215, The Mailbox hardware module receives the clear instruction to clear the address of the third processor core stored in the mailbox destination register of the first communication channel.

[0157] S216, The Mailbox hardware module sends a source interrupt signal to the first processor core.

[0158] S217, Receive the source interrupt signal.

[0159] In this way, only need to configure the Mailbox hardware module once, which can achieve multiple transmissions from a single core to multiple cores, saving hardware resources.

[0160] Optionally, the running configuration instruction further includes: setting the transmission mode of the communication channel expected to be used; sending an interrupt request signal to the processor core corresponding to the destination address according to the communication channel expected to be used to transmit the data to be sent until the first preset condition is met, including: performing a second preset operation on all communication channels that meet the third preset condition; in the case where the second preset operation is performed on all communication channels that meet the third preset condition, confirming that the first preset condition is met. Wherein, the second preset operation includes sending an interrupt request signal to the processor core corresponding to the destination address recorded in the mailbox destination register of this communication channel to transmit the data to be sent; the third preset condition is that the transmission mode of the communication channel is the link mode, and the source address is recorded in the mailbox source register of this communication channel.

[0161] Optionally, performing the second preset operation on the communication channels that meet the third preset condition includes: if the transmission mode of the communication channel is the link mode, performing the second preset operation on this communication channel and the adjacent channels until the transmission mode of the adjacent channels is the normal mode; the adjacent channels are the communication channels adjacent to this communication channel and with a channel number greater than the channel number of this communication channel.

[0162] Exemplarily, assume that the processor core corresponding to the source address is the first processor core, and the communication channels expected to be used are the first communication channel and the second communication channel; the running configuration instruction includes instructing to record the address of the second processor core in the mailbox destination register of the first communication channel, record the address of the second processor core in the mailbox destination register of the second communication channel, record the address of the first processor core in the mailbox source register of the first communication channel, record the address of the first processor core in the mailbox source register of the second communication channel, the transmission mode of the first communication channel is the link mode, and the transmission mode of the second communication channel is the normal mode; combined with Figure 9 As shown in

[0163] S301, the first processor core determines the first communication channel and the second communication channel as the communication channels expected to be used.

[0164] S302, the first processor core writes the data to be sent into the shared memory.

[0165] S303, the first processor core sends a running configuration instruction to the Mailbox hardware module.

[0166] S304, the Mailbox hardware module receives the running configuration instruction.

[0167] S305, the first processor core modifies the hardware semaphores of the first communication channel and the second communication channel to busy.

[0168] S306, the first processor core sends an interrupt trigger signal to the Mailbox hardware module.

[0169] S307, the Mailbox hardware module receives the interrupt trigger signal.

[0170] S308, the Mailbox hardware module sends an interrupt request signal to the second processor core through the first communication channel.

[0171] S309, the second processor core receives the interrupt request signal and obtains the data to be sent.

[0172] S310, the second processor core sends a completion instruction to the Mailbox hardware module.

[0173] S311, the Mailbox hardware module receives the completion instruction.

[0174] S312, the Mailbox hardware module sends an interrupt request signal to the second processor core through the second communication channel.

[0175] In S313, the second processor core receives an interrupt request signal and obtains the data to be sent.

[0176] In S314, the second processor core sends a completion instruction to the Mailbox hardware module.

[0177] In S315, the Mailbox hardware module receives the completion instruction.

[0178] In S316, the Mailbox hardware module sends a source interrupt signal to the first processor core.

[0179] In S317, the source interrupt signal is received.

[0180] In this way, the Mailbox hardware module only needs to be configured once, and multiple transmissions for a single processor core can be achieved. It solves the difficulty of large - data - volume transmission for the same processor core in a multi - core system at the same time.

[0181] Optionally, the processor core includes a RISC - V core; each RISC - V core stores the corresponding relationship between the base address, the destination interrupt number, the source interrupt number, and the interrupt function. Sending an interrupt request signal to the processor core corresponding to the destination address to transmit the data to be sent includes: sending an interrupt request signal to the processor core corresponding to the destination address, triggering the processor core to execute a third preset operation. Among them, the third preset operation includes obtaining the destination interrupt number of the processor core executing the third preset operation and the source interrupt number of the processor core generating the interrupt trigger signal, looking up the interrupt function according to the preset base address, destination interrupt number, and source interrupt number, executing the interrupt function and reading the data to be sent. The interrupt function is used to respond to the processor core generating the interrupt trigger signal.

[0182] Optionally, the data to be sent includes: service type. The communication method further includes: the processor core corresponding to the destination address transmits the data to be sent to the service layer corresponding to the service type.

[0183] Exemplarily, assume that the multi-core system is a RISC-V multi-core system, and there are three RISC-V processor cores in the multi-core system, such as: the first processor core, the second processor core, and the third processor core. First, the first processor core, the second processor core, and the third processor core respectively configure their corresponding enhanced core local interrupt controllers, set the interrupt vector mode, trigger mode, interrupt level, interrupt priority, interrupt handling function entry address, etc. in the enhanced core local interrupt controller, and enable the interrupt. Assume that the processor core corresponding to the source address is the first processor core, and the desired communication channel is the first communication channel, and data to be sent needs to be transmitted to the second processor core and the third processor core. At this time, the first processor core writes the data to be sent into the shared memory, and then sends a running configuration instruction to configure the Mailbox hardware module. The running configuration instruction is, for example: record the addresses of the second processor core and the third processor core in the mailbox destination register of the first communication channel, record the address of the first processor core in the mailbox source register of the first communication channel, and set the transmission mode of the first communication channel to the auto-response mode. After configuring the Mailbox hardware module, the first processor core modifies the hardware semaphore of the first communication channel to busy and sends an interrupt trigger signal to the Mailbox hardware module. After receiving the interrupt trigger signal, the Mailbox hardware module sends an interrupt request signal to the second processor core. The second processor core receives the interrupt request signal, obtains the destination interrupt number of the second processor core and the source interrupt number of the first processor core that generates the interrupt trigger signal, searches for the interrupt function according to the preset base address, the destination interrupt number of the second processor core, and the source interrupt number of the first processor core, executes the interrupt function and reads the data to be sent. After reading the data to be sent, the second processor core sends a clear instruction to the Mailbox hardware module. The Mailbox hardware module receives the clear instruction and clears the address of the second processor core stored in the mailbox destination register of the first communication channel. Since the address of the third processor core is still stored in the mailbox destination register of the first communication channel at this time, the Mailbox hardware module continues to send an interrupt request signal to the third processor core. The third processor core receives the interrupt request signal, obtains the destination interrupt number of the third processor core and the source interrupt number of the first processor core that generates the interrupt trigger signal, searches for the interrupt function according to the preset base address, the destination interrupt number of the third processor core, and the source interrupt number of the first processor core, executes the interrupt function and reads the data to be sent. After reading the data to be sent, the third processor core sends a clear instruction to the Mailbox hardware module. The Mailbox hardware module receives the clear instruction and clears the address of the third processor core stored in the mailbox destination register of the first communication channel.Since the mailbox target register of the first communication channel does not store the destination address at this time, the Mailbox hardware module sends a source interrupt signal to the first processor core.

[0184] It can be understood that the embodiments described in Embodiment 1 are also applicable in Embodiment 2 without conflict. For the sake of simplicity of description, they will not be elaborated here.

[0185] The technical solution of the embodiment of the present application can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes one or more instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method of the embodiment of the present application. The foregoing storage medium can be a non-transitory storage medium, including: various media such as USB flash drives, mobile hard disks, read-only memories, random access memories, magnetic disks, or optical discs that can store program codes, or it can also be a transient storage medium.

[0186] In the embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are only illustrative. For example, the division of units is only a logical function division, and there can be other division methods in actual implementation. For another example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed.

[0187] The above are only the embodiments of the present application and are not used to limit the protection scope of the present application. For those skilled in the art, the present application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application. At the same time, the above embodiments can be combined with each other without conflict to form new embodiments.

Claims

1. A communication method for a multi-core system, characterized in that, Applied to the Mailbox hardware module in a multi-core system, the multi-core system further includes a plurality of processor cores; the Mailbox hardware module includes a plurality of communication channels; each of the communication channels is respectively provided with a mailbox destination register and a mailbox source register; the method includes: Receiving a running configuration instruction of the processor core for the Mailbox hardware module; the running configuration instruction is used to set a destination address in the mailbox destination register of the communication channel expected to be used, and set a source address in the mailbox source register of the communication channel expected to be used; the destination address is the address of the processor core that receives the data to be sent; the source address is the address of the processor core that sends the data to be sent; When an interrupt trigger signal of the processor core corresponding to the source address is received, sending an interrupt request signal to the processor core corresponding to the destination address through the communication channel expected to be used to transmit the data to be sent until a first preset condition is met, and sending a source interrupt signal to the processor core corresponding to the source address; the first preset condition is that all the communication channels where the mailbox source register recording the source address is located are used, and the destination addresses recorded in the mailbox destination registers of these communication channels have all been transmitted.

2. The method according to claim 1, wherein The running configuration instruction further includes: setting the transmission mode of the communication channel expected to be used; sending an interrupt request signal to the processor core corresponding to the destination address through the communication channel expected to be used to transmit the data to be sent until a first preset condition is met, including: For the communication channel that meets the second preset condition, performing a first preset operation on the processor core corresponding to the destination address recorded in the mailbox destination register of this communication channel; the first preset operation includes sending the interrupt request signal to the processor core corresponding to the destination address to transmit the data to be sent; the second preset condition is that the transmission mode of the communication channel is the automatic response mode, and the source address is recorded in the mailbox source register of the communication channel. Wherein, when the first preset operation is performed on the processor cores corresponding to the destination addresses of all the communication channels that meet the second preset condition, it is confirmed that the first preset condition is met.

3. The method according to claim 2, wherein Performing the first preset operation on the processor core corresponding to the destination address recorded in the mailbox destination register of the communication channel, including: Repeatedly performing the first preset operation on the processor core corresponding to the destination address currently located at the first position in the mailbox destination register, and receiving a clear instruction from this processor core, and clearing the destination address located at the first position in the mailbox destination register based on the clear instruction until no destination address is stored in the mailbox destination register.

4. The method according to claim 1, characterized in that The running configuration instruction further includes: setting the transmission mode of the communication channel expected to be used; sending an interrupt request signal to the processor core corresponding to the destination address through the communication channel expected to be used to transmit the data to be sent until a first preset condition is met, including: Perform a second preset operation on all communication channels that meet the third preset condition; the second preset operation includes sending the interrupt request signal to the processor core corresponding to the destination address recorded in the mailbox destination register of the communication channel to transmit the data to be sent; the third preset condition is that the transmission mode of the communication channel is the link mode, and the source address is recorded in the mailbox source register of the communication channel. Wherein, when the second preset operation is performed on all communication channels that meet the third preset condition, it is confirmed that the first preset condition is met.

5. The method according to claim 4, characterized in that, Performing the second preset operation on the communication channels that meet the third preset condition includes: If the transmission mode of the communication channel is the link mode, perform the second preset operation on the communication channel and the adjacent channel until the transmission mode of the adjacent channel is the normal mode; the adjacent channel is the communication channel adjacent to the communication channel and with a channel number greater than the channel number of the communication channel.

6. The method according to any one of claims 1 to 5, characterized in that The processor core includes a RISC-V core; each RISC-V core stores the corresponding relationship between the base address, the destination interrupt number, the source interrupt number, and the interrupt function. Sending an interrupt request signal to the processor core corresponding to the destination address to transmit the data to be sent includes: Sending an interrupt request signal to the processor core corresponding to the destination address to trigger the processor core to perform a third preset operation; the third preset operation includes obtaining the destination interrupt number of the processor core performing the third preset operation and the source interrupt number of the processor core generating the interrupt trigger signal, looking up the interrupt function according to the preset base address, the destination interrupt number, and the source interrupt number, and executing the interrupt function and reading the data to be sent; the interrupt function is used to respond to the processor core generating the interrupt trigger signal.

7. A communication method for a multi-core system, characterized in that Applied to any one of the processor cores in a multi-core system, the multi-core system further includes a Mailbox hardware module; the Mailbox hardware module includes multiple communication channels; the method includes: Obtain the destination address and the communication channel expected to be used. Set the destination address in the mailbox destination register of the communication channel expected to be used, and set the source address in the mailbox source register of the communication channel expected to be used; the destination address is the address of the processor core receiving the data to be sent; the source address is the address of the processor core sending the data to be sent. Send an interrupt trigger signal to trigger the Mailbox hardware module to send an interrupt request signal to the processor core corresponding to the destination address according to the communication channel expected to be used to transmit the data to be sent until the first preset condition is met, and receive the source interrupt signal returned by the Mailbox hardware module.

8. The method according to claim 7, wherein The communication channel expected to be used is obtained by: Determine the number of channels according to the data volume of the data to be sent; Determine the communication channel expected to be used according to the number of channels and the hardware signal volume of each communication channel.

9. The method according to claim 7, characterized in that, The method further includes: Obtain the data to be sent. Write the data to be sent to a storage location accessible by the processor core corresponding to the destination address.

10. The method according to claim 7, wherein The data to be sent includes: service type; the method further includes: Transmit the data to be sent to the service layer corresponding to the service type.

11. The method according to any one of claims 7 to 10, characterized in that, The processor core includes a RISC-V core; the corresponding relationships between the base address, destination interrupt number, source interrupt number, and interrupt function are respectively stored in each RISC-V core; the method further includes: When receiving the interrupt request signal, obtain the carried destination interrupt number and the source interrupt number of the processor core that generates the interrupt trigger signal. Search for an interrupt function according to the preset base address, the destination interrupt number, and the source interrupt number; the interrupt function is used to respond to the processor core that generates the interrupt trigger signal. Execute the interrupt function and read the data to be sent.

12. A multi-core system, characterized in that, Includes: A processor core for obtaining a destination address and a communication channel expected to be used. Set the destination address in the mailbox target register of the communication channel expected to be used, and set the source address in the mailbox source register of the communication channel expected to be used. Send an interrupt trigger signal to the Mailbox hardware module; the destination address is the address of the processor core that receives the data to be sent; the source address is the address of the processor core that sends the data to be sent. The Mailbox hardware module is configured to send an interrupt request signal to the processor core corresponding to the destination address according to the communication channel expected to be used to transmit the data to be sent until a first preset condition is met, and send a source interrupt signal to the processor core corresponding to the source address.

13. The multi-core system according to claim 12, characterized in that, The processor core is further configured to set the transmission mode of the communication channel expected to be used; specifically, the Mailbox hardware module is configured to send an interrupt request signal to the processor core corresponding to the destination address according to the communication channel expected to be used to transmit the data to be sent until a first preset condition is met in the following manner: For the communication channel that meets the second preset condition, perform a first preset operation on the processor core corresponding to the destination address recorded in the mailbox target register of this communication channel; the first preset operation includes sending the interrupt request signal to the processor core corresponding to the destination address to transmit the data to be sent; the second preset condition is that the transmission mode of the communication channel is the auto-response mode, and the source address is recorded in the mailbox source register of the communication channel. Wherein, when the first preset operation is executed by the processor cores corresponding to the destination addresses of all the communication channels that meet the second preset condition, it is confirmed that the first preset condition is met.

14. The multi-core system according to claim 13, characterized in that, Specifically, the Mailbox hardware module is configured to perform the first preset operation on the processor core corresponding to the destination address recorded in the mailbox target register of the communication channel in the following manner: Repeatedly perform a first preset operation on the processor core corresponding to the destination address currently located at the first position in the mailbox target register, and receive a clear instruction from this processor core. Based on the clear instruction, clear the destination address located at the first position in the mailbox target register until the mailbox target register does not store the destination address.

15. The multi-core system according to claim 12, wherein The processor core is further configured to set the transmission mode of the communication channel expected to be used; specifically, the Mailbox hardware module is configured to send an interrupt request signal to the processor core corresponding to the destination address through the following manner according to the communication channel expected to be used to transmit the data to be sent until a first preset condition is satisfied: Perform a second preset operation on all communication channels that meet a third preset condition; the second preset operation includes sending the interrupt request signal to the processor core corresponding to the destination address recorded in the mailbox target register of this communication channel to transmit the data to be sent; the third preset condition is that the transmission mode of the communication channel is the link mode, and the source address is recorded in the mailbox source register of this communication channel. Among them, when the second preset operation is performed on all communication channels that meet the third preset condition, it is confirmed that the first preset condition is satisfied.

16. The multi-core system according to claim 15, wherein Specifically, the Mailbox hardware module is configured to perform the second preset operation on the communication channels that meet the third preset condition through the following manner: If the transmission mode of the communication channel is the link mode, perform the second preset operation on this communication channel and the adjacent channel until the transmission mode of the adjacent channel is the normal mode; the adjacent channel is the communication channel adjacent to this communication channel and with a channel number greater than the channel number of this communication channel.

17. The multi-core system according to claim 12, wherein The processor core is further configured to: obtain the data to be sent; write the data to be sent to a storage location accessible by the processor core corresponding to the destination address.

18. The multi-core system according to claim 12, wherein The data to be sent includes: service type; the processor core is further configured to: transmit the data to be sent to the service layer corresponding to the service type.

19. The multi-core system according to any one of claims 12 to 18, characterized in that, The processor core includes a RISC-V core; each RISC-V core stores the corresponding relationship between the base address, destination interrupt number, source interrupt number, and interrupt function; the processor core is further configured to: When receiving the interrupt request signal, obtain the carried destination interrupt number and the source interrupt number of the processor core that generates the interrupt trigger signal; Search for an interrupt function according to the preset base address, the destination interrupt number, and the source interrupt number; the interrupt function is used to respond to the processor core that generates the interrupt trigger signal; Execute the interrupt function and read the data to be sent.

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