Test method of split-gate flash memory
By testing the capacitance between the first through hole and the second through hole structure in the split gate flash memory, the problem of over-etching of the active region is solved, precise control of the etching process is achieved, and the manufacturing quality of the memory is ensured.
Patent Information
- Application Number
- CN202510396988.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-31
- Publication Date
- 2025-07-18
AI Technical Summary
In the prior art, the partition flash memory is prone to overetching of the active region during the formation of floating gate, gate polysilicon or memory gate, which makes it impossible to accurately judge the etching situation.
After forming a gate structure in a split gate flash memory, the capacitance between the first through-hole structure and the second through-hole structure is tested, and whether the capacitance is within the set value, and whether the active region has over-etched. The specific method includes forming a through-hole structure on the gate polysilicon and the memory gate, and testing the capacitance value to judge the over-etching situation during the etching process.
Accurate judgment of the overetching problem of active region is achieved, precise control of etching during the manufacturing process of sub-gate flash memory, and overetching of the active region is avoided.
Smart Images
Figure CN120340575A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and more particularly to a test method for a split-gate flash memory. Background Art
[0002] With the development of technology, the application of data storage media has shifted from some traditional non-volatile memories to flash memory type memories. Large-capacity solid-state storage devices with flash memory as the main storage medium have become one of the mainstream solutions for data storage today.
[0003] The split-gate flash memory includes a stacked gate structure such as a floating gate layer (Floating gate, FG), a control gate layer, a gate polysilicon, and a memory polysilicon formed on an active region. Specifically, please refer to Figure 1 , a gate oxide layer 102 is formed on the surface of the active region 101. A gate structure is formed on the surface of the gate oxide layer 102. The gate structure includes a floating gate 103 located on the surface of the gate oxide layer 102, a first sidewall 104 located on the surface of the floating gate 103, a word line 105 located between the openings formed by the floating gate 103, a second sidewall 106 that separates both the word line 105 from the first sidewall 104 and the word line 105 from the floating gate 103, and a word line protection layer 107 covering the word line 105. The split-gate flash memory further includes a first interlayer dielectric layer 108, a memory gate 109, a second interlayer dielectric layer 109, and a gate polysilicon 110 that sequentially cover the gate structure.
[0004] However, through slice analysis of the existing split-gate flash memory, it is found that sometimes the problem of over-etching of the active region occurs, and it is impossible to know that the active region is etched during the formation of the floating gate, the gate polysilicon, or the memory gate. Summary of the Invention
[0005] The purpose of the present invention is to provide a test method for a split-gate flash memory, which can determine whether the over-etching of the active region is caused during the formation of the floating gate, the gate polysilicon, or the memory gate.
[0006] To achieve the above purpose, the present invention provides a test method for a split-gate flash memory, including:
[0007] Providing a substrate and forming an active region in the substrate;
[0008] Forming a gate structure on the surface of a part of the active region, the gate structure including a floating gate located on the surface of the active region, a first sidewall located on the surface of the floating gate, a word line located between the openings formed by the floating gate, and a second sidewall that separates both the first sidewall and the floating gate from the word line;
[0009] A memory gate and gate polysilicon are sequentially formed on the surface of the gate structure, and a part of the surface of the memory gate is exposed by the gate polysilicon. Parts of the surfaces of the gate polysilicon, the memory gate, and the gate structure are exposed on the surface of the active region.
[0010] A first via structure is formed on the gate polysilicon, a second via structure is formed on the exposed memory gate, and a third via structure is formed on the exposed active region.
[0011] Test the first capacitance between the first via structure and the second via structure or test the second capacitance between the second via structure and the third via structure, and determine whether the first capacitance is within a first set value, determine whether the second capacitance is within a second set value, and determine whether the sum of the first capacitance and the second capacitance is within a third set value. If the sum of the first capacitance and the second capacitance is within the set values, it is considered that the active region is over-etched during the formation of the memory gate. If the second capacitance is within the set value, it is considered that the gate polysilicon is still... When the sum of the first capacitance and the second capacitance is within the third set value, it is determined that the active region is over-etched during the formation of the floating gate. When the first capacitance is outside the first set value and the second capacitance is within the second set value, it is determined that the active region is over-etched during the formation of the gate polysilicon. When the first capacitance is within the first set value and the second capacitance is outside the second set value, it is determined that the active region is over-etched during the formation of the memory gate.
[0012] Optionally, in the test method of the split-gate flash memory, the gate structure further includes: a gate oxide layer, and the gate oxide layer is located between the active region and the floating gate.
[0013] Optionally, in the test method of the split-gate flash memory, the gate structure further includes: a word line protection layer, and the word line protection layer is located on the surface of the word line.
[0014] Optionally, in the test method of the split-gate flash memory, after forming the gate structure on the surface of the active region, it further includes:
[0015] Form a first interlayer dielectric layer on the surface of the gate structure.
[0016] Optionally, in the test method of the split-gate flash memory, after forming the memory gate on the surface of the gate structure, it further includes:
[0017] Form a second interlayer dielectric layer on the surface of the memory gate.
[0018] Optionally, in the test method of the split-gate flash memory, there are multiple gate structures, and adjacent gate structures expose parts of the surface of the active region.
[0019] Optionally, in the method for testing the split-gate flash memory, the gate polysilicon on the adjacent gate structures exposes the surface of the memory gate on the active region between the adjacent gate structures.
[0020] Optionally, in the method for testing the split-gate flash memory, the method for forming the floating gate includes:
[0021] Forming a floating gate material layer on the surface of the active region;
[0022] After forming the word line, etching the floating gate material layer to form the floating gate.
[0023] Optionally, in the method for testing the split-gate flash memory, the method for forming the memory gate includes:
[0024] Forming a polysilicon material layer on the surface of the gate structure;
[0025] Etching the polysilicon material layer to form the memory gate.
[0026] Optionally, in the method for testing the split-gate flash memory, the method for forming the gate polysilicon includes:
[0027] Forming a polysilicon material layer on the surface of the memory gate;
[0028] Etching the polysilicon material layer to form the gate polysilicon.
[0029] In the method for testing the split-gate flash memory provided by the present invention, when over-etching occurs in the active region, by testing the first capacitor and the second capacitor and determining whether it is within the set value, it is determined that the problem of over-etching of the active region occurs during the formation of the floating gate, the gate polysilicon, or the memory gate. Description of the Drawings
[0030] Figure 1 is a schematic structural diagram of a split-gate flash memory in the prior art;
[0031] Figure 2 is a flowchart of the method for testing the split-gate flash memory according to an embodiment of the present invention;
[0032] Figures 3 to 6 is a schematic structural diagram of forming a split-gate flash memory according to an embodiment of the present invention;
[0033] In the figure: 101 - active region, 102 - gate oxide layer, 103 - floating gate, 104 - first sidewall, 105 - word line, 106 - second sidewall, 107 - word line protection layer, 108 - first interlayer dielectric layer, 109 - memory gate, 110 - second interlayer dielectric layer, 111 - gate polysilicon, 201 - active region, 202 - gate oxide layer, 202A - gate oxide material layer, 203 - floating gate, 203A - floating gate material layer, 204 - mask layer, 205 - first sidewall, 206 - second sidewall, 207 - word line, 208 - word line protection layer, 209 - first interlayer dielectric layer, 210 - memory gate, 211 - second interlayer dielectric layer, 212 - gate polysilicon, 213 - first via structure, 214 - second via structure, 215 - third via structure. Detailed implementation manners
[0034] The specific implementation manners of the present invention will be described in more detail below with reference to the schematic diagrams. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only for the purpose of facilitating and clearly assisting in explaining the purpose of the embodiments of the present invention.
[0035] In the following text, terms such as "first" and "second" are used to distinguish between similar elements and are not necessarily used to describe a specific order or time sequence. It should be understood that, under appropriate circumstances, these terms used in this way can be replaced. Similarly, if the method described in this article includes a series of steps, and the order of these steps presented in this article is not necessarily the only order in which these steps can be executed, and some of the described steps can be omitted and / or some other steps not described in this article can be added to this method.
[0036] Moreover, it should be understood that when a layer (or film), region, pattern or structure is referred to as being "on" a substrate, layer (or film), region and / or pattern, it can be directly on another layer or substrate, and / or there can also be an intervening layer. Additionally, it should be understood that when a layer is referred to as being "under" another layer, it can be directly under another layer, and / or there can also be one or more intervening layers. Additionally, the references to "on" and "under" each layer can be based on the drawings.
[0037] Please refer to Figure 2 , the present invention provides a test method for a split-gate flash memory, including:
[0038] S11: Provide a substrate and form an active region in the substrate;
[0039] S12: Form a gate structure on the surface of the partial active region. The gate structure includes a floating gate located on the surface of the active region, a first sidewall located on the surface of the floating gate, a word line located between the openings formed by the floating gate, and a second sidewall separating both the first sidewall and the floating gate from the word line;
[0040] S13: Sequentially form a memory gate and gate polysilicon on the surface of the gate structure. The gate polysilicon exposes the surface of part of the memory gate, and the gate polysilicon, the memory gate, and the gate structure all expose the surface of part of the active region;
[0041] S14: Form a first via structure on the gate polysilicon, a second via structure on the exposed memory gate, and a third via structure on the exposed active region;
[0042] S15: Test the first capacitance between the first via structure and the second via structure or test the second capacitance between the second via structure and the third via structure, and determine whether the first capacitance is within a first set value, determine whether the second capacitance is within a second set value, and determine whether the sum of the first capacitance and the second capacitance is within a third set value. If the sum of the first capacitance and the second capacitance is within the set values, it is considered that the active region is over-etched during the formation of the memory gate. If the second capacitance is within the set value, it is considered that the gate polysilicon is still... When the sum of the first capacitance and the second capacitance is within the third set value, determine that the active region is over-etched during the formation of the floating gate. When the first capacitance is outside the first set value and the second capacitance is within the second set value, determine that the active region is over-etched during the formation of the gate polysilicon. When the first capacitance is within the first set value and the second capacitance is outside the second set value, determine that the active region is over-etched during the formation of the memory gate.
[0043] Please refer to Figure 3 , first, provide a substrate. The substrate can be a silicon substrate. In the embodiments of the present invention, a wafer is selected as the substrate. Next, form a plurality of shallow trench isolation structures in the substrate, and form an active region 201 in the substrate between the shallow trench isolation structures. Next, form a gate oxide material layer 202A on the surface of the active region 201. The forming method can be a PVD deposition method. The material of the gate oxide material layer 202A can be silicon oxide. Specifically, in the embodiments of the present invention, silicon dioxide is selected. Next, form a floating gate material layer 203A on the surface of the gate oxide material layer 202A. The forming method can be a PVD deposition method. The material of the floating gate material layer 203A can be polysilicon. Next, form a floating gate mask layer 204 on the surface of the floating gate material layer 203A. The forming method can be a PVD deposition method. The material of the floating gate mask layer 204 can be a nitride. Specifically, in the embodiments of the present invention, silicon nitride is selected. Next, please continue to refer to Figure 3, etch the floating gate mask layer 204 and a part of the thickness of the floating gate material layer 203A downward from the surface of the floating gate mask layer 204 in sequence to form a first opening in the floating gate mask layer 204 and the floating gate material layer 203A. Then, form a first sidewall 205 in the first opening. The top of the first sidewall 205 is connected to the floating gate mask layer 204, and the bottom of the first sidewall 205 is connected to the floating gate material layer 203A. Therefore, the first sidewall 205 covers the sidewall of the floating gate mask layer 204 and a part of the floating gate material layer 203A. The material of the first sidewall 205 can be an oxide, specifically silicon dioxide. The method of forming the first sidewall 205 can be to first form a silicon dioxide material layer in the first opening by deposition, and then etch the silicon dioxide material layer to form the first sidewall 205. Then, use the first sidewall 205 as a mask to etch the floating gate material layer 203A and the gate oxide material layer 202A to form a second opening, and the surface of the active region 201 is exposed in the second opening.
[0044] Then, please continue to refer to Figure 4 , form a second sidewall 206 in the second opening. The top of the second sidewall 206 is connected to the first sidewall 205, and the bottom is connected to the surface of the active region 201. The material of the second sidewall 206 can be an oxide, specifically silicon dioxide. The method of forming the second sidewall 206 can be to first form a silicon dioxide material layer in the second opening by deposition, and then etch the silicon dioxide material layer to form the second sidewall 206. Then, fill a polysilicon material layer in the third opening formed by the first sidewall 205 and the second sidewall 206, and grind the surface of the polysilicon material layer, so as to form a word line 207 in the third opening. Then, form a word line protection layer 208 on the surface of the word line 207. The material of the word line protection layer 208 can be an oxide, specifically silicon dioxide.
[0045] Then, please refer to Figure 5 , remove the floating gate mask layer 204, and remove the floating gate material layer 203A and the gate oxide material layer 202A located under the floating gate mask layer 204 to expose the surface of a part of the active region 201. The remaining floating gate material layer 203A forms the floating gate 203, and the remaining gate oxide material layer 202A serves as the gate oxide layer 202. At this time, during the process of etching the floating gate material layer 203A to form the floating gate 203, if over-etching occurs, it may cause over-etching of the active region 201. The word line protection layer 208, the word line 207, the second sidewall 206, the first sidewall 205, the floating gate 203, and the gate oxide layer 202 form a gate structure.
[0046] Then, please refer to Figure 6, a first interlayer dielectric layer 209, a memory gate 210, a second interlayer dielectric layer 211, and a gate polysilicon 212 are sequentially formed on the surface of the gate structure and the surface of the exposed active region 201. The method of forming the memory gate 210 is to first form a polysilicon material layer and then etch the polysilicon material layer to form the memory gate 210. At this time, if over-etching occurs during the process of etching the polysilicon material layer to form the memory gate 210, over-etching of the active region 201 may be caused. The method of forming the gate polysilicon 212 is to first form a polysilicon material layer and then etch the polysilicon material layer to form the gate polysilicon 212. At this time, if over-etching occurs during the process of etching the polysilicon material layer to form the gate polysilicon 212, over-etching of the active region 201 may also be caused. Then, a first via structure 213 is formed on the surface of the gate polysilicon 212, a second via structure 214 is formed on the memory gate, and a third via structure 215 is formed on the surface of the active region. Among them, when there are multiple gate structures, each gate structure is connected, and a gate oxide layer 202, a floating gate 203, a first sidewall 205 on the surface of the floating gate 203, a word line 207 between the openings formed by the floating gate 203, and a second sidewall 206 that separates the floating gate oxide layer 202, the first sidewall 205, and the floating gate 203 from the word line 207 are formed on the surface of the active region according to the foregoing steps. The surface of a part of the active region 201 is exposed between the gate structures, and the first interlayer dielectric layer 209 and the memory gate 210 cover the surface of the gate structure and the surface of the active region 201 exposed between adjacent gate structures. The second interlayer dielectric layer 211 and the gate polysilicon 212 cover the memory gate 210 on the surface of the gate structure, and a part of the surface of the memory gate 210 between adjacent gate structures is exposed. Since the memory gate 210 forms a corner in the space between adjacent gate structures, gate polysilicon is not formed here, which can prevent redundant particles from appearing in the gate polysilicon here.
[0047] Finally, through the slicing analysis of the split-gate memory, by comparing the surface of the active region with the surface of other active regions or the surface of the shallow trench isolation structure, it is checked whether there is over-etching of the active region. If over-etching exists, the first capacitance between the first via structure and the second via structure or the second capacitance between the second via structure and the third via structure is tested. It is judged whether the first capacitance is within the first set value, whether the second capacitance is within the second set value, and whether the sum of the first capacitance and the second capacitance is within the third set value. The first set value, the second set value, and the third set value are all values set by testing the first capacitance, the second capacitance, and the third capacitance of a normal split-gate memory. When the sum of the first capacitance and the second capacitance is within the third set value, it is judged that over-etching occurs in the process of etching the floating gate material layer to form the floating gate. When the first capacitance is outside the first set value and the second capacitance is within the second set value, it is judged that over-etching occurs in the process of etching the polysilicon material layer to form the gate polysilicon. When the first capacitance is within the first set value and the second capacitance is outside the second set value, it is judged that over-etching occurs in the process of etching the polysilicon material layer to form the memory gate.
[0048] In summary, in the test method of the split-gate flash memory provided in the embodiment of the present invention, when over-etching occurs in the active region, by testing the first capacitance and the second capacitance and judging whether they are within the set values, it is judged that the problem of over-etching of the active region occurs in the process of forming the floating gate, the gate polysilicon, or the memory gate.
[0049] The above is only the preferred embodiment of the present invention and does not impose any limitation on the present invention. Any person skilled in the art, without departing from the technical solution of the present invention, makes any form of equivalent replacement or modification and other changes to the technical solution and technical content disclosed in the present invention, which are all within the content of the technical solution of the present invention and still belong to the protection scope of the present invention.
Claims
1. A test method for a split-gate flash memory, characterized in that, Including: Providing a substrate and forming an active region within the substrate; Forming a gate structure on the surface of a part of the active region, the gate structure including a floating gate located on the surface of the active region, a first sidewall located on the surface of the floating gate, a word line located between the openings formed by the floating gate, and a second sidewall separating both the first sidewall and the floating gate from the word line; Sequentially forming a memory gate and gate polysilicon on the surface of the gate structure, with the gate polysilicon exposing a part of the surface of the memory gate, and the gate polysilicon, the memory gate, and the gate structure all exposing a part of the surface of the active region; Forming a first via structure on the gate polysilicon, forming a second via structure on the exposed memory gate, and forming a third via structure on the exposed active region; Testing a first capacitance between the first via structure and the second via structure or testing a second capacitance between the second via structure and the third via structure, and determining whether the first capacitance is within a first set value, determining whether the second capacitance is within a second set value, determining whether the sum of the first capacitance and the second capacitance is within a third set value. If the sum of the first capacitance and the second capacitance is within the set values, it is considered that the active region is over-etched during the formation of the memory gate. If the second capacitance is within the set value, it is considered that the gate polysilicon is still... When the sum of the first capacitance and the second capacitance is within the third set value, it is determined that the active region is over-etched during the formation of the floating gate. When the first capacitance is outside the first set value and the second capacitance is within the second set value, it is determined that the active region is over-etched during the formation of the gate polysilicon. When the first capacitance is within the first set value and the second capacitance is outside the second set value, it is determined that the active region is over-etched during the formation of the memory gate.
2. The test method of the split-gate flash memory according to claim 1, wherein The gate structure further includes: a gate oxide layer located between the active region and the floating gate.
3. The test method for the split-gate flash memory according to claim 1, characterized in that, The gate structure further includes: a word line protection layer located on the surface of the word line.
4. The test method of the split-gate flash memory according to claim 1, characterized in that, After forming the gate structure on the surface of the active region, it further includes: Forming a first interlayer dielectric layer on the surface of the gate structure.
5. The test method of the split-gate flash memory according to claim 1, wherein After forming the memory gate on the surface of the gate structure, it further includes: Forming a second interlayer dielectric layer on the surface of the memory gate.
6. The test method of the split-gate flash memory according to claim 1, characterized in that There are multiple gate structures, and adjacent gate structures expose a part of the surface of the active region.
7. The test method of the split-gate flash memory according to claim 6, characterized in that, The gate polysilicon on adjacent gate structures exposes the surface of the memory gate on the active region between adjacent gate structures.
8. The testing method of the split-gate flash memory according to claim 1, characterized in that, The method for forming the floating gate includes: Forming a floating gate material layer on the surface of the active region; After forming the word line, etching the floating gate material layer to form the floating gate.
9. The test method of the split-gate flash memory according to claim 1, wherein The method for forming the memory gate includes: Forming a polysilicon material layer on the surface of the gate structure; Etching the polysilicon material layer to form the memory gate.
10. The test method for the split-gate flash memory according to claim 1, characterized in that, The method for forming the gate polysilicon includes: Forming a polysilicon material layer on the surface of the memory gate; Etching the polysilicon material layer to form the gate polysilicon.