Preparation method of surface acoustic wave filter integrated with CMOS (complementary metal oxide semiconductor) process

Abstract

The invention relates to a preparation method of a surface acoustic wave filter integrated with a CMOS (Complementary Metal Oxide Semiconductor) process, which comprises the following steps of: preparing a CMOS radio-frequency signal processing circuit by using a silicon or silicon carbide substrate, combining a dielectric buffer layer with a piezoelectric material, and then depositing a metal interdigital structure on the surface of the piezoelectric material to prepare the surface acoustic wave filter. A passivation layer is deposited on the surface of the filter to protect the filter structure, finally a metal interconnection line and the passivation layer are prepared above the filter, and in order to not affect the performance of the filter, an air cavity is prepared between the passivation layer and the metal interconnection layer of the filter, so that the passivation layer and the metal interconnection layer are effectively isolated. According to the preparation method, the surface acoustic wave filter and the CMOS radio frequency circuit can be integrated, the problem that radio frequency front-end and rear-end signal processing cannot be integrated at the same time at present is solved, and the preparation method plays an important role in promoting development of a radio frequency chip in the directions of high integration, low cost, miniaturization and the like; and the radio frequency chip has wide practical value and economic value in the radio frequency chip application field.

Description

Technical Field

[0001] The present invention belongs to the field of filters, and particularly relates to a preparation method of a surface acoustic wave filter integrally integrated with a CMOS process. Background Art

[0002] Surface acoustic wave filters have the advantages of low power consumption, high operating frequency, high stability and reliability, etc., and are widely used in the fields of mobile communication, electronic industry, microfluidics, and various biological and environmental sensors. With the communication entering the 5G or future 6G era, the number of frequency bands that communication devices need to support is increasing. For example, more than 90 filters are implanted in the RF-FEM chips of current high-end smartphones, and this number will continue to grow to more than 100 in the next few years. However, due to market and ergonomic reasons, the volume of existing communication devices, especially the size of mobile communication devices, has been restricted. At present, the main way to solve this problem is to integrate filters, switches, power amplifiers, etc. into a radio frequency front-end module to save the main board space of communication devices. However, limited by the volume requirements of the radio frequency module, the volume of communication devices cannot be further reduced with the increase in the number of filters. Especially with the advent of a new round of information technology revolution, the application fields of filters will be further expanded, such as future multi-terminal Internet of Things, VR entertainment, wearable communication products, micro terminals, etc., which makes the development of radio frequency chips towards miniaturization, low cost, and high integration an inevitable trend in the future.

[0003] Facing the above problems, integrating acoustic filters and radio frequency integrated circuits is the target technology to meet the area and performance requirements of the next generation of 5 GHz and sub-6 GHz. Such technologies mainly include 3D integration technology and integrated integration technology. Among them, the 3D integration technology is also limited by the volume of radio frequency integrated circuit chips and filters. It needs to be integrated through thinning technology, and its preparation process flow is complex, with high difficulty and increased reliability risks. Therefore, the preparation cost of such chips is relatively high. And the integrated integration technology has been stagnant due to the inability to bond piezoelectric single crystal materials with the wafer prepared with CMOS radio frequency circuits, and can only be studied under the condition of low-temperature deposition of piezoelectric materials. Summary of the Invention

[0004] In order to solve the problems in the background art, the present invention provides a preparation method of a surface acoustic wave filter integrally integrated with a CMOS process, which makes full use of the advantages of the CMOS process and designs a preparation process of a surface acoustic wave filter that can be integrally integrated with the CMOS process, including:

[0005] S1: Spin-coat photoresist on a substrate suitable for the CMOS process, and release the activation region where transistors need to be prepared through photolithography and development techniques; and complete the preparation of the N-well or P-well region in the activation region through light doping ion implantation;

[0006] S2: After removing the photoresist, cleaning and drying, SiO2 is deposited on the upper surface of the N-well or P-well region as a gate oxide layer;

[0007] S3: using a low-temperature physical vapor deposition method to deposit a certain thickness of polysilicon material on the upper surface of the gate oxide layer, and then immersing Si compounds on the surface of the polysilicon material for metallization to form a metallized polysilicon layer;

[0008] S4: Spin-coating photoresist on the metallized polysilicon layer, and exposing the source and drain regions of the MOS tube above the N-well or P-well region by exposure and development, and completing the preparation of the transistor source and drain regions in the N-well or P-well region by ion implantation and rapid thermal annealing process;

[0009] S5: After removing the photoresist, cleaning and drying, depositing a first SiO2 layer on the metallized polysilicon layer by CVD technology, and bonding the LiTaO3 piezoelectric single crystal to the upper surface of the first SiO2 layer;

[0010] S6: etching a first through hole on the upper surface of the LiTaO3 piezoelectric single crystal by photoresist, photolithography, development, and etching, and filling the first through hole with a metal material to connect the source, drain, gate, and filter electrode of the MOS tube;

[0011] S7: A filter structure is prepared on the upper surface of the LiTaO3 piezoelectric single crystal through photolithography, development processes, and a metal thin film material is deposited to prepare a filter, and the filter electrode is connected to the metal in the first through hole; and a second SiO2 layer and a first Si3N4 layer are deposited on the filter through physical vapor deposition as a first passivation layer to protect the filter structure and improve the reliability of the filter;

[0012] S8: spin coating or depositing a polyimide sacrificial layer on the first passivation layer, and then depositing a third SiO2 layer on the sacrificial layer by using a HDPCVD method, and then removing the sacrificial layer by using a degumming solution to form an air isolation cavity;

[0013] S9: performing photoresist, photolithography, development, and etching processes on the third SiO2 layer to complete the preparation of the second through hole, and depositing metal in the second through hole for connecting the filter electrode and the metal wire layer;

[0014] S10: preparing a metal wire layer pattern on the third SiO2 layer by photoresist, photolithography, and development, and depositing a metal film by physical vapor deposition to complete the preparation of the metal wire layer, and repeating steps S9-S10 to complete the preparation of multiple metal wire layers and the connection between the multiple metal wire layers;

[0015] S11: Deposit a second passivation layer on top of the top metal wire layer, and form a third via by etching on top of the second passivation layer for releasing the metal electrodes of the top metal wire layer.

[0016] Preferably, after the bonding of the LiTaO3 piezoelectric single crystal and the first SiO2 layer is completed, the upper surface of the LiTaO3 piezoelectric single crystal is planarized by chemical mechanical polishing so that the standard deviation of its thickness is less than 5 nm.

[0017] Preferably, the substrate applicable to the CMOS process includes: P-type, N-type, intrinsic silicon substrate, SiC substrate, AlN substrate, GaN or GaAs substrate for the preparation of CMOS integrated circuit process, and the CMOS process includes radio frequency CMOS integration process, digital-analog CMOS integration process, BiCMOS integration process, HV-CMOS integration process, HKMG integration process, SOI-CMOS integration process or FinFET integration process.

[0018] Preferably, depositing SiO2 as the gate oxide layer on the upper surface of the N-well or P-well region includes: forming a layer of SiO2 with a thickness of 3 nm to 10 nm on the surface by wet oxidation at a temperature of 800 °C to 1000 °C, and then oxidizing Si by dry oxidation to form a gate oxide layer with good texture, structure and uniformity.

[0019] Preferably, the method of bonding the upper surfaces of the LiTaO3 piezoelectric single crystal and the first SiO2 layer includes: direct wafer bonding method, plasma-activated bonding method, surface-activated bonding method, polymer wafer bonding method, physical vapor deposition method, chemical vapor deposition method, sol-gel method, pulsed laser deposition method, radio frequency sputtering method and molecular beam epitaxy method.

[0020] Preferably, the metal materials used to fill the first via, the second via and the third via include: Al and Cu.

[0021] Preferably, the filter includes: a single filter structure or multiple filter structures, and its filter type includes one or more of SAW, BAW, FSAW and FBAW.

[0022] Preferably, the thicknesses of the first passivation layer and the second passivation layer are 800 nm to 1500 nm.

[0023] The present invention has at least the following beneficial effects

[0024] (1) The surface acoustic wave filter designed based on the CMOS process can be integrated with the radio frequency backend signal processing circuit, and the design method and preparation process are simple, which is beneficial to further reducing the manufacturing cost of the radio frequency chip.

[0025] (2) The surface acoustic wave filter designed based on CMOS process can be fabricated and integrated simultaneously with antennas, amplifiers, etc. in the RF front-end, and can be wafer-level packaged with them, greatly reducing the area of the RF chip.

[0026] (3) This type of surface acoustic wave filter can not only fabricate and integrate multiple surface acoustic wave filters simultaneously, but also fabricate and integrate surface acoustic wave filters and bulk acoustic wave filters simultaneously, providing new design and integration ideas for the development of future 5G, 6G, and millimeter-wave communication chips. Description of the Drawings

[0027] Figure 1 is the substrate for preparing N-well or P-well;

[0028] Figure 2 is the substrate for depositing polysilicon and source / drain;

[0029] Figure 3 is the structure after preparing the piezoelectric layer;

[0030] Figure 4 is the structure after fabricating the filter and depositing the passivation layer;

[0031] Figure 5 is the structure after depositing the sacrificial layer and SiO2 dielectric layer;

[0032] Figure 6 is the structure for depositing the metal interconnect layer, dielectric layer, and passivation layer. Detailed Embodiments

[0033] The following specific examples illustrate the embodiments of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the drawings provided in the following embodiments only illustrate the basic concept of the present invention schematically. Without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0034] Among them, the drawings are only for illustrative purposes, showing only schematic diagrams, not physical diagrams, and should not be construed as a limitation to the present invention; for better illustrating the embodiments of the present invention, some components in the drawings will be omitted, enlarged, or reduced, which do not represent the dimensions of the actual product; for those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.

[0035] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components; in the description of the present invention, it should be understood that if there are terms such as "upper", "lower", "left", "right", "front", "rear", etc. indicating the orientation or positional relationship, they are based on the orientation or positional relationship shown in the accompanying drawings. This is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, the terms describing the positional relationship in the accompanying drawings are only for illustrative purposes and cannot be construed as limitations on the present invention. For those of ordinary skill in the art, the specific meanings of the above terms can be understood according to specific circumstances.

[0036] Please refer to Figures 1 to 6 , this embodiment provides a method for preparing a surface acoustic wave filter integrated with a CMOS process, including: a silicon substrate, a dielectric buffer layer, a piezoelectric material layer, a filter layer, an air cavity, a dielectric layer, a metal interconnection layer, and a chip surface passivation layer; the silicon substrate is generally the silicon substrate required for the CMOS process, used to prepare a radio frequency signal processing circuit and connect the circuit to the filter; the dielectric buffer layer refers to the dielectric material located below the piezoelectric material, mainly used to reduce the surface stress between the substrate material and the piezoelectric material; the filter layer mainly refers to the surface acoustic wave filter composed of metal interdigital structures deposited on the piezoelectric layer and connects it to the signal processing circuit; the air cavity is located between the filter and the dielectric layer above the filter, mainly used to isolate the filter and the dielectric material and improve the electromechanical coupling coefficient between the interdigital structure and the piezoelectric material; the dielectric layer refers to the dielectric material located between the air cavity and the metal interconnection layer, mainly used for electrical isolation between metal wires; the metal interconnection layer is mainly used for signal connection and transmission between signal processing circuits; the chip surface passivation layer mainly refers to the passivation dielectric layer deposited on the chip surface to improve the high-temperature resistance, corrosion resistance, impact resistance, and oxidation resistance of the chip; this preparation method mainly includes light doping, ion implantation, gate oxide layer deposition, polysilicon deposition and metallization, dry and wet etching, buffer layer deposition, piezoelectric material bonding, filter structure preparation, passivation layer deposition, dielectric layer and metal interconnection layer deposition, and finally completes the preparation of such chips.

[0037] As a preferred embodiment, the present invention provides a method for preparing a surface acoustic wave filter integrated with a CMOS process, including:

[0038] S1: Spin-coat a photoresist 102 on a substrate 101 suitable for the CMOS process, and release the activation region where transistors need to be prepared through photolithography and development techniques; and complete the preparation of the N-well or P-well region 103 in the activation region through light doping ion implantation;

[0039] Preferably, the substrate 101 applicable to the CMOS process includes, but is not limited to, P-type, N-type, intrinsic silicon substrates, SiC substrates, AlN substrates, GaN or GaAs substrates, etc. used for the preparation of CMOS integrated circuit processes. The CMOS process includes, but is not limited to, radio frequency CMOS integration process, digital-analog CMOS integration process, BiCMOS integration process, HV-CMOS integration process, HKMG integration process, SOI-CMOS integration process or FinFET integration process, etc.

[0040] S2: Clean and dry to remove the photoresist 102, and deposit SiO2 on the upper surface of the N-well or P-well region 103 as the gate oxide layer 105;

[0041] Preferably, the deposition of SiO2 on the upper surface of the N-well or P-well region 103 as the gate oxide layer 105 includes: forming a layer of SiO2 with a thickness of 3 nm to 10 nm on the surface by wet oxidation at a temperature of 800 °C to 1000 °C, and then oxidizing Si by dry oxidation to form a gate oxide layer 105 with good texture, structure and uniformity.

[0042] S3: Deposit a certain thickness of polysilicon material on the upper surface of the gate oxide layer 105 by low-temperature physical vapor deposition method, and then immerse the silicide on the surface of the polysilicon material for metallization to form a metallized polysilicon layer 106;

[0043] Preferably, the thickness of the silicide immersed on the surface of the polysilicon material is 100 nm to 500 nm, and the silicide includes, but is not limited to, CoSi2, WSi2, NiSi2.

[0044] S4: Spin-coat the photoresist 107 on the metallized polysilicon layer 106, and expose and develop to expose the source and drain regions of the MOS transistor above the N-well or P-well region 103. Complete the preparation of the transistor source and drain regions 104 in the N-well or P-well region 103 through ion implantation and rapid thermal annealing processes;

[0045] S5: After cleaning and drying, remove the photoresist 107, deposit the first SiO2 layer 108 on the metallized polysilicon layer 106 by CVD technology, and bond the LiTaO3 piezoelectric single crystal 109 to the upper surface of the first SiO2 layer 108;

[0046] Preferably, this embodiment provides an implementation manner of step S5, including: depositing a certain thickness of undoped Si glass on the surface of the metallized polysilicon layer 106 by plasma-enhanced chemical vapor deposition method, and then depositing a certain thickness of SiO2 layer 108 by atmospheric pressure chemical vapor deposition method as the buffer layer 108 between the polysilicon layer and the piezoelectric material dielectric layer. The thickness of the undoped Si glass is 20 to 50 nm, and the thickness of the SiO2 is 300 nm to 700 nm.

[0047] Preferably, the method for bonding the LiTaO3 piezoelectric single crystal 109 to the upper surface of the first SiO2 layer 108 includes, but is not limited to, direct wafer bonding method, plasma-activated bonding method, surface-activated bonding method, polymer wafer bonding method, physical vapor deposition method, chemical vapor deposition method, sol-gel method, pulsed laser deposition method, radio frequency sputtering method, and molecular beam epitaxy method.

[0048] S6: Etch the first via hole 110 on the upper surface of the LiTaO3 piezoelectric single crystal 109 through spin coating, photolithography, development, and etching, and fill the metal material in the first via hole 110 for connecting the source, drain, gate of the MOS transistor, and the filter electrode;

[0049] S7: Prepare the filter structure on the upper surface of the LiTaO3 piezoelectric single crystal 109 through spin coating, photolithography, and development processes, deposit the metal thin film material to prepare the filter 111, and connect the filter electrode to the metal in the first via hole 110; and deposit the second SiO2 layer 112 and the first Si3N4 layer 113 on the filter 111 as the first passivation layer through physical vapor deposition method to protect the filter structure and improve the reliability of the filter;

[0050] Preferably, the filter 111 includes: a single filter structure or multiple filter structures, and its filter types include one or more of SAW, BAW, FSAW, and FBAW. The thickness of the metal thin film is 100 nm to 300 nm. The metal thin film includes a single metal film component, such as Al, Cu, Au, etc.; it also includes a composite film layer, such as Al / Cu / Al / Ti, Ti / AlCu / Ti, Ti / Cu / Ti / Al, etc.

[0051] Preferably, the first passivation layer material includes an inorganic passivation film mainly composed of SiO2 and Si3N4, and also includes an organic passivation film mainly composed of a silane coupling agent.

[0052] S8: Spin coat or deposit the polyimide sacrificial layer 114 on the first passivation layer, then deposit the third SiO2 layer 115 on the sacrificial layer 114 by HDP CVD method, and then remove the sacrificial layer 114 by the stripping solution to form the air isolation cavity 117;

[0053] Preferably, the sacrificial layer 114 mainly includes a support material mainly composed of polyimide, photoresist, polysilicon, etc.

[0054] S9: Complete the preparation of the second via hole 116 through spin coating, photolithography, development, and etching processes on the third SiO2 layer 115, and deposit metal in the second via hole 116 for connecting the filter electrode and the metal wire layer 118;

[0055] Preferably, the second through-hole 116 is made of Al and Cu, and is isolated from the side wall of the second through-hole 116 by TiN.

[0056] S10: On the third SiO2 layer 115, a metal wire layer pattern is prepared through spin coating, photolithography, and development, and a metal thin film is deposited by physical vapor deposition to complete the preparation of the metal wire layer 118. Steps S9 - S10 are repeatedly executed to complete the preparation of the multi-layer metal wire layer and the connection between the multi-layer metal wire layers; the metal thin film is mainly a metal thin film such as Al, AlCu, Cu, or Wu.

[0057] Preferably, the thickness of the third SiO2 layer 115 is 300 - 500 nm, and the thickness of the top layer metal is 500 nm - 2500 nm.

[0058] S11: A second passivation layer 126 is deposited on the top layer metal wire layer, and a third through-hole 127 is formed by etching on the second passivation layer 126 to release the metal electrode of the top layer metal wire layer.

[0059] Preferably, the second passivation layer 126 is generally a Si3N4 layer, and its thickness is 800 nm - 1500 nm.

[0060] Preferably, after the bonding of the LiTaO3 piezoelectric single crystal 109 and the first SiO2 layer 108 is completed, the upper surface of the LiTaO3 piezoelectric single crystal 109 is planarized by chemical mechanical polishing, so that the standard deviation of its thickness is less than 5 nm.

[0061] Preferably, the metal materials used to fill the first through-hole 110, the second through-hole 116, and the third through-hole 127 include: Al and Cu.

[0062] Preferably, the thickness of the first passivation layer and the second passivation layer 126 is 800 nm - 1500 nm.

[0063] In this embodiment, a structure stacked with multi-layer metal wire layers is provided, including: after the preparation of the metal wire layer in step S10, continue to deposit a SiO2 dielectric layer 119 on the metal wire layer, etch through-holes 120 on the SiO2 dielectric layer 119, repeat the etching and deposition steps on the surface of the above structure to complete through-holes 120 and through-holes 122, metal interconnect layers 121 and metal interconnect layers 124, SiO2 dielectrics 123 and SiO2 dielectrics 125, and finally deposit a Si3N4 passivation layer 126 on the surface of the chip, and release the metal electrode position 127 by etching the third through-hole 127 to complete the preparation of the chip.

[0064] In summary, the present invention grows a polysilicon layer and a SiO2 layer on a Si substrate, then bonds them to a piezoelectric material, prepares a surface acoustic wave filter on the surface of the piezoelectric material, and finally isolates the filter from the upper dielectric layer and wire connection layer through a sacrificial layer, thus finally completing the preparation of the filter structure. The polysilicon layer can effectively reduce the signal interference of the substrate carriers on the surface acoustic wave device. SiO2 not only plays an electrical isolation effect, but also can be used as a temperature compensation layer to reduce the temperature drift and power consumption of the device. The period of the interdigital transducer structure of this type of filter can be continuously reduced with the improvement of the semiconductor process, which is beneficial to the improvement of the filter performance. In addition, this structure can not only be integrated with switches, antennas, and low-noise amplifiers in the RF front-end at the same time, but also meet the conditions for wafer-level packaging, which can greatly reduce the area and cost of the RF front-end chip, and is the key technology for realizing the high integration of RF front-end chips in the future.

[0065] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principles of the present invention shall be included in the protection scope of the present invention.

[0066] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the purpose and scope of the present technical solution, and they should all be covered by the scope of the claims of the present invention.

Claims

1. A method for fabricating a surface acoustic wave filter integrated with a CMOS process, characterized in that, Including: S1: Spin-coat photoresist on a substrate (101) suitable for CMOS process, and release the active region where transistors need to be fabricated through photolithography and development techniques; and complete the preparation of the N-well or P-well region (103) in the active region through lightly doped ion implantation. S2: After removing the photoresist, clean and dry, and deposit SiO2 on the upper surface of the N-well or P-well region (103) as the gate oxide layer (105). S3: Use low-temperature physical vapor deposition method to deposit a certain thickness of polysilicon material on the upper surface of the gate oxide layer (105), and then immerse in silicide on the polysilicon material surface for metallization to form a metallized polysilicon layer (106). S4: Spin-coat photoresist on the metallized polysilicon layer (106), and expose the source and drain regions of the MOS transistor above the N-well or P-well region (103) through exposure and development. Complete the preparation of the transistor source and drain regions (104) in the N-well or P-well region (103) through ion implantation and rapid thermal annealing processes. S5: After removing the photoresist, clean and dry, deposit the first SiO2 layer (108) on the metallized polysilicon layer (106) through CVD technology, and bond the LiTaO3 piezoelectric single crystal (109) to the upper surface of the first SiO2 layer (108). S6: Etch the first through-hole (110) on the upper surface of the LiTaO3 piezoelectric single crystal (109) through spin-coating, photolithography, development, and etching, and fill the metal material in the first through-hole (110) for connecting the source, drain, gate, and filter electrodes of the MOS transistor. S7: Through spin-coating, photolithography, development processes on the upper surface of the LiTaO3 piezoelectric single crystal (109), prepare the filter structure, deposit the metal thin film material to prepare the filter (111), and connect the filter electrode to the metal in the first through-hole (110); and deposit the second SiO2 layer (112) and the first Si3N4 layer (113) on the filter (111) through physical vapor deposition method as the first passivation layer to protect the filter structure and improve the reliability of the filter. S8: Spin-coat or deposit the polyimide sacrificial layer (114) on the first passivation layer, then deposit the third SiO2 layer (115) on the sacrificial layer (114) using HDP CVD method, and then remove the sacrificial layer (114) through the deglue solution to form the air isolation cavity (117). S9: Perform spin-coating, photolithography, development, and etching processes on the third SiO2 layer (115) to complete the preparation of the second through-hole (116), and deposit metal in the second through-hole (116) for connecting the filter electrode and the metal wire layer (118). S10: Prepare the metal wire layer pattern on the third SiO2 layer (115) through spin-coating, photolithography, and development, and deposit the metal thin film using physical vapor deposition method to complete the preparation of the metal wire layer (118). Repeat steps S9 - S10 to complete the preparation of the multi-layer metal wire layer and the connection between the multi-layer metal wire layers. S11: Deposit a second passivation layer (126) on the top metal wire layer, and form a third via hole (127) by etching on the second passivation layer (126) to release the metal electrodes of the top metal wire layer.

2. The manufacturing method of a surface acoustic wave filter integrally integrated with a CMOS process according to claim 1, characterized in that, After bonding the LiTaO3 piezoelectric single crystal (109) and the first SiO2 layer (108), planarize the upper surface of the LiTaO3 piezoelectric single crystal (109) by chemical mechanical polishing to make the standard deviation of its thickness less than 5 nm.

3. The manufacturing method of a surface acoustic wave filter integrally integrated with a CMOS process according to claim 1, characterized in that, The substrate (101) applicable to the CMOS process includes: P-type, N-type, intrinsic silicon substrates, SiC substrates, AlN substrates, GaN or GaAs substrates for the preparation of CMOS integrated circuit processes. The CMOS process includes radio frequency CMOS integration process, digital-analog CMOS integration process, BiCMOS integration process, HV-CMOS integration process, HKMG integration process, SOI-CMOS integration process or FinFET integration process.

4. The preparation method of a surface acoustic wave filter integrally integrated with a CMOS process according to claim 1, characterized in that, Depositing SiO2 as the gate oxide layer (105) on the upper surface of the N-well or P-well region (103) includes: forming a layer of SiO2 with a thickness of 3 nm to 10 nm on the surface by wet oxidation at a temperature of 800 °C to 1000 °C, and then oxidizing Si by dry oxidation to form a gate oxide layer (105) with good texture, structure and uniformity.

5. The manufacturing method of a surface acoustic wave filter integrally integrated with a CMOS process according to claim 1, characterized in that The method of bonding the upper surfaces of the LiTaO3 piezoelectric single crystal (109) and the first SiO2 layer (108) includes: direct wafer bonding method, plasma-activated bonding method, surface-activated bonding method, polymer wafer bonding method, physical vapor deposition method, chemical vapor deposition method, sol-gel method, pulsed laser deposition method, radio frequency sputtering method and molecular beam epitaxy method.

6. The preparation method of a surface acoustic wave filter integrally integrated with a CMOS process according to claim 1, characterized in that, The metal materials for filling the first via hole (110), the second via hole (116) and the third via hole (127) include: Al and Cu.

7. The manufacturing method of a surface acoustic wave filter integrated with a CMOS process according to claim 1, characterized in that, The filter (111) includes: a single filter structure or multiple filter structures, and the filter types include one or more of SAW, BAW, FSAW and FBAW.

8. The manufacturing method of a surface acoustic wave filter integrally integrated with a CMOS process according to claim 1, characterized in that The thickness of the first passivation layer and the second passivation layer (126) is 800 nm to 1500 nm.

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