System memory management method and system, electronic equipment and storage medium

Abstract

According to the system memory management method and system, the electronic equipment and the storage medium provided by the invention, the virtual address information in the access information is extracted, and the virtual address information comprises the target virtual address; under the condition that the target virtual address is determined to be in a first preset virtual address range according to the virtual address information, determining an initial physical address corresponding to an initial virtual address in the first preset virtual address range according to a preset address mapping table; performing physical address calculation processing according to the target virtual address, the initial virtual address and the initial physical address to obtain a target physical address corresponding to the target virtual address; and accessing a system memory based on the target physical address and performing memory management on the system memory. By quickly returning the conversion relation from the virtual address to the physical address in the specified range, the conversion efficiency from the virtual address to the physical address can be improved, a conversion page table does not need to be configured according to MMU granularity, waste of storage space can be reduced, and the address conversion efficiency can be improved.

Description

Technical Field

[0001] The present disclosure relates to the technical field of data processing, and particularly to a method and system for system memory management, an electronic device, and a storage medium. Background Art

[0002] The Memory Management Unit (MMU) is located between the Central Processing Unit (CPU) and the memory in a computer system. Its main functions include virtual address to physical address translation, memory protection, control of the CPU cache, etc. The MMU can manage memory resources more effectively, support multitasking, and allow multiple programs to run simultaneously, with each program having its own memory space and execution environment.

[0003] In the application of the MMU, to store the address translation page table that maps virtual addresses (VA) to physical addresses (PA), a certain amount of memory space is occupied. At the same time, to speed up the processing speed, a part of the address translation page table is pre-cached in the MMU. However, when a cache miss occurs during access, it takes a long time to obtain the required address translation page table from the memory.

[0004] Furthermore, the address translation page table has long consecutive addresses. The existing memory management method is to configure the page table at the MMU granularity regardless of whether the addresses are consecutive, resulting in a high cache miss rate, which leads to waste of storage space and a decrease in address translation efficiency. Summary of the Invention

[0005] The present disclosure provides a method and system for system memory management, an electronic device, and a storage medium. Its main purpose is to solve the problem that the existing memory management method configures the page table at the MMU granularity regardless of whether the addresses are consecutive, resulting in a high cache miss rate, which leads to waste of storage space and a decrease in address translation efficiency.

[0006] According to a first aspect of the present disclosure, there is provided a method for system memory management, including: extracting virtual address information from the received access information, where the access information is used to access the system memory, and the virtual address information is used to indicate the target virtual address of the system memory; When it is determined that the target virtual address is within the first preset virtual address range according to the virtual address information, determine the starting physical address corresponding to the starting virtual address in the first preset virtual address range according to a preset address mapping table, where the first preset virtual address range includes a starting virtual address and an ending virtual address, and the preset address mapping table at least includes the starting physical address corresponding to the starting virtual address; Perform physical address calculation processing based on the target virtual address, the starting virtual address, and the starting physical address to obtain the target physical address corresponding to the target virtual address; Access the system memory based on the target physical address and perform memory management on the system memory.

[0007] Optionally, after extracting the virtual address information in the received access information, the method further includes: When it is determined that the target virtual address is not within the first preset virtual address range according to the virtual address information, perform physical address conversion processing on the target virtual address through a preset address conversion mode in the memory management unit to obtain the target physical address.

[0008] Optionally, after extracting the virtual address information in the received access information, the method further includes: Determine whether the target virtual address is within a second preset virtual address range according to the virtual address information; When it is determined that the target virtual address is within the second preset virtual address range, determine whether the target virtual address is within the first preset virtual address range according to the virtual address information; When it is determined that the target virtual address is not within the second preset virtual address range, determine that the target virtual address is incorrect and generate an error prompt message, where the second preset virtual address range includes the first preset virtual address range.

[0009] Optionally, before extracting the virtual address information in the received access information, the method further includes: Obtain continuous physical address information in the system memory, where the continuous physical address information includes multiple segments of continuous physical addresses in the system memory, and the multiple segments of continuous physical addresses do not overlap with each other; Perform virtual address range configuration processing on each of the multiple segments of continuous physical addresses to obtain a target virtual address range, where the first preset virtual address range includes the target virtual address ranges respectively corresponding to the configurations of the multiple segments of continuous physical addresses, and the multiple target virtual address ranges do not overlap with each other.

[0010] Optionally, the process of configuring virtual address ranges for the multiple segments of consecutive physical addresses respectively to obtain target virtual address ranges includes: Performing virtual address correspondence processing on the first starting physical address of the target consecutive physical address to obtain a first starting virtual address, where the target consecutive physical address is any one of the multiple segments of consecutive physical addresses; Performing virtual address correspondence processing on the first ending physical address of the target consecutive physical address to obtain a first ending virtual address; Determining the virtual address range between the first starting virtual address and the first ending virtual address as the target virtual address range, and storing the first starting physical address and the first starting virtual address corresponding to the first starting physical address into the preset address mapping table.

[0011] Optionally, the process of performing physical address calculation processing according to the target virtual address, the starting virtual address, and the starting physical address to obtain the target physical address corresponding to the target virtual address includes: Performing address subtraction calculation on the target virtual address and the starting virtual address to obtain an address deviation; Performing address addition calculation according to the address deviation and the starting physical address to obtain the target physical address.

[0012] Optionally, the method further includes: In the case of obtaining an invalid configuration instruction, performing invalidation processing on the second preset virtual address range to obtain an invalidated second preset virtual address range; In the case of determining that the target virtual address is within the invalidated second preset virtual address range, determining that the target virtual address is incorrect and generating an error prompt message.

[0013] According to a second aspect of the present disclosure, a system for system memory management is provided, including: an address translation module, a memory management unit, a processor, and a bus, The address translation module is configured between the memory management unit, the processor, and the bus, and is respectively connected to the memory management unit, the processor, and the bus; The address translation module is used to receive access information from the processor and extract the virtual address information in the received access information, where the access information is used to access the system memory, and the virtual address information is used to indicate the target virtual address of the system memory; The address translation module is further configured to, when determining that the target virtual address is within a first preset virtual address range according to the virtual address information, determine, from the memory management unit, a starting physical address corresponding to the starting virtual address in the first preset virtual address range, where the first preset virtual address range includes a starting virtual address and an ending virtual address, and the preset address mapping table includes at least the starting physical address corresponding to the starting virtual address; The address translation module is further configured to perform physical address calculation processing based on the target virtual address, the starting virtual address, and the starting physical address to obtain a target physical address corresponding to the target virtual address; The address translation module is further configured to transmit the target physical address to the bus; The bus is configured to access the system memory based on the target physical address and perform memory management on the system memory.

[0014] According to a third aspect of the present disclosure, there is provided an apparatus for system memory management, including: An extraction unit configured to extract virtual address information from the received access information, where the access information is used to access the system memory, and the virtual address information is used to indicate a target virtual address of the system memory; A determination unit configured to, when determining that the target virtual address is within a first preset virtual address range according to the virtual address information, determine a starting physical address corresponding to the starting virtual address in the first preset virtual address range according to a preset address mapping table, where the first preset virtual address range includes a starting virtual address and an ending virtual address, and the preset address mapping table includes at least the starting physical address corresponding to the starting virtual address; A calculation unit configured to perform physical address calculation processing based on the target virtual address, the starting virtual address, and the starting physical address to obtain a target physical address corresponding to the target virtual address; A processing unit configured to access the system memory based on the target physical address and perform memory management on the system memory.

[0015] According to a fourth aspect of the present disclosure, there is provided an electronic device, including: At least one processor; and A memory communicatively connected to the at least one processor; where The memory stores instructions executable by the at least one processor, and when the instructions are executed by the at least one processor, the at least one processor is enabled to execute the method described in the foregoing first aspect.

[0016] According to a fifth aspect of the present disclosure, there is provided a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to cause the computer to execute the method described in the foregoing first aspect.

[0017] According to a sixth aspect of the present disclosure, there is provided a computer program product including a computer program which, when executed by a processor, implements the method described in the foregoing first aspect.

[0018] The method and system for system memory management, electronic device and storage medium provided by the present disclosure extract virtual address information in received access information, wherein the access information is used to access the system memory, and the virtual address information is used to indicate a target virtual address of the system memory; when it is determined according to the virtual address information that the target virtual address is within a first preset virtual address range, a starting physical address corresponding to the starting virtual address in the first preset virtual address range is determined according to a preset address mapping table, wherein the first preset virtual address range includes a starting virtual address and an ending virtual address, and the preset address mapping table at least includes the starting physical address corresponding to the starting virtual address; physical address calculation processing is performed according to the target virtual address, the starting virtual address and the starting physical address to obtain a target physical address corresponding to the target virtual address; the system memory is accessed based on the target physical address and memory management of the system memory is performed. Compared with the related art, the embodiment of the present disclosure can improve the conversion efficiency from a virtual address to a physical address by quickly returning the conversion relationship of virtual addresses within a specified range to physical addresses, and there is no need to configure a translation page table according to the MMU granularity, which can reduce the waste of storage space and improve the address conversion efficiency.

[0019] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it used to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The drawings are used to better understand the solution and do not constitute a limitation to the present disclosure. Among them: Figure 1 is a flowchart of a method for system memory management provided by an embodiment of the present disclosure; Figure 2 is a structural diagram of a system for system memory management provided by an embodiment of the present disclosure; Figure 3 is a structural diagram of a device for system memory management provided by an embodiment of the present disclosure; Figure 4Schematic structural diagram of another system memory management device provided by an embodiment of the present disclosure; Figure 5 Schematic block diagram of an electronic device provided by an embodiment of the present disclosure. Detailed implementation manners

[0021] The following describes exemplary embodiments of the present disclosure with reference to the accompanying drawings. Various details of the embodiments of the present disclosure are included to facilitate understanding, and they should be considered merely exemplary. Therefore, those of ordinary skill in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, descriptions of well-known functions and structures are omitted below for clarity and conciseness.

[0022] The following describes the method and system for system memory management, electronic device, and storage medium according to embodiments of the present disclosure with reference to the accompanying drawings.

[0023] Figure 1 Schematic flowchart of a method for system memory management provided by an embodiment of the present disclosure.

[0024] As Figure 1 shown, the method includes the following steps: Step 101: Extract virtual address information from the received access information, where the access information is used to access the system memory, and the virtual address information is used to indicate the target virtual address of the system memory.

[0025] In an embodiment of the present disclosure, when the central processing unit (CPU) needs to access the system memory, access information including a virtual address is generated. The virtual address is a target address dynamically allocated within the logical address space during program execution. The system memory refers to the physical storage medium in a computer for storing data and instructions, including dynamic random access memory or other types of physical storage units.

[0026] Among them, extracting virtual address information from the received access information specifically refers to parsing the target virtual address included in the access request. The target virtual address is the virtual memory location that the program attempts to access. For example: a specific memory address that an application program needs to read or write during execution.

[0027] Step 102: When it is determined according to the virtual address information that the target virtual address is within a first preset virtual address range, determine the starting physical address corresponding to the starting virtual address in the first preset virtual address range according to a preset address mapping table, where the first preset virtual address range includes a starting virtual address and an ending virtual address, and the preset address mapping table includes at least the starting physical address corresponding to the starting virtual address.

[0028] In an embodiment of the present disclosure, the subsequent processing logic is determined by judging whether the target virtual address is within a preset first virtual address range. The first preset virtual address range is a predefined continuous virtual address interval defined jointly by a starting virtual address and an ending virtual address. The starting virtual address is the first address of this interval, for example: 0x1000_0000, and the ending virtual address is the last address of the interval, for example: 0x4200_0000. The preset address mapping table is a data structure storing key mapping relationships, and at least includes the starting physical address corresponding to the starting virtual address. The starting physical address is the first address of a continuous physical address space in the system memory, for example: 0x8000_0000. If the target virtual address falls within the first preset virtual address range, the system directly obtains the starting physical address by querying this mapping table without traversing the traditional page table level by level.

[0029] Step 103, perform physical address calculation processing according to the target virtual address, the starting virtual address, and the starting physical address to obtain the target physical address corresponding to the target virtual address.

[0030] In an embodiment of the present disclosure, according to the difference between the target virtual address and the starting virtual address, combined with the starting physical address, the final target physical address is generated through physical address calculation processing. Specifically, the target physical address is equal to the starting physical address plus the offset between the target virtual address and the starting virtual address. For example: if the target virtual address is 0x2089_8000, the starting virtual address is 0x1000_0000, and the starting physical address is 0x8000_0000, then the offset is 0x1089_8000, and the target physical address is 0x9089_8000. This calculation process can be implemented through hardware logic or a dedicated module, significantly reducing the processing cycles required for the traditional page table level-by-level query.

[0031] Step 104, access the system memory based on the target physical address and perform memory management on the system memory.

[0032] In an embodiment of the present disclosure, the obtained target physical address is used to directly access the system memory to complete data reading or writing operations. At the same time, the system performs memory management functions during this process, including but not limited to memory access permission verification, cache coherence maintenance, and address translation exception handling. The memory management unit (MMU) optimizes the cache policy and reduces redundant configurations for discontinuous physical address spaces by dynamically monitoring the access patterns of physical addresses. For example: when the target virtual address exceeds the preset range, that is, the first preset virtual address range, the system switches to the traditional MMU processing flow to ensure compatibility and flexibility.

[0033] Through the preset address mapping table and offset calculation mechanism, it avoids the waste of storage space caused by the fixed granularity of the traditional page table, and at the same time greatly reduces the cache miss rate. For application scenarios with long continuous physical addresses, this method covers the entire continuous range with a single mapping entry, reducing the overhead of page table level queries, thereby improving the address translation efficiency. In addition, the system can flexibly adapt to the allocation requirements of continuous physical addresses of different lengths, and can still operate efficiently in the scenario of physical memory fragmentation without forcibly allocating huge pages or sacrificing memory utilization.

[0034] The method for system memory management provided by the present disclosure extracts virtual address information from the received access information, where the access information is used to access the system memory, and the virtual address information is used to indicate the target virtual address of the system memory; when it is determined according to the virtual address information that the target virtual address is within a first preset virtual address range, the starting physical address corresponding to the starting virtual address in the first preset virtual address range is determined according to a preset address mapping table, where the first preset virtual address range includes a starting virtual address and an ending virtual address, and the preset address mapping table at least includes the starting physical address corresponding to the starting virtual address; physical address calculation processing is performed based on the target virtual address, the starting virtual address, and the starting physical address to obtain the target physical address corresponding to the target virtual address; the system memory is accessed based on the target physical address and memory management of the system memory is performed. Compared with the related art, the embodiment of the present disclosure can improve the conversion efficiency from a virtual address to a physical address by quickly returning the conversion relationship between virtual addresses within a specified range to physical addresses, and there is no need to configure a translation page table according to the MMU granularity, which can reduce the waste of storage space and improve the address translation efficiency.

[0035] In an implementable manner of the embodiment of the present disclosure, after extracting the virtual address information from the received access information, the following manner can also be adopted but is not limited to: when it is determined according to the virtual address information that the target virtual address is not within the first preset virtual address range, physical address conversion processing is performed according to the target virtual address through a preset address conversion mode in the memory management unit to obtain the target physical address.

[0036] In an embodiment of the present disclosure, when the target virtual address is not within the first preset virtual address range, a preset address translation mode of the Memory Management Unit (MMU) will be used for physical address translation. The preset address translation mode refers to the traditional multi-level page table query mechanism, which relies on the page table structure built into the MMU to implement the mapping from virtual address to physical address. The memory management unit is a hardware module in a computer system responsible for address translation, memory protection, and cache control. It stores the mapping relationship between virtual addresses and physical addresses through multi-level page tables (such as page directories, page table entries, etc.). In this mode, the patent module will directly forward the virtual address request sent by the bus to the MMU, and the MMU will parse the target virtual address level by level according to the currently activated page table. For example, if the target virtual address is 0x5200_0000 and this address is not included in the configured continuous virtual address range, that is, within the first preset virtual address range, the offset calculation will no longer be performed, but the address request will be passed through to the MMU. The MMU locates the corresponding physical page frame number layer by layer by querying its cache (such as the Translation Lookaside Buffer (TLB)) or the page table in memory, and finally combines to obtain the complete physical address. After the MMU completes the conversion, the generated physical address will be returned to the bus to access the system memory.

[0037] The hybrid processing mechanism ensures that the system can not only utilize the efficient continuous address translation ability but also be compatible with non-continuous or scattered physical address spaces through the traditional page table mode, thus maintaining the overall conversion efficiency and resource utilization rate in complex memory allocation scenarios. By dynamically switching the translation strategy, the over-reliance on the continuity of physical addresses by a single mapping mechanism is avoided, enabling the system to flexibly handle the memory fragmentation problem while reducing the mandatory requirement for large page allocation. For non-continuous address regions, although using traditional page table translation may introduce a certain query delay, through the collaborative work of the patent module and the MMU, the system can still maintain the high efficiency and stability of overall memory management, avoiding memory resource waste or increased configuration complexity caused by forcibly expanding the continuous mapping range.

[0038] In an implementable manner of the embodiments of the present disclosure, after extracting the virtual address information from the received access information, the following manner can be adopted but is not limited to: determining whether the target virtual address is within a second preset virtual address range according to the virtual address information; in the case where it is determined that the target virtual address is within the second preset virtual address range, determining whether the target virtual address is within the first preset virtual address range according to the virtual address information; in the case where it is determined that the target virtual address is not within the second preset virtual address range, determining that the target virtual address is incorrect and generating an error prompt message, wherein the second preset virtual address range includes the first preset virtual address range.

[0039] In the embodiments of the present disclosure, after extracting the virtual address information, an hierarchical verification process of the address range is further performed to enhance the security and processing efficiency of memory access. The second preset virtual address range is a globally valid virtual address interval defined in advance, which covers the first preset virtual address range and extends outward to a larger logical address boundary. For example: if the first preset virtual address range is from 0x1000_0000 to 0x4200_0000 (corresponding to a continuous physical address mapping area), the second preset virtual address range may be set to 0x0000_0000 to 0x5000_0000 (including all virtual addresses allowed for application programs to access). Through the dual-range verification mechanism, it is ensured that the target virtual address is both within the legal interval globally allowed for system access and further determines whether it falls within the continuous mapping area that requires special processing.

[0040] When it is determined that the target virtual address is within the second preset virtual address range, the original process will continue, that is, further determining whether it belongs to the first preset virtual address range. If it belongs, the offset calculation logic will be triggered; if it does not belong, the traditional MMU page table conversion mode will be switched. For example: when the target virtual address is 0x3000_0000, if the address is within the second preset virtual address range but not within the first preset virtual address range, the conversion will be directly completed by querying the page table through the MMU. If the target virtual address exceeds the second preset virtual address range (for example: 0x6000_0000), the address conversion process will be immediately terminated, determining that the access request is illegal, and generating an error prompt message. The error prompt message is an abnormal signal feedback by the system, including but not limited to: error type code (such as: address out-of-bounds error) and the virtual address value that triggers the exception. This information can be notified to the operating system or upper-layer applications through the interrupt mechanism for error handling.

[0041] By introducing a hierarchical verification mechanism for the second preset virtual address range, it is possible to filter illegal or out-of-bounds virtual address access requests at an early stage, avoiding resource waste caused by invalid addresses entering the subsequent conversion process. For example, when an application attempts to access an unallocated virtual address due to a programming error, it can be intercepted and reported at the first range verification stage without triggering the page table query or calculation logic of the MMU. This not only reduces the load on the memory management unit caused by illegal access but also shortens the error response time. In addition, the global definition of the second preset virtual address range enables the system to flexibly configure access permissions at different levels. For example, the first preset virtual address range can be set as a dedicated continuous memory area for high-priority tasks, while the second preset virtual address range covers the scattered memory areas of ordinary tasks, thereby achieving fine-grained control of resource allocation. While ensuring efficient processing of continuous address mapping, it strengthens the system's defense against abnormal access and improves the overall robustness of memory management.

[0042] In an implementable manner of the embodiments of the present disclosure, before extracting the virtual address information in the received access information, it is necessary to configure a preset virtual address range and a preset address mapping table. Specifically, the following methods can be used but are not limited to: obtaining the continuous physical address information in the system memory, where the continuous physical address information includes multiple segments of continuous physical addresses in the system memory, and the multiple segments of continuous physical addresses do not overlap with each other; performing virtual address range configuration processing on each of the multiple segments of continuous physical addresses to obtain a target virtual address range, where the first preset virtual address range includes the target virtual address ranges corresponding to each of the multiple segments of continuous physical addresses configured respectively, and the multiple target virtual address ranges do not overlap with each other.

[0043] In the embodiments of the present disclosure, during the initialization stage or the dynamic memory allocation process, the physical memory layout is actively scanned to identify available continuous physical address spaces. The continuous physical address information refers to multiple physically independent and non-overlapping physical address segments parsed from the system memory, and each address segment is defined by a starting physical address and a length. For example, the system may detect that the physical address range from 0x8000_0000 to 0xB200_0000 is a continuous space of 800 megabytes (MB), and there are three 50MB continuous spaces starting from 0xC000_0000, 0xD000_0000, and 0xE000_0000 respectively. These physical address segments are obtained through interfaces provided by the memory controller or the operating system kernel, and their distribution may be affected by hardware architecture limitations or dynamic memory allocation policies.

[0044] Perform virtual address range configuration processing on each continuous physical address segment. This processing refers to dynamically allocating a corresponding virtual address range, i.e., the target virtual address range, for each physical address segment, and ensuring that the virtual address ranges do not overlap within the logical address space. For example: map an 800MB physical segment to the virtual address range from 0x1000_0000 to 0x4200_0000, and map three 50MB physical segments to the ranges from 0x5000_0000 to 0x5320_0000, from 0x5400_0000 to 0x5720_0000, and from 0x5800_0000 to 0x5B20_0000 respectively. The target virtual address range is a set of virtual-physical mapping relationships formed after configuration, and each of its elements corresponds to a continuous physical address segment and its bound virtual address range. The first preset virtual address range consists of multiple such target virtual address ranges. For example: the union of the above four ranges.

[0045] During the configuration process, establish a linear relationship between virtual addresses and physical addresses through a preset strategy (such as: linear mapping in the order of physical addresses or customizing offsets according to application requirements), and write key mapping parameters (such as: the start and end addresses of each target virtual address range and the corresponding start physical address) into the configuration register or a dedicated storage structure. This preprocessing mechanism enables efficient conversion by quickly identifying continuous regions based on the preconfigured mapping rules during subsequent virtual address access.

[0046] By actively analyzing the physical memory continuity and dynamically configuring multi-segment virtual address mapping, the system can still maximize the advantages of continuous address conversion even when the physical memory is fragmented, avoiding the problem of being forced to fallback to small-granularity page table queries due to discontinuous physical memory in traditional solutions. At the same time, the non-overlapping virtual address configuration eliminates the risk of mapping conflicts, ensuring the determinacy of the address conversion process. This preprocessing mechanism also reduces the overhead of dynamically adjusting mapping relationships at runtime, enabling the system to adapt to complex and changing physical memory allocation scenarios. For example: quickly reconstructing an efficient mapping relationship during virtual machine migration or real-time task scheduling without interrupting services or reloading the entire page table.

[0047] In an implementable manner of the embodiments of the present disclosure, for the virtual address range configuration processing of the multiple consecutive physical addresses, the following manner can be adopted but is not limited thereto: perform virtual address correspondence processing on the first starting physical address of the target consecutive physical address to obtain the first starting virtual address, where the target consecutive physical address is any one of the multiple consecutive physical addresses; perform virtual address correspondence processing on the first ending physical address of the target consecutive physical address to obtain the first ending virtual address; determine the virtual address range between the first starting virtual address and the first ending virtual address as the target virtual address range, and store the first starting physical address and the first starting virtual address corresponding to the first starting physical address in the preset address mapping table.

[0048] In the embodiments of the present disclosure, the virtual address range configuration process for multiple consecutive physical addresses is achieved by establishing a linear mapping relationship between virtual addresses and physical addresses, thereby ensuring the efficiency and predictability of the conversion process. The target consecutive physical address refers to any consecutive physical address space identified from the system memory. For example: a physical segment starting from 0x8000_0000 and having a length of 800MB. The first starting physical address is the starting position of this physical segment, for example: 0x8000_0000, and the first ending physical address is the end address of this segment, for example: 0xB200_0000 (calculated by adding the starting address and the length). The virtual address correspondence processing refers to allocating a corresponding virtual address range for the consecutive physical address segment, and its mapping rule generally follows the linear offset principle, that is, the virtual address and the physical address maintain a fixed offset. For example: if it is selected to map the starting address 0x8000_0000 of the physical segment to the virtual address 0x1000_0000, then the first starting virtual address is 0x1000_0000. Similarly, the first ending virtual address is calculated by the length of the physical segment and the virtual starting address. For example: 0x1000_0000 plus 800MB gives 0x4200_0000. The target virtual address range is the virtual address range determined therefrom (from 0x1000_0000 to 0x4200_0000), which forms a one-to-one linear mapping relationship with the physical segment.

[0049] It should also be noted that the multiple consecutive physical addresses are not continuous, that is, the multiple consecutive physical addresses do not overlap or adjoin each other, indicating that there is a break between the target segment of the multiple consecutive physical addresses and other segments of the multiple consecutive physical addresses. The target segment of the multiple consecutive physical addresses is any one of the multiple consecutive physical addresses, and other segments of the multiple consecutive physical addresses are each segment of the multiple consecutive physical addresses except the target segment of the multiple consecutive physical addresses.

[0050] During this process, the first starting physical address (0x8000_0000) and its corresponding first starting virtual address (0x1000_0000) are stored as key mapping entries in a preset address mapping table. The preset address mapping table is an optimized data structure, usually implemented in the form of a register bank or a dedicated cache. It only stores the mapping relationships of the starting addresses of each continuous physical segment, rather than the detailed entries of all pages in a traditional page table. For example: for the above 800MB physical segment, only the entry 0x1000_0000 (virtual) → 0x8000_0000 (physical) needs to be recorded in the mapping table, without the need to configure each 4-kilobyte (KB) page separately. This configuration method can significantly reduce the storage overhead, and at the same time, when performing address conversion, based on the mapping relationship of the starting address, the target physical address can be quickly generated through simple offset calculation. For other continuous physical segments (such as: three 50MB physical segments), the same process is repeated, non-overlapping virtual address ranges are allocated for them respectively, and the starting address mapping relationships of each segment are appended to the preset address mapping table. In this way, multiple continuous regions scattered in physical memory can be flexibly adapted without the need to forcibly merge them into a single large page.

[0051] Specifically, the content in the preset address mapping table can be expressed as: in the preset address mapping table, it includes the first starting physical addresses of multiple continuous physical addresses, and the first starting virtual addresses corresponding to each of the multiple first starting physical addresses. The multiple first starting physical addresses at least include the starting physical address, and the multiple first starting virtual addresses at least include the starting virtual address.

[0052] When obtaining the target physical address, it can also be achieved by, but not limited to, the following methods: based on the first preset virtual address range where the target virtual address is located, determine the starting virtual address from the multiple first starting virtual addresses in the preset address mapping table; perform address offset calculation processing according to the target virtual address, the starting virtual address, and the starting physical address corresponding to the starting virtual address in the preset address mapping table to obtain the target physical address.

[0053] Through the linear mapping rule and the streamlined mapping table design, the occupation of storage resources by the traditional multi-level page table is significantly reduced, and at the same time, the mapping efficiency decline caused by physical memory fragmentation is avoided. For example: in a scenario where there are four non-continuous physical segments, only four entries need to be maintained in the mapping table to cover all continuous regions, while a traditional page table may require thousands of entries. In addition, the non-overlapping nature of the virtual address ranges ensures the uniqueness and certainty of the address conversion process, eliminates the risk of mapping conflicts, and thus improves system stability.

[0054] In an implementable manner of the embodiments of the present disclosure, when performing physical address calculation processing based on the target virtual address, the starting virtual address, and the starting physical address, the following manner can be adopted but is not limited to: performing an address subtraction calculation on the target virtual address and the starting virtual address to obtain an address deviation; performing an address addition calculation on the address deviation and the starting physical address to obtain the target physical address.

[0055] In the embodiments of the present disclosure, in physical address calculation processing, a fast conversion from a virtual address to a physical address is achieved through a linear operation mechanism, and the virtual address offset is directly added to the corresponding physical base address by using a preset continuous mapping relationship. Address subtraction calculation refers to performing an arithmetic subtraction operation on the target virtual address and the starting virtual address to determine the logical offset therebetween. For example: if the target virtual address is 0x2089_8000 and the starting virtual address is 0x1000_0000, the address deviation is 0x1089_8000 (i.e., 0x2089_8000 - 0x1000_0000). The address deviation represents the offset distance of the target virtual address relative to the starting position of the first preset continuous virtual address range, and essentially is a relative displacement amount within the virtual address space.

[0056] Address addition calculation is to perform an arithmetic addition operation on the calculated address deviation and the starting physical address, thereby converting the offset in the virtual space into the actual position in the physical space. For example: if the starting physical address is 0x8000_0000, after adding the address deviation 0x1089_8000, the target physical address is 0x9089_8000.

[0057] The linear calculation mechanism significantly improves the conversion efficiency of continuous address ranges by eliminating the hierarchical traversal overhead of traditional page table lookups. The operations of address subtraction and addition only require several clock cycles at the hardware level, and the performance improvement is particularly significant compared to the hundreds of cycle delays required for traditional MMUs to load multi-level page tables from memory when page table misses occur. In addition, the need to store redundant page table entries is avoided through the direct mapping relationship. For example: for a 1 Gigabyte (GB) continuous address space, a traditional 4KB page table needs to store 262,144 entries, while the present disclosure only needs to maintain a single mapping relationship between the starting virtual address and the starting physical address, greatly reducing the storage resource occupancy.

[0058] The dynamic calculation feature of address deviation enables the system to flexibly adapt to continuous physical address allocations of different lengths. Even when the physical segment length varies randomly (e.g., 800MB or 50MB), only the starting address configuration needs to be updated without reconstructing the entire page table. This mechanism is particularly important in scenarios of physical memory fragmentation. By configuring multiple independent continuous mapping intervals, scattered physical segments can be efficiently mapped to the virtual space while maintaining the consistency of the conversion process. For example, in a scenario with four non - continuous physical memory segments, full - range coverage can be achieved through four independent sets of start - and - end address configurations, while traditional solutions may result in decreased cache utilization due to page - table granularity limitations. The calculation mode also enhances the system real - time performance through a deterministic operation path, ensuring that memory access for critical tasks can meet strict timing requirements. For example, when handling high - priority interrupts in a real - time operating system, the response delay introduced by the uncertainty of page - table queries can be avoided.

[0059] In an implementable manner of the embodiment of the present disclosure, when the system receives an invalid configuration, that is, an invalid configuration, it is necessary to turn off the current forwarding function, that is, the address conversion function. When a subsequent access request for this range is received, an error is prompted. Specifically, but not limited to the following methods: when an invalid configuration instruction is obtained, the second preset virtual address range is invalidated to obtain an invalidated second preset virtual address range; when it is determined that the target virtual address is within the invalidated second preset virtual address range, it is determined that the target virtual address is incorrect, and an error prompt message is generated.

[0060] In the embodiment of the present disclosure, during the operation of the system, if an invalid configuration instruction is received (e.g., a memory - area disabling command triggered by an operating system or a security module), a dynamic adjustment process for the second preset virtual address range will be triggered. The invalid configuration instruction is an externally input control signal that contains an identifier of the virtual address range to be invalidated or security - policy parameters. For example, it requires immediately prohibiting the access permission to a certain virtual - address segment. The invalidation process refers to modifying the validity status of the second preset virtual address range according to the instruction content. For example, some or all sub - intervals in the original second range (e.g., from 0x0000_0000 to 0x5000_0000) are marked as inaccessible.

[0061] When it is detected that the target virtual address falls within the invalidated second preset virtual address range (e.g., the address 0x3500_0000 is within the disabled range from 0x3000_0000 to 0x4000_0000), the address - conversion process is immediately terminated and the access request is determined to be illegal. The error prompt message is an abnormal feedback signal generated by the system, which contains error - type identifiers (such as address - access violation), the virtual - address value that triggers the exception, and a timestamp, etc.

[0062] By dynamically responding to invalid configuration instructions and updating the second preset virtual address range in real time, the memory access policy can be flexibly adjusted during runtime. For example, when a memory security threat is detected, the attacked area can be quickly isolated, or the address space of a released task can be reclaimed during multitasking scheduling. This effectively prevents illegal access caused by outdated or incorrect address mapping relationships. Furthermore, to facilitate understanding of the implementation process of the present disclosure, embodiments of the present disclosure also provide an example for illustration: Requirement scenario: 1. The size of the address translation page table is 4KB; 2. The VA address range (the second preset virtual address range) requires 1GB; 3. The physically continuous larger space is 800MB, and other address ranges are fragmented in 4KB block (4KB block) ranges; 4. The starting VA address is 0x1000 0000 (the starting virtual address of the first preset virtual address range); 5. The continuous PA address is 0x8000 0000 - 0xb200 0000; 6. The fragmented address range is above the 0xa000 0000 address.

[0063] Configuration process: 1. The software configures the valid VA address range 0x1000_0000~0x4200_0000 (the first preset virtual address range); 2. The software configures the PA corresponding to 0x1000_0000 (the starting virtual address) as 0x8000_0000 (the starting physical address). A multi-level page table can be used, and only this one page table needs to be configured; 3. The software further configures the PA address corresponding to the VA from 0x4200_0000 to 0x5000_0000 (the PA acquisition of this space still uses the traditional MMU method).

[0064] Access process: 1. The VA value from the bus, such as 0x2089_8000 (the target virtual address), falls within the range of 0x1000_0000 - 0x4200_0000. Then, the corresponding PA 0x8000_0000 is obtained by accessing the MMU through the 0x1000_0000 VA. At the same time, by calculating: 0x2089_8000 - 0x1000_0000 + 0x8000_0000, the PA value of 0x9089_8000 (the target physical address) is obtained for use.

[0065] 2. If VA is greater than 0x4200_0000, forward the request to the MMU, and the MMU returns PA through a preset address translation mode.

[0066] Figure 2 The structural schematic diagram of a system for system memory management provided by an embodiment of the present disclosure.

[0067] As Figure 2 shown, it includes: an address translation module 21, a memory management unit 22, a processor 23, and a bus 24. The address translation module 21 is configured between the memory management unit 22, the processor 23, and the bus 24, and is respectively connected to the memory management unit 22, the processor 23, and the bus 24. The address translation module 21 is used to receive access information from the processor 23 and extract the virtual address information in the received access information, where the access information is used to access the system memory, and the virtual address information is used to indicate the target virtual address of the system memory. The address translation module 21 is further used to, when it is determined that the target virtual address is within a first preset virtual address range according to the virtual address information, determine the starting physical address corresponding to the starting virtual address in the first preset virtual address range from the memory management unit 22 according to a preset address mapping table, where the first preset virtual address range includes a starting virtual address and an ending virtual address, and the preset address mapping table at least includes the starting physical address corresponding to the starting virtual address. The address translation module 21 is further used to perform physical address calculation processing according to the target virtual address, the starting virtual address, and the starting physical address to obtain the target physical address corresponding to the target virtual address. The address translation module 21 is further used to transmit the target physical address to the bus 24. The bus 24 is used to access the system memory based on the target physical address and perform memory management on the system memory.

[0068] Among them, the system for system memory management realizes the efficient mapping and access optimization of the continuous physical address space through the hardware architecture innovation of introducing an address translation module. As the core component, the address translation module is physically deployed between the memory management unit (MMU), the central processing unit (CPU), and the system bus, forming a three-way communication link. The memory management unit is a hardware unit responsible for traditional virtual address translation, memory protection, and cache control, and it contains a translation lookaside buffer and page table traversal logic inside. The processor refers to the CPU core that executes computing tasks, and it generates access requests containing virtual addresses during operation, such as reading instructions or writing data. The bus is a data transmission channel connecting the processor, memory, and peripherals, and it transmits signals following a specific communication protocol.

[0069] After receiving the access information sent by the processor, the address translation module first parses the target virtual address in it. The access information is a complete request packet initiated by the processor containing the operation type (read / write), data size, and virtual address. For example, a command to read 32-bit data at the address 0x2089_8000. The target virtual address is the logical memory location specified in the request, and its value is dynamically generated during program execution. The address translation module determines whether the target virtual address falls within the first preset virtual address range through the internal status register or configuration memory. The first preset virtual address range is one or more continuous virtual address intervals predefined by the system. For example, 0x1000_0000 to 0x4200_0000, which corresponds to the same continuous space segment in physical memory. The preset address mapping table is a set of concise mapping relationships stored inside the memory management unit, only recording the starting virtual address of each continuous virtual address interval and its corresponding starting physical address. For example, the entry 0x1000_0000 → 0x8000_0000 means that the starting position of this virtual interval is mapped to the physical memory 0x8000_0000.

[0070] If the target virtual address belongs to the first preset virtual address range, the address translation module sends a query request for the starting virtual address to the memory management unit. For example, for the target address 0x2089_8000, the module first confirms that it is within the range of 0x1000_0000 to 0x4200_0000, and then queries the MMU for the starting physical address 0x8000_0000 corresponding to 0x1000_0000. The memory management unit only needs to return the mapping relationship of the starting address during this process, without traversing the entire page table hierarchy. The address translation module then performs physical address calculation, adding the difference between the target virtual address and the starting virtual address (such as: 0x1089_8000) to the starting physical address (0x8000_0000) to generate the final target physical address 0x9089_8000.

[0071] The calculation process is implemented through dedicated hardware circuits (such as subtractors and adder chains) to ensure that the operation is completed within a single cycle. Finally, the target physical address is transmitted to the memory controller via the bus. The bus accesses the corresponding physical memory unit according to the address signal and performs data read and write operations. The memory management function is executed synchronously during this process, including checking the access rights of the physical address, updating the status flags of the cache lines, and handling address alignment exceptions.

[0072] Through the hardware-level mapping optimization of the address translation module, the computational load of the traditional MMU in the continuous address translation scenario is significantly reduced. For a long continuous virtual address range, the address translation module only needs to query the starting address once to cover the entire range, avoiding the latency and storage overhead of the traditional page table hierarchical query.

[0073] Corresponding to the above method of system memory management, the present invention also proposes a device for system memory management. Since the device embodiment of the present invention corresponds to the above method embodiment, the details not disclosed in the device embodiment can be referred to the above method embodiment, and will not be elaborated in the present invention.

[0074] Figure 3 The structural schematic diagram of a device for system memory management provided by an embodiment of the present disclosure is shown in Figure 3 as follows, including: An extraction unit 31, configured to extract virtual address information from the received access information, where the access information is used to access the system memory, and the virtual address information is used to indicate the target virtual address of the system memory; A determination unit 32, configured to, when determining that the target virtual address is within a first preset virtual address range according to the virtual address information, determine the starting physical address corresponding to the starting virtual address in the first preset virtual address range according to a preset address mapping table, where the first preset virtual address range includes a starting virtual address and an ending virtual address, and the preset address mapping table at least includes the starting physical address corresponding to the starting virtual address; A calculation unit 33, configured to perform physical address calculation processing according to the target virtual address, the starting virtual address, and the starting physical address to obtain the target physical address corresponding to the target virtual address; A processing unit 34, configured to access the system memory based on the target physical address and perform memory management on the system memory.

[0075] The device for system memory management provided by the present disclosure extracts virtual address information from the received access information, where the access information is used to access the system memory, and the virtual address information is used to indicate the target virtual address of the system memory; when it is determined according to the virtual address information that the target virtual address is within a first preset virtual address range, determine the starting physical address corresponding to the starting virtual address in the first preset virtual address range according to a preset address mapping table, where the first preset virtual address range includes a starting virtual address and an ending virtual address, and the preset address mapping table at least includes the starting physical address corresponding to the starting virtual address; perform physical address calculation processing according to the target virtual address, the starting virtual address, and the starting physical address to obtain the target physical address corresponding to the target virtual address; access the system memory based on the target physical address and perform memory management on the system memory. Compared with the related art, the embodiment of the present disclosure can improve the conversion efficiency from virtual address to physical address by quickly returning the conversion relationship of virtual addresses within a specified range to physical addresses, and there is no need to configure the translation page table according to the MMU granularity, which can reduce the waste of storage space and improve the address conversion efficiency.

[0076] Further, in a possible implementation manner of the embodiment of the present disclosure, as Figure 4 shown, the device further includes: A conversion unit 35, configured to, when it is determined according to the virtual address information that the target virtual address is not within the first preset virtual address range, perform physical address conversion processing according to the target virtual address through a preset address conversion mode in the memory management unit to obtain the target physical address.

[0077] Further, in a possible implementation manner of the embodiment of the present disclosure, the determining unit 32 is further configured to determine whether the target virtual address is within a second preset virtual address range according to the virtual address information; The determining unit 32 is further configured to, when it is determined that the target virtual address is within the second preset virtual address range, determine whether the target virtual address is within the first preset virtual address range according to the virtual address information; The determining unit 32 is further configured to, when it is determined that the target virtual address is not within the second preset virtual address range, determine that the target virtual address is incorrect and generate an error prompt message, where the second preset virtual address range includes the first preset virtual address range.

[0078] Further, in a possible implementation manner of the embodiment of the present disclosure, as Figure 4 shown, the device further includes: An acquisition unit 36, configured to acquire continuous physical address information in the system memory, where the continuous physical address information includes multiple segments of continuous physical addresses in the system memory, and the multiple segments of continuous physical addresses do not overlap with each other; A configuration unit 37, configured to perform virtual address range configuration processing on each of the multiple segments of continuous physical addresses to obtain target virtual address ranges, where the first preset virtual address range includes the target virtual address ranges respectively corresponding to the multiple segments of continuous physical addresses, and the multiple target virtual address ranges do not overlap with each other.

[0079] Further, in a possible implementation manner of the embodiments of the present disclosure, the configuration unit 37 is further configured to: Perform virtual address correspondence processing on a first starting physical address of a target continuous physical address to obtain a first starting virtual address, where the target continuous physical address is any one of the multiple segments of continuous physical addresses; Perform virtual address correspondence processing on a first ending physical address of the target continuous physical address to obtain a first ending virtual address; Determine the virtual address range between the first starting virtual address and the first ending virtual address as the target virtual address range, and store the first starting physical address and the first starting virtual address corresponding to the first starting physical address in the preset address mapping table.

[0080] Further, in a possible implementation manner of the embodiments of the present disclosure, the calculation unit 33 is further configured to: Perform an address subtraction calculation based on the target virtual address and the starting virtual address to obtain an address deviation; Perform an address addition calculation based on the address deviation and the starting physical address to obtain the target physical address.

[0081] Further, in a possible implementation manner of the embodiments of the present disclosure, the processing unit 34 is further configured to: In the case of obtaining an invalid configuration instruction, perform invalid processing on the second preset virtual address range to obtain an invalid processed second preset virtual address range; In the case of determining that the target virtual address is within the invalid processed second preset virtual address range, determine that the target virtual address is incorrect and generate an error prompt message.

[0082] It should be noted that the foregoing explanations of the method embodiments also apply to the devices of the embodiments of the present disclosure, and the principles are the same. They are not limited in the embodiments of the present disclosure.

[0083] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device, a readable storage medium, and a computer program product.

[0084] Figure 5 FIG. shows a schematic block diagram of an exemplary electronic device 500 that can be used to implement embodiments of the present disclosure. The electronic device is intended to represent various forms of digital computers, such as, for example, laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as, for example, personal digital assistants, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely exemplary and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0085] As Figure 5 shown, the electronic device 500 includes a device computing unit 501 that can execute various appropriate actions and processes according to a computer program stored in a ROM (Read-Only Memory) 502 or a computer program loaded from a storage unit 508 into a RAM (Random Access Memory) 503. In the RAM 503, various programs and data required for the operation of the electronic device 500 can also be stored. The device computing unit 501, the ROM 502, and the RAM 503 are connected to each other via a device bus 504. An I / O (Input / Output) interface 505 is also connected to the device bus 504.

[0086] Multiple components in the electronic device 500 are connected to the I / O interface 505, including: an input unit 506, such as a keyboard, a mouse, etc.; an output unit 507, such as various types of displays, speakers, etc.; a storage unit 508, such as a magnetic disk, an optical disk, etc.; and a communication unit 509, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 509 allows the electronic device 500 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0087] The device computing unit 501 can be various general and / or special processing components with processing and computing capabilities. Some examples of the device computing unit 501 include, but are not limited to, a CPU (Central Processing Unit), a GPU (Graphic Processing Units), various dedicated AI (Artificial Intelligence) computing chips, various device computing units running machine learning model algorithms, a DSP (Digital Signal Processor), and any suitable processor, controller, microcontroller, etc. The device computing unit 501 executes the various methods and processes described above, such as the method of system memory management. For example, in some embodiments, the method of system memory management can be implemented as a computer software program tangibly embodied in a machine-readable medium, such as the storage unit 508. In some embodiments, part or all of the computer program can be loaded and / or installed onto the electronic device 500 via the ROM 502 and / or the communication unit 509. When the computer program is loaded into the RAM 503 and executed by the device computing unit 501, one or more steps of the methods described above can be executed. Alternatively, in other embodiments, the device computing unit 501 can be configured to execute the aforementioned method of system memory management in any other suitable manner (e.g., by means of firmware).

[0088] The various embodiments of the systems and techniques described above in this document can be implemented in digital electronic circuitry, integrated circuit systems, FPGAs (Field Programmable Gate Arrays), ASICs (Application-Specific Integrated Circuits), ASSPs (Application Specific Standard Products), SOCs (System On Chip), CPLDs (Complex Programmable Logic Devices), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special or general programmable processor that receives data and instructions from a storage system, at least one input device, and at least one output device, and transmits the data and instructions to the storage system, the at least one input device, and the at least one output device.

[0089] The program code for implementing the methods of the present disclosure can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when the program codes are executed by the processor or controller, the functions / operations specified in the flowchart and / or block diagram are implemented. The program code can be executed entirely on the machine, partially on the machine, executed partially on the machine as an independent software package and partially on a remote machine, or executed entirely on a remote machine or server.

[0090] In the context of the present disclosure, a machine-readable medium can be a tangible medium that can contain or store a program for use by or in connection with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer disk, a hard disk, a RAM, a ROM, an EPROM (Electrically Programmable Read-Only Memory), or a flash memory, an optical fiber, a CD-ROM (Compact Disc Read-Only Memory), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0091] In order to provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (Cathode-Ray Tube) or an LCD (Liquid Crystal Display) monitor); and a keyboard and a pointing device (e.g., a mouse or a trackball), by which the user can provide input to the computer. Other kinds of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and the input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0092] The systems and techniques described herein can be implemented in a computing system including backend components (e.g., as a data server), or a computing system including middleware components (e.g., an application server), or a computing system including frontend components (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with embodiments of the systems and techniques described herein), or a computing system including any combination of such backend components, middleware components, or frontend components. The components of the system can be interconnected to each other by digital data communication in any form or medium (e.g., a communication network). Examples of communication networks include: LAN (Local Area Network), WAN (Wide Area Network), the Internet, and blockchain networks.

[0093] A computer system can include a client and a server. The client and the server are generally remote from each other and typically interact through a communication network. The client-server relationship is created by computer programs running on respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or a cloud host, which is a host product in the cloud computing service system, solving the defects of difficult management and weak business scalability existing in traditional physical hosts and VPS services ("Virtual Private Server", or simply "VPS"). The server can also be a server of a distributed system, or a server combined with blockchain.

[0094] It should be noted that artificial intelligence is a discipline that studies how to make a computer simulate certain thinking processes and intelligent behaviors of humans (such as learning, reasoning, thinking, planning, etc.), and it has both hardware-level technologies and software-level technologies. Artificial intelligence hardware technologies generally include technologies such as sensors, dedicated artificial intelligence chips, cloud computing, distributed storage, and big data processing; artificial intelligence software technologies mainly include several major directions such as computer vision technology, speech recognition technology, natural language processing technology, and machine learning / deep learning, big data processing technology, and knowledge graph technology.

[0095] It should be understood that various forms of the processes shown above can be used, reordering, adding, or deleting steps. For example, the steps recited in this disclosure can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and no limitations are imposed herein.

[0096] The above specific embodiments do not constitute a limitation on the protection scope of the present disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principle of the present disclosure shall be included within the protection scope of the present disclosure.

Claims

1. A method for system memory management, characterized in that Including: Extracting virtual address information from the received access information, where the access information is used to access the system memory, and the virtual address information is used to indicate the target virtual address of the system memory; When it is determined that the target virtual address is within the first preset virtual address range according to the virtual address information, determining the starting physical address corresponding to the starting virtual address in the first preset virtual address range according to a preset address mapping table, where the first preset virtual address range includes a starting virtual address and an ending virtual address, and the preset address mapping table at least includes the starting physical address corresponding to the starting virtual address; Performing physical address calculation processing based on the target virtual address, the starting virtual address, and the starting physical address to obtain the target physical address corresponding to the target virtual address; Accessing the system memory based on the target physical address and performing memory management on the system memory.

2. The method for system memory management according to claim 1, wherein After extracting the virtual address information from the received access information, the method further includes: When it is determined that the target virtual address is not within the first preset virtual address range according to the virtual address information, performing physical address conversion processing on the target virtual address through a preset address conversion mode in a memory management unit to obtain the target physical address.

3. The method for system memory management according to claim 1, characterized in that, After extracting the virtual address information from the received access information, the method further includes: Determining whether the target virtual address is within a second preset virtual address range according to the virtual address information; When it is determined that the target virtual address is within the second preset virtual address range, determining whether the target virtual address is within the first preset virtual address range according to the virtual address information; When it is determined that the target virtual address is not within the second preset virtual address range, determining that the target virtual address is incorrect and generating an error prompt message, where the second preset virtual address range includes the first preset virtual address range.

4. The method for system memory management according to claim 1, wherein Before extracting the virtual address information from the received access information, the method further includes: Obtaining continuous physical address information in the system memory, where the continuous physical address information includes multiple segments of continuous physical addresses in the system memory, and the multiple segments of continuous physical addresses do not overlap; Performing virtual address range configuration processing on each of the multiple segments of continuous physical addresses to obtain a target virtual address range, where the first preset virtual address range includes the target virtual address ranges respectively corresponding to the configurations of the multiple segments of continuous physical addresses, and the multiple target virtual address ranges do not overlap.

5. The method for system memory management according to claim 4, wherein The performing virtual address range configuration processing on each of the multiple segments of continuous physical addresses to obtain a target virtual address range includes: Performing virtual address correspondence processing on the first starting physical address of a target continuous physical address to obtain a first starting virtual address, where the target continuous physical address is any one of the multiple segments of continuous physical addresses; Performing virtual address correspondence processing on the first ending physical address of the target continuous physical address to obtain a first ending virtual address; Determine the virtual address range between the first starting virtual address and the first ending virtual address as the target virtual address range, and store the first starting physical address and the first starting virtual address corresponding to the first starting physical address into the preset address mapping table.

6. The method for system memory management according to claim 1, wherein The physical address calculation process according to the target virtual address, the starting virtual address, and the starting physical address to obtain the target physical address corresponding to the target virtual address includes: Perform an address subtraction calculation between the target virtual address and the starting virtual address to obtain an address deviation; Perform an address addition calculation based on the address deviation and the starting physical address to obtain the target physical address.

7. The method for system memory management according to claim 3, wherein The method further includes: In the case of obtaining an invalid configuration instruction, perform invalid processing on the second preset virtual address range to obtain the second preset virtual address range after invalid processing; In the case of determining that the target virtual address is within the second preset virtual address range after invalid processing, determine that the target virtual address is incorrect and generate an error prompt message.

8. A system for system memory management, characterized in that, The system includes: an address translation module, a memory management unit, a processor, and a bus. The address translation module is configured between the memory management unit, the processor, and the bus, and is respectively connected to the memory management unit, the processor, and the bus; The address translation module is used to receive access information from the processor and extract the virtual address information in the received access information, where the access information is used to access the system memory, and the virtual address information is used to indicate the target virtual address of the system memory; The address translation module is further used to, in the case of determining that the target virtual address is within the first preset virtual address range according to the virtual address information, determine the starting physical address corresponding to the starting virtual address in the first preset virtual address range from the memory management unit according to the preset address mapping table, where the first preset virtual address range includes a starting virtual address and an ending virtual address, and the preset address mapping table at least includes the starting physical address corresponding to the starting virtual address; The address translation module is further used to perform a physical address calculation process according to the target virtual address, the starting virtual address, and the starting physical address to obtain the target physical address corresponding to the target virtual address; The address translation module is further used to transmit the target physical address to the bus; The bus is used to access the system memory based on the target physical address and perform memory management on the system memory.

9. An electronic device, characterized in that, Includes: At least one processor; And A memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the method according to any one of claims 1-7.

10. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to execute the method according to any one of claims 1-7.

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